4-Switch Non-Inverting Buck-Boost: Seamless Crossover

A 4-switch non-inverting buck-boost keeps regulation when VIN crosses VOUT, avoiding polarity inversion and eliminating output glitches during buck ↔ blend ↔ boost mode changes. It targets sources with wide dynamics while offering higher efficiency than SEPIC/Ćuk in many mid-power ranges and simpler magnetics than SEPIC.

• Continuous regulation across VIN↔VOUT crossover (USB-PD sinks/sources, brown-outs, solar/battery).
• Higher efficiency vs SEPIC/Ćuk in many mid-power ranges; simpler magnetics vs SEPIC.
• Non-inverting output simplifies rail distribution and sequencing.
• Typical ranges: VIN 2.7–36 V (variants up to 60–100 V), VOUT 3.3–20 V, 1–20 A.

The power stage is an H-bridge of four FETs (input side HS/LS, output side HS/LS) with a single inductor between mid-nodes. Current sensing may use lossless DCR/RDS(on) or a shunt; control can be peak or valley current-mode with slope compensation. Adaptive dead-time minimizes shoot-through and body-diode conduction.

• Drivers: adaptive dead-time; bootstrap vs charge-pump for near-100% duty.
• Protections: OCP (valley/peak), OVP/UVP, OTP, short-circuit; optional front ideal-diode for reverse battery.
• Telemetry & timing: PMBus/I²C (if digital), PG chain, soft-start/tracking, pre-bias safe start.

The converter operates across three regions with a smooth blend near VIN ≈ VOUT, keeping the inductor current continuous and avoiding hard toggles. Mode selection is continuous: buck-dominant when VIN ≫ VOUT, boost-dominant when VIN ≪ VOUT, and a controlled blend around unity ratio.

• Buck-dominant (VIN ≫ VOUT): inductor charges from VIN side; discharges to VOUT side; duty follows VOUT/VIN.
• Boost-dominant (VIN ≪ VOUT): inductor stores energy on VIN side; delivers via output switches; duty follows 1−VIN/VOUT.
• Crossover blend (VIN ≈ VOUT): complementary gating keeps IL continuous; avoid discontinuities in current limit and error amp.

• Current-limit consistency: ensure IL clamp continuity across modes; no step loss of deliverable current at unity.
• Interleaving (multi-phase): reduce ripple and cross-over stress; improve transient and EMI margins.
• Dual compensation with cross-fade: blend gains across plant change; maintain phase/gain margin during transition.
• Pre-bias handling: prevent reverse discharge; apply blanking/sample windows during mode handoff.
• Adaptive dead-time: minimize shoot-through while limiting body-diode conduction near unity.

• Inductor (L): choose from ΔIL = 20–40% IOUT at nominal; verify L·di/dt at buck/boost extremes; keep ≥20–30% saturation margin worst case.
• Switching frequency (fSW): balance transient vs EMI/efficiency; check gate-charge and dead-time losses in both modes; consider spread-spectrum.
• FETs: RDS(on) for conduction, Qg/Qgd for switching; check SOA at low VIN/high I and during boost peaks; pick symmetric/asymmetric pairs by dominant mode.
• Dead-time: prefer adaptive; validate across temperature/process; trade shoot-through against body-diode conduction.
• Sense & compensation: slope comp ≥ 0.5–1× downslope (current-mode); compensate for plant changes across modes; ensure gain/phase margin in both corners.
• Input/Output caps: place ESR zero appropriately; RMS ripple is worst at input in boost and at output in buck; mix polymer/MLCC for stability and step response.
• Thermals: hotspots shift (LS FET in buck, HS FET in boost); balance inductor copper vs core loss; meet θJA budget with airflow.
• Soft-start & tracking: pre-bias safe start; PG window; coordinate ramps with upstream/downstream rails.
• Protections: valley current-limit for robust shorts; apply blanking during mode changes; decide hiccup vs latch by safety/availability goals.

Route for all three modes. Keep hot loops tight, sense lines quiet, and grounds unambiguous.

• Tight hot loops: buck/boost/blend loops differ; shrink each; minimize SW-node copper; shield sensitive traces.
• Kelvin sense: CS/ILIM to device pins; RC filters with matched routing; keep away from SW node and high dv/dt zones.
• Ground strategy: star AGND reference; join PGND↔AGND at a single point near the controller; keep high-frequency returns short.
• Snubbers & gate resistors: tame ringing; verify rise/fall symmetry across modes; split Rg (up/down) if needed.
• Spread-spectrum & input damping: compare EMI with/without; add small R or RC across Cin if LC is underdamped.

1. Crossover sweep: slowly vary VIN across VOUT at several loads; scope VOUT, IL, SW; no glitches, PG intact.
2. Load steps: 10–80% IOUT in buck corner, near crossover, and in boost; record undershoot/overshoot and recovery.
3. Startup & pre-bias: ensure no reverse discharge; ramp profile meets tracking requirements.
4. Protections: short-to-ground, OVP/UVP, thermal foldback; observe behavior during mode transitions.
5. EMI: CISPR 22/32 conducted/radiated; compare spread-spectrum on/off; verify input filter stability.
6. Thermals: IR maps at VIN min/max; check inductor, LS FET in buck, HS FET in boost.
7. Aging/soak: 48 h soak; temperature sweep −40…+85/105 °C; re-verify margins.

How do I guarantee glitch-free crossover at VIN ≈ VOUT?

Use blended mode near unity: gradually cross-fade duty between buck and boost while keeping the inductor current continuous. Enforce current-limit continuity and blank current-sense sampling during handoff. Validate with a slow VIN sweep at multiple loads, verifying no PG drop, zero output undershoot spikes, and stable loop gain margins around the boundary.

Valley vs peak current limit—what changes at the mode boundary?

Valley limits are more tolerant of short circuits and minimize overshoot when the switch node commutes; peak limits give tighter transient control but can step the available current at crossover. Choose one scheme and keep the clamp equivalent across modes, then verify with fast load steps and VIN sweeps close to unity ratio.

How do I tune dead-time without raising diode conduction loss?

Start with adaptive dead-time and trim until shoot-through disappears over temperature while minimizing body-diode conduction. Probe SW ringing and reverse-recovery at light and heavy loads in both buck and boost corners. If needed, split gate resistors for HS/LS to balance rise/fall symmetry through the crossover region.

How should I handle pre-bias start and avoid reverse discharge?

Sense output pre-bias and start with synchronous rectification disabled until the internal ramp overtakes VOUT. Add blanking around zero-cross events during mode detection. Confirm no negative current into the load with a high-impedance scope probe and replicate worst-case with hot VOUT and cold VIN swing conditions.

Why does input RMS current peak in boost mode?

In boost, input current is pulsed at a higher duty and ripple, raising RMS stress on Cin and upstream paths. Size Cin from worst-case boost I_RMS, include polymer plus MLCC mix, and evaluate heating at VIN minimum. Validate with current probe measurements and verify input filter damping to avoid peaking.

Does spread-spectrum affect control loop measurement accuracy?

Yes. Frequency dithering smears switching harmonics and can distort Bode injection readings. Disable spread-spectrum during loop measurement or synchronize to a fixed clock. After tuning, re-enable and re-check phase margin with a small-signal load step to confirm equivalent stability with dither active.

Which inductor core works best for wide VIN sweeps?

Choose a low-loss core with modest permeability shift over temperature; ferrite is efficient at higher fSW, powdered iron tolerates DC bias better. Check saturation at both corners with 20–30% headroom. Compare core versus copper loss using vendor curves and validate thermal rise at VIN min/max in steady load.

How do I manage PG and sequencing with downstream LDO/VRM rails?

Set PG thresholds with hysteresis and a minimum valid-time filter, then sequence rails using tracking or timed enables. Ensure downstream soft-start aligns with buck-boost ramp and pre-bias rules. Validate brown-out behavior by stepping VIN through the PG window while observing rail order integrity.

How should soft-start ramp address inrush in different modes?

Use a controlled ramp that limits peak inductor current and avoids saturating Cin or magnetic components, especially in boost at low VIN. Coordinate with current-limit thresholds and input source capacity. Record inrush with a shunt or Hall probe and ensure supply droop remains within upstream tolerances.

What sense filter RC values won’t destabilize current-mode control?

Keep the sense RC pole above the current-loop bandwidth but below the switching edge noise; typical time constants sit near several switching periods. Match differential routes and avoid SW coupling. Verify slope compensation is ≥ 0.5–1× downslope and re-check gain/phase at buck and boost extremes.

When should I prefer a 2-switch inverting topology for −V rails?

Choose 2-switch inverting when the negative rail is dedicated, regulation never crosses polarity, and efficiency at that load exceeds a 4-switch solution. It simplifies control and layout. If the rail must traverse VIN≈|VOUT| or share magnetics, stay with non-inverting 4-switch for smoother transitions.

USB-PD: how to maintain regulation through PDO changes?

Pre-bias the new target, blend modes near the anticipated ratio, and keep IL and duty continuous during contract renegotiation. Coordinate soft-start with PD controller timing and monitor PG. Test worst-case with rapid 5–20 V steps at multiple loads, confirming no droop-induced resets downstream.

Automotive crank: how do I ensure hold-up across cold-crank dips?

Size input capacitance and control limits to ride through 6–9 V dips while maintaining regulation. Validate ISO pulse profiles and check valley current-limit behavior. Combine with an ideal-diode front end or pre-regulator if required, and confirm PG continuity during extended transients and load dump tests.

How do asymmetric FET choices help thermal balancing?

Use lower R_DS(on) on the device that bears more conduction loss in the dominant mode—LS in buck, HS in boost—while keeping manageable Q_g. Tune gate resistors to equalize switching losses. Re-map hotspots with IR imaging at VIN min/max and rebalance if one device exceeds thermal budget.

EMI failures near switching harmonics—what should I probe first?

Start with the hot loop geometry, SW overshoot/ringing, and input filter damping. Add or tune RC snubbers, revisit gate resistors, and check ground returns. Compare spread-spectrum on/off scans and verify LISN stability; if peaks persist, reduce SW node copper and increase shielding over sense lines.

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