Architectures & bandwidth (SAR/Pipeline/Flash/Folding/TI-ADC/ΣΔ/Hybrid), front-ends & channel forms, sampling bands, resolution-speed tiers, interfaces & clocks, digital features, application patterns, and design hooks.
Architectures & Bandwidth
SAR ADC (Successive Approximation)
Low power, mid-speed, excellent DC specs and µs-class latency.
Pipeline ADC
10–250+ MSPS with moderate latency and background calibration.
Flash ADC
Ultra-high speed (>1 GSPS) at low resolution for scopes/eyes/trigger.
Folding/Subranging ADC
Speed–power balance, 8–12 bit @ hundreds of MSPS for radar/comms.
Time-Interleaved ADC (TI-ADC)
Interleave channels for higher rate; needs gain/offset/timing calibration.
Sigma-Delta ADC (High-Resolution)
16–24 bit with OSR + digital filtering for precision/low-bandwidth.
Delta-Sigma Modulator (Bitstream)
1-bit/multi-bit streams for external decimation; great for isolated sensing.
Hybrid / Pipelined-SAR
Marry SAR DC accuracy with pipeline speed for wideband precision.
Front-Ends & Channel Forms
T/H Front-End ADC
Wide input BW with driver matching and lower jitter sensitivity.
Simultaneous-Sampling / MxADC
Phase-aligned sampling and sync triggers for multi-phase systems.
MUXed SAR ADC
On-chip MUX with crosstalk/settling optimizations for sensor polling.
ADC with PGA
Programmable gain to match input ranges for precision front-ends.
Isolated ADC / Isolated ΔΣ Modulator
High CMTI/insulation for high-side HV and inverter measurements.
Shunt/Bridge Front-Ends
Direct shunt/bridge sensing with on-chip bias/excitation options.
Sampling Bands
RF-Sampling ADC
Direct RF to digital with built-in DDC/NCO for wideband comms.
IF-Sampling
Mid-band capture with jitter/image suppression for radar/instruments.
DC / Low-Frequency Precision
Low drift/noise with chopping and self-calibration for metrology.
Resolution & Speed Tiers
Ultra-High Resolution (24–32 bit ΣΔ)
Exceptional 0.1–10 Hz noise and drift for weighing/lab gear.
High-Speed Mid-Res (12–14 bit)
100 MSPS–multi-GSPS with front-end/clock/layout as key factors.
Mid-Speed 16-bit
100 kSPS–10 MSPS for control/measurement balance.
Low-Power Portable (8–12 bit ≤1 MSPS)
µW–mW class for battery-powered IoT/portable devices.
Interfaces & Clocking
SPI/I²C (SAR/ΣΔ)
Low-pin, easy routing for industrial/sensor nodes.
Parallel / LVDS
High-speed synchronous links with low-jitter transport.
JESD204B/C
Multi-channel serial, subclass alignment and SYSREF.
Clocking & Jitter
Phase-noise/jitter budgets, aperture jitter and clean distribution.
Digital Backend & Features
Digital Filters & Decimation
SINC/FFE, band-pass/notch options for ΣΔ and RF-sampling chains.
DDC / NCO / CFR Hooks
Frequency shift, decimation and channelization for SDR/comms.
Calibration (BG/FG)
Gain/offset/INL correction and TI-ADC mismatch fixes.
Trigger & Timestamp
Sync I/O, GPIO gate and PTP-aligned multi-card timing.
Linearity & Errors
INL/DNL, THD/SFDR, SNR/ENOB and drift/aging metrics.
Application-Focused
Energy-Metering ΣΔ
24-bit, zero-cross sync, PF/harmonics for utility meters.
Motor Control / PSU SAR
Sync sampling, low latency and OSR noise shaping for FOC/PID.
Precision Instrumentation
Ultra-low noise & drift for scales/thermocouples/bridges.
Imaging / Line-Scan
High BW, low FPN with column-parallel/SLVS-EC options.
Ultrasound / Acoustic AFE
Low-noise TIA + ADC arrays with beamforming sync.
Automotive (ASIL)
BIST, redundancy and diagnostics for EV/drivetrain/chassis.
Aerospace / Space-Grade
TID/SEE-hardened parts, isolation front-ends and wide-temp packs.
Design Hooks & Pitfalls
Reference & Buffering
Low-noise/low-drift refs and stable drivers under load/thermal steps.
Driver & Anti-Alias Filter
Bandwidth/Q, driver distortion & stability vs SNR/THD budgets.
Clocking & PCB Layout
Diff clocks, intact returns and smart ground partitioning/coupling.
Link Integrity
LVDS/JESD eye diagrams, EQ/CDR and Subclass-1 SYSREF alignment.
Synchronization
Multi-card/channel expansion with consistent timebases & triggers.
Calibration & Self-Test
Zero/gain/linearity hooks, built-in modes and factory test pins.
Thermal & Drift
Power spread and junction drift impacts on INL/SNR; airflow planning.
EMC/ESD & Protection
Input clamps/RC, TVS/CMCs and surge-proofing for long cables.
