Chip types & paradigms, product definition, front-end architecture, verification, back-end implementation, DFT/ATE, high-speed I/O, security & FuSa, package/system integration, manufacturing & reliability, software stack, key specs, design hooks, costs & program, and quick pairings.
Chip Types & Paradigms
Full-Custom / Semi-Custom
Transistor-level PPA vs standard-cell efficiency and schedule trade-offs.
ASSP (Application-Specific Standard Product)
Generalizable parts for verticals with lower NRE than custom ASICs.
SoC (System-on-Chip)
CPU/GPU/NPU/ISP integration; runs Linux/RTOS/bare-metal.
Analog / Mixed-Signal ASIC
Data-converter/PLL/LDO/driver co-design with digital.
Chiplet & Advanced Packaging
Die-to-die (BoW/UCIe/AXI-Stream), IP reuse and yield optimization.
Product Definition & Spec
Target Workloads
KPIs: throughput, latency and energy efficiency (TOPS/W, Gbps/W).
PPA Trade-offs
Frequency/voltage domains and process corners shaping PPA.
Cost & Yield
Die area, masks/MPW, packaging and test BOM impacts.
Compliance & Longevity
Auto/medical/telecom requirements and 10–15y supply plans.
Front-End & Architecture
uArch & HW/SW Partitioning
Accelerator vs software flexibility; pipeline, cache and NoC choices.
IP Selection
CPU/GPU/DSP/NPU/ISP/video/audio licensing and P/A/P models.
On-Chip Interconnect
AXI/CHI/NoC bandwidth, latency, QoS and coherency domains.
Memory Subsystem
SRAM/TCM/eDRAM, LLC sizing and DMA/cache coherency.
Clock & Power Architecture
PLLs/dividers, DVFS/AVS and multi-VDD with power gating.
Verification & Validation
Functional Verification (UVM)
Coverage goals with assertions and protocol checkers.
Formal Verification
Safety/deadlock/equivalence proofs via properties.
Perf/Power Modeling
TLM and cycle-accurate models with power vectors.
HW/SW Co-Verification
FPGA protos & sim models to co-bring up drivers/firmware.
Security Verification
Model SCA/glitch and validate attack surfaces.
Back-End Implementation
Logic Synthesis
SDC constraints, MCMM and UPF/CPF low-power intents.
Place & Route
Congestion control, CTS/skew and ECO strategies.
Static Timing Analysis
OCV/AOCV/POCV with clock uncertainty budgets.
Power/IR-Drop & EM
IR/EM screens with grid planning and decoupling.
Signal Integrity
Crosstalk/noise margins and delay variations.
Physical Verification
DRC/LVS/DFM/ANT with friendly layout practices.
AMS Co-Simulation
Layout parasitics vs behavioral checks for PLL/ADC/IO.
DFT & ATE
Scan & Compression
Coverage targets for stuck-at/transition faults.
BIST (MBIST/Logic BIST)
Memory/logic self-test including power-on checks.
Boundary Scan
IEEE 1149.1/1149.6 for board and system diagnostics.
ATE Patterns
Shmoo, yield analysis and speed/power binning.
High-Speed I/O
DDR/LPDDR Ctrl + PHY
Training/calibration with tight SI/PI budgets.
SerDes (PCIe/JESD/Ethernet/Die-to-Die)
CDR/equalization/JTOL and channel modeling hooks.
MIPI/Display/Camera/Audio
Prefer hard macros; keep CTS compliance hooks.
Low-Speed Interfaces
I²C/SPI/UART/I³C/CAN-FD for management/peripherals.
Security & Functional Safety
Secure Boot & Root of Trust
OTP/PUF keying, anti-rollback and lifecycle controls.
Crypto Engines
AES/SHA/RSA/ECC/TRNG acceleration for sessions/storage.
SCA/FI Hardening
Masking/jitter/balancing and redundancy checks.
Functional Safety
Lockstep, diagnostic coverage and FMEDA workflows.
Package & System Integration
Package Selection
Pin-map, thermal/warpage and stress considerations.
Package-Board Co-Design
PDN resonance, SSN/SSO and decoupling networks.
Advanced Interconnects
Interposers/TSV/RDL bandwidth density and latency.
Manufacturing, Yield & Reliability
Process & Mask Options
MPW choices, metal stacks and Vt variants.
Yield Ramp
FA, SPC/DOE and EFA/EBIRCH-based debug plans.
Reliability
HTOL/HAST/ESD/LU/TDDB/BTI with lifetime modeling.
Ecosystem & Supply Chain
Foundry/OSAT/materials multi-sourcing strategies.
Software & System Stack
Boot & Firmware
ROM/bootloader/BL31/UEFI with 2-stage load and DT.
OS & Drivers
Power/clock/IO/MMC/PCIe/Ethernet driver bring-up.
Middleware & Libraries
NN SDK, media/graphics/crypto mapping and scheduling.
Debug & Observability
Trace/JTAG/ETM, perf counters and field telemetry.
Key Specs & Selection
PPA Metrics
Dynamic/static power, peak/avg perf and area/cost.
Frequency & Voltage
Max frequency, DVFS range and efficiency knees.
Memory Subsystem KPIs
BW/latency, capacity, ECC and QoS budgets.
I/O Capabilities
PCIe lanes, DDR rate/width and SerDes speeds.
Security & FuSa
Boot chain, crypto/keying and diagnostic coverage.
Manufacturability & Test
DFM convergence, yield goals and test time/coverage.
Reliability & Lifetime
Target TJ, aging models and FIT rates.
Design Hooks & Pitfalls
Requirements Freeze
Lock PRD + use-cases + perf model to prevent spec drift.
NoC/DDR Mismatch
Peak bandwidth vs NoC/DDR limits—simulate early.
CDC/RDC Hygiene
Apply CDC rules and async FIFOs across the chip.
Low-Power UPF Consistency
Isolation/retention cells with power-aware sims.
IR/EM & PDN Early
Model peaks & SSO/SSN to avoid jitter-induced failures.
SerDes/JTOL Margins
Budget ref jitter/insertion loss; keep retimer/EQ options.
DFT Timing Intrusion
Iterate with synthesis/P&R to recover critical paths.
Firmware Sync
Co-develop HW/SW with FPGA protos to avoid slips.
Secure Manufacturing
HSM-based key injection, signing and rollback controls.
Cost & Program
NRE Costs
Masks/design/IP licenses, DV, ATE and certifications.
MPW & Engineering Builds
MPW for function, small eng lots for yield/package.
Ramp Plan
Pilot→PVT→PRQ with CPK/DOA/PPM quality gates.
Stepping & ECO
Reserve metal ECO and DFX; maintain compatibility matrix.
Quick Pairings
Edge AI SoC
Cortex-A + NPU, LPDDR4-ECC, PCIe Gen3, GbE, secure boot and DVFS.
Industrial Vision ASIC
CSI-2×N + ISP, DDR shaping, TSN MAC with security/time-stamping.
High-Performance Interface ASIC
JESD204C/PCIe Gen4 SerDes, low-jitter PLLs, DFT/PRBS and 2.5D.
Mixed-Signal Power Control
ADC/ΣΔ + hi-res PWM with safety island and FuSa docs.
