Automotive Supervisor for Cranking & Load Dump

Start from post-protection residuals: peak, duration, and slew. Map minimum operating voltage to Vth_low, add hysteresis sized to ripple plus measurement noise, and choose a deglitch window that exceeds the inter-spike spacing. For load dump, ensure reset delay covers regulator recovery. Prefer window supervisors when both undervoltage and overvoltage can appear during transients.

Use a budget that exceeds clock and power settling: tRST >= tPLL_lock + 3 to 5 times the clock-domain start time, plus regulator settling margin. Include any boot ROM or supervisor release delay. If the power tree reorders during cranking, gate release on both stable voltage and a valid clock-good indicator to avoid partial starts.

Choose open-drain when multiple domains or devices must share one reset line or when the receiving logic runs at a higher or different voltage. Pull up to the target I/O rail to ensure level compatibility. Prefer push-pull for single-domain, fast edges, and tight EMI control, but avoid back-powering and overvoltage on cross-domain paths.

Increase hysteresis to exceed ripple plus measurement noise, then apply a deglitch window longer than half the ripple period. Prefer integrating or K-of-M sampling rather than instantaneous comparison on slow slopes. During cranking, temporarily widen thresholds or extend delay, and release reset only after the regulator output is within margin and stable.

Size hysteresis to at least one and a half times the expected ripple plus noise bandwidth, yet keep it below roughly half of the available voltage margin above the true minimum operating level. Validate at temperature corners and under ripple-injected tests. If nuisance trips persist, combine moderate hysteresis with a short deglitch window rather than huge hysteresis.

Define a minimal record set and guarantee a hold-up window: rail_id, monotonic sequence or timestamp, state, reason, and CRC. Use a small buffer or capacitor-backed domain to complete the write. Without a secure real-time clock, rely on monotonic counters and rollover handling to maintain ordering and detect tamper or incomplete records.

Use a windowed digital filter or K-of-M sampling so isolated spikes do not trigger reset. Set the deglitch time longer than the inter-spike spacing observed after protection. Add a small series resistor and modest input capacitance to limit dV/dt injection, and confirm that the RC time constant remains well below functional delays.

Measure at -40, 25, 85, and 125 or 150 degrees Celsius using calibrated sources and the intended wiring harness. Record both threshold and reset timing drift, including pull-up effects on open-drain outputs. Accept parts only if worst-case results stay within data sheet limits and the aggregate margin still protects downstream clock and logic domains.

Only if the device provides independent sense inputs and distinct outputs or tags per rail. Avoid tying rails through a single reset where one domain’s noise induces false trips on the other. Prefer multi-channel window supervisors or separate devices, and aggregate power-good signals with explicit source labels to preserve diagnostic clarity.

Use a directed wired-AND or logic gate so power-good requires all contributing rails to be valid. Attach a source_tag to any fault path and record reason and sequence. Time-align signals with small delays to avoid race conditions, and avoid anonymous OR networks that make root-cause analysis hard during field returns or audits.

Estimate rise time from RPU times bus capacitance and target an RC that meets edge-speed and EMI goals. Typical 3.3 volt domains start between 4.7 and 22 kiloohms and tune by measurement. For long lines or larger fan-out, split the net or buffer the reset to control capacitance rather than forcing very small pull-up resistors.

Watch for looser threshold accuracy codes, missing AEC-Q100 references, different temperature grades, or taller packages that violate enclosure clearances. Scrutinize fixed delay codes, output type differences, and undocumented hysteresis. Unusual lead times, vague cross references, or relabeled lots are warning signs; demand traceable data sheets and parametric evidence before approval.