Battery Protector / Pack Switch — Safety Matrix, IC Selection & Validation

Shipping Mode (Ultra-low Standby)

Goal: keep pack quiescent current in the µA range while outputs are safely off. Allow controlled wake-up via charger plug-in, system signal, or momentary push-button.

• Standby Iq budget <= target µA; leakage audit across pack switch, sense, LEDs.
• Wake policy: single/dual trigger, debounce time, safe precharge before enable.

Pack Wake-up (Controlled Ramp)

Avoid inrush spikes and brown-out resets when leaving shipping mode. Use dV/dt control and a precharge path so the system rail rises smoothly before switching fully on.

• Size precharge (R/C) for worst-case cable inductance and C_sys.
• Scope peak inrush and V_gs/V_ds; verify no brown-out on downstream MCU.

Reverse Polarity (User Mis-plug)

Protect against accidental reversal at the pack or system connector. Use an ideal-diode path or back-to-back FETs with fast detection and a safe turn-off policy.

• Define detection threshold & debounce; avoid false trips during hot-plug transients.
• Thermal budget vs. conduction loss: R_DS(on), copper spread, θ_JA.

Backfeed Prevention (Ports & Multi-sources)

Stop unintended reverse current into the pack or into external ports (e.g., USB-C). Coordinate the ideal-diode and pack switch so only the intended path conducts.

• Set reverse current limit; validate under low-V pack and high-V external sources.
• Define fault policy: cutoff vs. retry vs. latch; log events for diagnostics.

OVP — Over-Voltage

Trigger: V_pack > V_OVP(th) (include temp & tolerance). Action: Off or Latch.

• Sense at battery side; define hysteresis & min on/off time.
• Scope charger overshoot; avoid false trip on wake.

UVP — Under-Voltage

Trigger: V_pack < V_UVP(th); allow rebound. Action: Delayed Off.

• Add debounce; choose wake via charger or system event.
• Log event for cycle-life analysis.

OCP — Over-Current

Trigger: I > I_OCP (avg/filtered). Action: Limit → Off.

• Kelvin sense; pick Rsense for signal-to-noise & loss.
• Thermal drift & tolerance stack-up.

Short-Circuit

Trigger: µs-scale detection (V_ds/V_sys drop). Action: Fast Off, often Latch.

• Comparator RC & hysteresis; gate discharge path.
• Validate with worst-case cable inductance.

OTP — Over-Temperature

Trigger: T_j/PCB over limit (on-die + NTC). Action: Derate → Off → Thermal Retry.

• Spread copper; design for θ_JA/θ_JC and airflow.
• Place sensor near hotspot (FET/driver).

Reverse Polarity

Detect mis-plug at pack/system connector. Action: Isolate via back-to-back FETs or ideal-diode.

• Fast decision; avoid damage to measurement front-end.
• Check conduction loss vs. protection strength.

Backfeed

Multi-sources/ports may reverse-feed the pack. Action: Enforce direction + cutoff.

• Set I_rev limit and verify with high-V external sources.
• Define cutoff vs. retry vs. latch policy.

Low-Side Single FET

Pros Simple gate drive, low loss. Cons Ground reference shifts; reverse/backfeed needs extra path.

• Check sense accuracy vs. ground lift.
• EMI: minimize gate loop; keep return tight.

Low-Side Back-to-Back FETs

Pros Blocks reverse cleanly. Cons Higher loss; ground still floating issues.

• Size Rds(on) ×2; thermal sharing matters.
• Define reverse-current detection & policy.

High-Side Single FET

Pros Stable measurement reference. Cons Needs bootstrap/charge pump.

• Confirm Vgs margin across pack voltage.
• Consider ideal-diode assist for ports.

High-Side Back-to-Back FETs

Pros Reverse block + stable ground. Cons Cost & drive complexity ↑.

• Symmetric routing; matched gate resistors.
• Verify V_ds, V_gs under surge events.

High-Side + Ideal-Diode Path

Pros One-way flow for ports/multi-sources. Cons Manage switchover chatter.

• Coordinate thresholds to avoid oscillation.
• Thermal: diode drop vs. FET conduction.

Voltage Thresholds

Choose OVP/UVP with margin/hysteresis; include divider tolerance, offset, and tempco.

• OVP near charge ceiling; UVP above rebound level.
• Set min on/off time; place RC close to comparator.

Current Limits & Short

Size Rsense for SNR and power; filter bandwidth vs. response; µs short cut-off.

• Kelvin routing; derate at temperature.
• Gate discharge path must be low impedance.

FET & Thermal

V_DSS surge margin; R_DS(on)(T) for loss; Qg vs. gate current for EMI/heat.

• Parallel with matched gates; symmetric copper.
• SOA vs. surge width; airflow & θ_JA.

Signals: PG / FLT / EN / WAKE

Open-drain outputs with pull-ups matched to MCU IO levels. Debounce and ESD at connectors.

• PG: asserts after V_sys stable for t_PG; use as downstream enable.
• FLT: any protection → low; clear by timeout/reset/cool-down.
• EN/WAKE: charger-in / system / push-button; 30–100 ms debounce.

States & Transitions

Ship → Wake → Normal; any protection can force Fault; recovery per policy.

• Ship: µA-level Iq; CHG/DSG off.
• Wake: precharge C_sys + dV/dt soft-start; raise PG after stable.
• Normal: matrix active; log events.
• Fault: Off/Retry/Latch; clearly defined exit.

EMC: keep signal returns short; isolate from gate-drive loop; add TVS where needed.

Sense & Kelvin

True Kelvin lines; RC at IC side; keep away from high dI/dt regions.

• Divider to local reference ground.
• TVS where cables/ports enter.

Gate Loop

Independent R_g per FET; fast discharge path; minimal gate-source loop area.

• Inner-layer or short outer-layer gate trace.
• Miller clamp/RC as needed.

Creepage & Clearance

Slots/keep-out at HV gaps; label distances; keep connectors away from board edge.

• Moisture/contamination margin by IEC category.
• Conformal coating notes if required.

Bench Setup

Program supply & load; real cable length/awg; scope with current & differential probes.

• Log ambient, unit ID, HW/FW versions.
• Probe points for I_inrush, V_GS, V_DS, V_sys.

Worst-Case Loads

Cold start + hot-plug; max C_sys and longest cable; high/low temperature repeats.

• Dynamic load steps; reverse/port backfeed scenarios.
• Monitor PG stability and fault logs.

Inrush & Surge

Precharge first; dV/dt soft-start; verify peaks and no brownout resets.

• Peak I_inrush < spec; V_GS/V_DS within limits.
• Adjust R_pre and R_g as needed.

ESD/Immunity

IEC 61000-4-2 points; EFT/Surge where applicable; device recovers automatically or via controlled reset.

• No permanent damage; faults logged correctly.
• PG/FLT behavior matches the policy.

Series · Pack Protector

OVP/UVP/OTP/OCP/Short with Latch/Retry policies.

Series · Pack Switch Driver

High-side gate driver for single/B2B FET; dV/dt & precharge friendly.

Series · Low Iq & Ship

Ultra-low standby with button/charger wake and PG/FLT lines.

Series · Pack Protector

Complete matrix with programmable thresholds.

Series · Ideal-Diode Controller

Backfeed stop for ports/multi-source, pairs with pack switch.

Series · Automotive Pack Switch

High-side B2B with PG/FLT and wake integration.

Series · Low Iq & Wake

Shipping µA, charger/button wake, debounce built-in.

Series · Pack Protector

OV/UV/OCP/Short/OTP with configurable debounce.

Series · High-Side Driver

Single/B2B FET drive; good for smooth dV/dt.

Series · Ideal-Diode

Backfeed prevention; pairs with port power mux.

Series · Compact Protector

Small-outline pack protector for space-limited designs.

Series · Auto Helper

Signal conditioning / diagnostics around PG/FLT.

How we help

• Cross-brand selection with action policy (Latch/Retry) and Low-Iq shipping.
• Pin-compatible alternates; quick checks on thresholds & thermal headroom.
• Risk notes on inrush, ESD, and SOA for your topology.

Before you upload

• Include PN, alt allowed, package, thresholds, current, and temperature range.
• Add port/OR needs (ideal-diode), PG/FLT signaling, and wake sources.
• Mention test status (inrush, ESD, short) if available.