How slow should soft-start be for analog, RF, or audio rails?

Limit ramp rate to avoid inrush, pops, and bias shocks: dv/dt ≈ I_SS/C_load or Vout/t_SS when a timer is given. Ensure the Buck has reached a stable level or PG before enabling the LDO. Observe device-specific ramp windows.

Which capacitor or ESR window matters for LDO stability?

LDOs require a specific output capacitance and ESR window for stable phase margin. Long traces and remote sense add ESL and ESR, shifting dynamics. If needed, add a feed-forward capacitor for mid-band gain but re-check stability. Keep MLCCs at pins with short returns.

What’s a sane split for FPGA rails such as CORE, PLL, and GT?

Drive CORE with a high-efficiency Buck and small LDO dropout; feed PLL or GT with higher-PSRR LDOs. Enforce sequencing and tracking windows across rails and prevent backfeed during power-down. Verify transients at realistic toggling loads.

Buck + Post-LDO: High-Efficiency Pre-Reg + Low-Noise Rail

Q: How do I estimate the LDO’s thermal loss quickly?

Use P_LDO ≈ (Vbuck − Vout) × Iout. Then approximate junction temperature: T_J ≈ T_A + P_total · RθJA. If margin is thin, reduce dropout, increase copper area, or choose a lower-Rθ package. Validate with steady-state heat measurements.

Q: How do I compute in-band output noise quickly?

Use a discrete-tone shortcut: combine the Buck’s switching tone and first harmonics through linear PSRR, then sum in RMS with the LDO’s integrated self-noise over your bandwidth. Apply ENBW corrections if using FFT measurements.

Q: What PSRR sweep and disturbance levels should I test?

Sweep across your application band, typically ten hertz to ten megahertz. Inject five to fifty millivolts RMS, record magnitude and phase, and note values at ten kilohertz, one hundred kilohertz, and one megahertz. Maintain short grounds and adequate averaging.

Pair a high-efficiency buck with a low-noise LDO to hit three goals at once: efficiency for thermal headroom, PSRR & noise suppression where it matters, and sequencing/tracking for reliable bring-up. Keep adequate headroom, space loop bandwidths, and verify with PSRR, noise, transient, and thermal tests.

Back to Buck / Boost / Buck-Boost Regulators

Quick Browse

Definition
Working Principle
Architectures
PSRR & Noise
Sequencing & Tracking
Design Rules
Application Scenarios
Layout & EMI
Validation & Measurement
IC Selection
FAQs & Submit Your BOM

Definition

Buck + Post-LDO is a two-stage supply where a high-efficiency Buck performs most of the voltage conversion and a low-noise LDO “cleans” the rail. The combo balances thermal efficiency with spectral cleanliness (PSRR & noise) and enables safe sequencing/tracking for sensitive digital/analog rails.

Compared with a single Buck, residual ripple/harmonics are attenuated before reaching PLL/SerDes/ADC-band sensitivities. Compared with a pure LDO drop, heat is reduced by keeping the LDO’s dropout small. This page focuses on the combination; high-current multiphase Buck or ultra-precision LDO topics live in sibling pages to avoid overlap.

Definition snapshot — why two stages balance efficiency, noise, and sequencing flexibility.

Headroom V_headroom = Vbuck − Vout ≥ Vdrop(max) + ΔV_transient

LDO thermal estimate P_LDO ≈ (Vbuck − Vout) × Iout

Working Principle

The Buck handles the heavy conversion from VIN, while the LDO linearly suppresses residual ripple and harmonics through its frequency-dependent PSRR. Total output noise equals the Buck ripple after PSRR plus the LDO’s self-noise integrated over the system bandwidth.

In frequency domain, Buck switching tone and harmonics dominate around its f_SW region; LDO PSRR is strong at low/mid bands and rolls off at high frequency. In time domain, align Buck/LDO soft-start and keep loop bandwidths de-coupled to prevent interaction. Maintain transient headroom so the LDO does not momentarily pass Buck ripple during load steps.

Top: VIN → Buck → LDO → LOAD. Bottom: Buck ripple across bands, LDO PSRR(f) roll-off, and residual ripple.

Ripple attenuation Vout_ripple(f) = Vin_ripple(f) · |PSRR(f)|

Noise composition (RMS) Vout_noise_rms ≈ √( ∫(Vin_ripple·|PSRR|)^2 df + ∫(Vn_LDO)^2 df )

Transient headroom Vbuck − Vout ≥ Vdrop(max) + ΔV_transient

Loop decoupling BW_Buck ≪ BW_LDO (or vice-versa) — avoid loop interaction

Architectures

Choose a topology that fits the rail set: single sensitive rail, split analog/digital rails, or multi-rail matrices for FPGA/SerDes. Keep headroom so the LDO never loses regulation during steps, and split thermal loss: the Buck handles conversion efficiency while the LDO uses small dropout to clean the band of interest.

Single-rail, split A/D, and multi-rail variants. Keep headroom and plan thermal split and PG/backfeed strategy.

Headroom Vbuck − Vout ≥ Vdrop(max) + ΔV_transient

Thermal split P_LDO ≈ (Vbuck − Vout) × Iout

Bandwidth spacing Aim for staggered loop bandwidths (Buck vs LDO)

Backfeed/ORing Use ideal diode/eFuse when rails can interact

PSRR & Noise Math

Model Buck residual ripple/harmonics multiplied by the LDO’s frequency-dependent PSRR, then add the LDO’s self-noise within the system bandwidth. Prioritize reducing Buck ripple first, and use the LDO to crush what remains in sensitive bands.

A practical shortcut uses discrete tones: f_SW and its first few harmonics. Convert PSRR to linear magnitude and combine in RMS. Remember that LDO high-frequency PSRR rolls off, so push energy out of sensitive bands (higher f_SW, LC/π filters) or into regions where PSRR is strongest.

Buck tones vs LDO PSRR(f). Compute residual per tone, add LDO self-noise over the bandwidth of interest.

Ripple attenuation (per tone) Vout_ripple(fi) = Vin_ripple(fi) · |PSRR(fi)|

RMS composition (discrete) Vout_rms ≈ √( Σ_i (Vri · |PSRR(fi)|)^2 + Vn_LDO_rms^2 )

LDO in-band noise Vn_LDO_rms ≈ √( ∫_BW (Vn_LDO(f))^2 df )

Quick intuition If Vin_ripple@fSW = 20 mVpp and PSRR@fSW = −40 dB (×0.01), residual ≈ 0.2 mVpp (tone only)

Sequencing & Tracking

Coordinate power-up/down so sources come first and loads follow. Match Buck/LDO soft-start (SS) slopes, chain Power-Good (PG) signals, and choose a tracking strategy (ratiometric or voltage tracking) that satisfies MCU/FPGA/SerDes/DDR timing windows.

Practical rules: keep the LDO’s dv/dt within the load’s safe ramp limit; assert PG_Buck → EN_LDO → PG_LDO → RESET_load with debounce; protect against backfeed on power-down using ideal diodes/eFuses or reverse-current-limited LDOs. Allow more margin at cold start and high load.

Use PG chain and matched soft-start to ensure “source-first, load-second”. Choose ratiometric or absolute voltage tracking based on device requirements.

Soft-start slope dv/dt_LDO ≈ I_SS / C_load or dv/dt_LDO ≈ Vout / t_SS

PG chain (order) PG_Buck → EN_LDO → PG_LDO → RESET_load

Sequencing window t(PG_upstream)+t_prop ≤ t(EN_downstream)

Power-down/backfeed Use ideal-diode/eFuse/QOD; prefer reverse-current-limited LDOs

Design Rules

Three hard rules: maintain headroom, keep the LDO stable (C/ESR/ESL window), and stagger loop bandwidths to avoid interaction. Check LC–LDO coupling and add damping if resonance appears.

Size headroom for worst-case temperature and load transients. Verify the LDO’s output capacitor and ESR window; long traces and remote sense add ESL/ESR and delay, reducing phase margin. Separate Buck and LDO crossover frequencies by at least 3–5× and consider small RC/Zobel damping at the LDO input when Buck LC is sharp.

Size headroom for worst case, keep LDO stable, separate loop bandwidths, and damp LC resonance to preserve phase margin.

Headroom (transient) Vbuck − Vout ≥ Vdrop(max) + ΔV_transient

Loop spacing BW_Buck and BW_LDO separated by ≥ 3–5×

LDO stability Respect LDO C/ESR/ESL window; check phase margin with long traces/remote sense

Junction temperature T_J ≈ T_A + P_total × RθJA

Application Scenarios

Buck + Post-LDO shines when you must balance efficiency, low noise/PSRR, and deterministic sequencing. Map rails to their targets (noise, current, headroom, timing) and choose single, split A/D, or multi-rail topologies accordingly.

Prioritize: ① reduce Buck residual ripple (frequency/LC/filter), ② use the LDO to crush in-band content, ③ enforce sequencing/tracking windows. Keep LDO dropout small to limit heat while preserving transient headroom.

Map each rail to target Noise, Current, Headroom, and Timing; choose single/split/multi-rail accordingly.

MCU / SoC

Small dropout, low Iq LDO; tie PG chain to reset.
Moderate ripple tolerance; focus on start-up timing.

FPGA / SerDes

CORE: high current with small dropout; PLL/GT: higher PSRR LDO.
Enforce tracking windows across rails.

PLL / Clock

Push f_SW or add LC/π so ripple falls into LDO’s strong PSRR band.
Consider small Cff; verify phase margin.

ADC / AFE

Split A/D rails; place MLCCs at pins.
Kelvin sense; keep analog returns quiet.

RF front-end

Low in-band noise; physical isolation and shielding.
Place LDO close to LNA/PA bias nodes.

Audio

Minimize 10 Hz–20 kHz noise; keep f_SW away from audio band.
Slow dv/dt to avoid pops and inrush.

Sensors / Precision

Prioritize low-frequency noise and drift.
Use RC prefilter and generous headroom.

Automotive / Industrial

Validate headroom at min VIN, cold crank; add TVS/EMI filter.
Ensure backfeed control and robust PG logic.

Noise budgetVout_rms ≈ √( Σ(Vri·|PSRR(fi)|)^2 + Vn_LDO_rms^2 )

LDO heatP_LDO ≈ (Vbuck − Vout) × Iout

Soft-startdv/dt_LDO ≈ Vout / t_SS

Layout & EMI

Minimize the Buck hot loop, protect LDO sensitive nodes, and join grounds at a clean star point. Route remote sense as paired traces and reserve probe pads for measurement. Dampen LC peaking if it couples with the LDO.

Place MLCCs at pins; keep the SW node compact and away from analog lines. Separate analog/digital returns before they converge. For EMI, place input filters near the connector and maintain a tight, ordered flow (connector → filter → regulator).

Shrink hot loop and SW copper, isolate LDO nodes, join grounds at a star point, route remote sense as paired traces, and reserve probe pads for measurement.

Minimize hot loop

Place Cin at FET pins; short, wide traces.
Keep SW copper compact and away from analog lines.

LDO stability & decoupling

Respect LDO C/ESR/ESL window; put MLCCs at pins.
Check phase margin with long traces or Cff use.

Grounding strategy

Separate analog/digital returns; join at star GND.
Keep high current away from quiet references.

Remote sense & probing

Kelvin at the load; route sense as tight pairs.
Provide Vout/GND pads or SMA; short ground springs.

Damping LC peakingAdd small series R–C (Zobel) at LDO input or raise ESR mildly

Probe disciplineKeep ground lead short; prefer coax/SMA for HF noise

Validation & Measurement

Prove the Buck→LDO combo with four checks: PSRR vs frequency, output noise (RMS), load-step transient, and thermal. Use disciplined fixtures, instrument bandwidths, and short ground paths to avoid measurement artifacts.

Sweep PSRR across the application band, integrate noise within the system bandwidth, characterize undershoot/overshoot and settling time on load steps, and validate temperature rise against your thermal budget. Record results in a simple table for VIN/VOUT/IOUT/Temp with PSRR@key f, Noise_RMS, ΔV/ts_settle, and hotspots.

_J ≈ T_A + P · RθJA; check margin

Use proper fixtures and bandwidths: sweep PSRR, integrate noise, step the load, and verify thermal margins. Keep ground paths short to avoid artifacts.

PSRR definition PSRR(dB) = 20·log10( Vin_disturbance / Vout_response )

Noise budget (RMS) Vout_rms ≈ √( Σ(Vri·|PSRR(fi)|)^2 + Vn_LDO_rms^2 )

Transient headroom Vbuck − Vout ≥ Vdrop(max) + ΔV_transient

Junction temperature T_J ≈ T_A + P_total · RθJA

IC Selection

Select the pair by Noise tier (Ultra-Low-Noise / Balanced / High-Efficiency) and Current tier (<300 mA / 300–1 A / >1 A). Pick the LDO for PSRR/noise in your sensitive band, then the Buck for efficiency, frequency, and interfaces (PG/EN/TRK). Verify headroom and LDO thermal loss.

Check compatibility: PG thresholds, enable logic, tracking pins, reverse-current behavior, QOD, and protections (UVLO/OVP/ILIM/OTP). For automotive, prefer AEC-Q100 variants and thermal packages with exposed pads.

Choose LDO by PSRR/noise in your band and Buck by efficiency/frequency/interfaces; verify headroom, thermal, and protections.

Thermal & headroom P_LDO ≈ (Vbuck − Vout) × Iout | Headroom ≥ Vdrop(max) + ΔV_transient

Interfaces Check PG/EN/TRK compatibility + reverse-current + QOD

Noise verification Verify PSRR@10k/100k/1M & noise density vs system BW

Automotive options Prefer AEC-Q100 variants & exposed-pad packages

FAQs

Short, field-tested answers for Buck + Post-LDO projects. Expand any item for practical rules, quick math, and links into deeper chapters.

What’s the practical headroom rule for Buck + LDO?

Keep sufficient headroom so the LDO never falls out of regulation during worst-case line/load steps. Use: Vbuck − Vout ≥ Vdrop(max) + ΔV_transient. Include cable/trace drops and low-temperature increases in dropout. Balance headroom against LDO heat rise. See Architectures and Design Rules.

How do I estimate the LDO’s thermal loss quickly?

Use P_LDO ≈ (Vbuck − Vout) × Iout. Then approximate junction temperature: T_J ≈ T_A + P_total · RθJA. If margin is thin, reduce dropout, increase copper area, or choose a lower-Rθ package. Validate with steady-state heat measurements. See Design and Validation.

Should I rely on PSRR alone to clean Buck ripple?

No. First reduce residual ripple at the source: raise switching frequency away from sensitive bands, tune LC or add a π-filter, and use synchronous operation. Then let the LDO’s PSRR remove in-band energy. High-frequency PSRR rolls off, so mixed strategies win. See PSRR & Noise Math.

Ratiometric vs voltage tracking—when should I use each?

Use ratiometric when multiple rails must rise proportionally, typical for SoC or DDR. Use voltage tracking when one rail must follow another’s absolute level, common for PLL/SerDes biasing. Coordinate PG → EN → PG → RESET and keep allowed timing windows. See Sequencing & Tracking.

How slow should soft-start be for analog/RF/audio rails?

Limit ramp rate to avoid inrush, pops, and bias shocks: dv/dt ≈ I_SS/C_load or Vout/t_SS when a timer is given. Ensure the Buck has already reached a stable level or PG. Observe device-specific ramp windows. See Sequencing.

How do I prevent backfeed during power-down?

Use reverse-current-limited LDOs, ideal-diode ORing, or eFuses on rails that can stay high while others fall. Provide quick output discharge (QOD) and ensure de-assert order: upstream PG drops before downstream enables. Verify with controlled power-down tests. See Sequencing and Design.

Which capacitor/ESR window matters for LDO stability?

LDOs require a specific output capacitance and ESR window for stable phase margin. Long traces and remote sense add ESL/ESR, shifting dynamics. If needed, add Cff for mid-band gain but re-check stability. Keep MLCCs at pins with short returns. See Design Rules.

Buck LC resonance couples into the LDO—how do I damp it?

Add a small series RC (Zobel) at the LDO input, slightly raise ESR, or reduce Q with additional damping. Stagger loop bandwidths by at least 3–5× to avoid interaction. Verify via load-step ringing and frequency response. See Design Rules.

How do I compute in-band output noise quickly?

Use a discrete-tone shortcut: combine the Buck’s f_SW and first harmonics through linear PSRR, then sum in RMS with the LDO’s integrated self-noise over your bandwidth. Apply ENBW corrections if using FFT measurements. See PSRR & Noise Math and Validation.

What PSRR sweep and disturbance levels should I test?

Sweep across your application band, typically 10 Hz to 10 MHz. Inject 5–50 mVrms, record magnitude and phase, and note values at 10 kHz, 100 kHz, and 1 MHz. Maintain short grounds and average sufficiently for repeatability. See Validation & Measurement.

Where should I place the LDO—before or near the load?

Place the LDO as close as possible to the sensitive load and route Kelvin sense pairs directly to the load pads. Keep the path away from the Buck’s SW node and hot loop. Separate analog/digital returns and join at a star point. See Layout & EMI.

How do I choose Buck switching frequency around sensitive bands?

Keep f_SW clear of audio, IF, and PLL bands. Raising frequency reduces magnetic size and can shift ripple into stronger LDO-PSRR regions. Consider spread-spectrum modes and additional LC/π filtering when needed. Validate with spectral measurements. See PSRR and Design.

What’s a sane split for FPGA rails (CORE/PLL/GT)?

Drive CORE with a high-efficiency Buck and small LDO dropout; feed PLL/GT with higher-PSRR LDOs. Enforce sequencing/tracking windows across rails and prevent backfeed during power-down. Verify transient behavior at realistic toggling loads. See Applications and Sequencing.

Balanced vs ultra-low-noise vs high-efficiency—how do I choose?

Ultra-low-noise suits PLL/RF/Audio—prioritize PSRR and noise, accept efficiency tradeoffs. Balanced fits mixed MCU/FPGA designs with tight headroom. High-efficiency serves high-current CORE rails—use minimal dropout and filtering for acceptable noise. Confirm interfaces (PG/EN/TRK/QOD). See IC Selection.

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