Remote Sense & Cable Drop Compensation
Measure at the load, not at the converter. Add clamped I×R compensation. Validate with 4-wire at the load pads.
- Remote differential Kelvin sense at the load pads
- Estimate line drop and add clamped I×R compensation
- Small, symmetric RC on sense pins; avoid SW polygon
- 4-wire and dynamic load validation (A/B on/off)
Definition & Principle
Remote Sense (RS): Differential, high-impedance sensing of Vload at the load pads via a Kelvin pair returning to the controller.
Cable Drop Compensation (CDC): A controlled I × Rline term added to the reference/error node, so the converter output rises just enough that Vload stays on target.
Line resistance (round-trip)
Rline ≈ ρ·L/A + Rconnectors
Setpoint with clamp
Vset = Vtarget + Iload·Rline, with ΔVcomp ≤ Clamp%·Vout
- Use differential remote sense; land on the actual load pads
- Keep the sense pair tight and shielded; avoid the SW polygon
- Start R=22–68 Ω, C=1–3.3 nF near the IC; corners outside inner-loop pole
- Clamp compensation to ≤4–6% of Vout; document setpoint and clamp
- Validate with 4-wire and dynamic steps at the load pads (A/B on/off)
Remote Sense Basics
- Prefer differential remote sense on cables/backplanes; single-ended only for very short, quiet runs.
- Kelvin pair: tight coupling, ground-shield corridor, no crossing of the SW polygon.
- Front-end limits: check CMRR, CMVR, Vos, and input bias; place small, symmetric RC at pins.
- Land the sense pair on the actual load pads; length mismatch ≤ 5 mm.
- Route as a tight pair over a continuous ground plane; keep a ground corridor.
- Do not cross the SW polygon; ≥ 2–3 mm clearance from SW copper.
- Paired vias, adjacent; no shared vias with load current.
- Series R: 22–68 Ω at pins; C: 1–3.3 nF to AGND, placed symmetrically.
- Single-point AGND–PGND tie near the controller sense pins.
Estimating Cable/Backplane Drop
Round-trip resistance
Rline ≈ ρ · L / A + Rconnectors
Setpoint with clamp
Vset = Vtarget + Iload · Rline, ΔVcomp ≤ Clamp%·Vout
Ballpark (Cu, one-way at 20–25 °C): 20 AWG ≈ 33 mΩ/m, 22 AWG ≈ 53 mΩ/m, 24 AWG ≈ 84 mΩ/m, 26 AWG ≈ 134 mΩ/m, 28 AWG ≈ 213 mΩ/m. Connector pair: 5–20 mΩ (new/clean).
Temperature drift: R(T) ≈ R25[1 + 0.0039·(T−25 °C)] → ≈ 0.39 %/°C.
- Pick Imax (worst DC current).
- Estimate Rline = 2·(ρ·L/A) + Σ Rconnector-pairs.
- Compute ΔV = Imax·Rline; if ≥ 1–3% of Vout → use RS/CDC.
- Set Vset with a clamp (e.g., ≤ 4–6% of Vout); document.
- Validate at the load pads: 4-wire + step loads; log A/B (RS/CDC off/on).
Example — 5 V @ 10 A; cable 0.5 m each way; 20 AWG (≈33 mΩ/m one-way). Round-trip Rline ≈ 2×0.5×0.033 = 0.033 Ω; add 10 mΩ connectors → 0.043 Ω. ΔV ≈ 10×0.043 = 0.43 V (8.6 %). RS/CDC clearly required; clamp ≈ ≤5 %.
Implementing Drop Compensation
- Prefer built-in features first (load-line/AVP, Vdroop, RS gain); record the final Clamp%.
- Use external I×R adder when the controller lacks features or for platform reuse.
- Clamp compensation to ≤ 4–6% Vout; enable RS first, then raise comp gain gradually.
Tuning Order
- Estimate Rline (incl. connectors & temp drift).
- Set clamp target (≤ 4–6% Vout at start).
- Enable RS only; verify loop margin.
- Raise I×R gain gradually; retest Bode/steps.
- Document final Clamp% and A/B logs.
Pitfalls
- Isense bandwidth too low → jittery comp.
- Clamp too high → light-load overshoot.
- Summing node adds pole near loop BW → margin loss.
Clamp: ≤ 4–6% Vout
Isense: shunt / DCR / Hall
Use built-in first: load-line / RS gain / Vdroop
Routing & Filtering Rules
- Kelvin twisted/diff pair over solid ground; no crossing of the SW polygon; keep ≥ 2–3 mm clearance.
- Symmetric RC at IC pins: R = 22–68 Ω series, C = 1–3.3 nF to AGND; corners outside inner-loop pole.
- Paired vias; no shared vias with load current; single AGND–PGND tie by the sense pins.
- Diff/Kelvin pair, tight and short; length mismatch ≤ 5 mm.
- Over a continuous ground plane; keep ≥ 2–3 mm from SW copper; no crossing.
- Paired, adjacent vias; no shared vias with load current paths.
- Series R: 22–68 Ω at pins; Shunt C: 1–3.3 nF to AGND (symmetric).
- Sense RC corner outside the inner-loop pole; verify phase margin (RS on/off).
Series-R: 22–68 Ω (pair)
Shunt-C: 1–3.3 nF (pair)
Clearance: ≥ 2–3 mm from SW copper
Mismatch: ≤ 5 mm length difference
Stability & Loop Interaction
- Place the sense RC at the IC pins, symmetric. Keep its corner outside the inner compensation poles and < fsw/10.
- Avoid creating an unintended inner loop with active buffers; keep the RS path passive and short.
- With AVP/Load-line, normalize I×R and AVP slopes into a single equivalent reference before checking phase margin.
Series-R: 22–68 Ω (at pins, symmetric)
Shunt-C: 1–3.3 nF to AGND (symmetric)
Corner: fRS_RC = 1/(2πRC) < fsw/10
- Phase margin with RS/CDC ON ≥ 45–60°; gain margin ≥ 6–10 dB.
- Load step: settling and overshoot no worse than RS-OFF baseline.
- RS fault (open/short): revert to local sense without oscillation.
Application Scenarios
Telco / Industrial Backplane
Benefit: offsets mΩ backplane + connectors; Risk: aging/oxidation shifts Rline, re-verify periodically.
Automotive Harness (12 V → PoL)
Benefit: holds ASIC rails across crank/jitter; Risk: harsh EMI—sense pair must use ground corridor and partitioning.
Server / FPGA / AI Boards
Benefit: big gain on 0.7–1.2 V accuracy; Risk: AVP interaction—sum slopes then check margin.
USB-PD Devices / Hubs
Benefit: adapts to cable/ PDO changes; Risk: I estimate errors → over-compensation, clamp tightly.
Robotics / Mobile Modules
Benefit: maintains spec after cord swaps; Risk: temperature rise changes R(T)—test hot.
Medical Carts / Lab Benches
Benefit: keeps setpoint with extensions; Risk: complex grounds—ensure CMVR window & CMRR margin.
Trigger: ΔVdrop ≥ 1–3% Vout
Clamp: ≤ 4–6% Vout (start small)
Validation: RS/CDC off/on, 4-wire, Bode + steps
Validation Playbook
- 4-wire at the load pads as truth source; share a reference timeline for scope & logger.
- Matrix: Iload (min/typ/max) × temp (cold/room/hot) × cable (short/long/aged) × CDC (off/on).
- Log Vload error, Comp% (ΔVcomp/Vout), thermal at cable/connectors, and pass bands.
Test Matrix
- Iload: min / typ / max
- Temp: −20 / 25 / +60 °C (example)
- Cables: short / long / aged
- CDC: off → on (gain steps)
Procedure
- Baseline: RS on, CDC off → static & 10→50→90% steps.
- Enable CDC; raise gain to meet band; re-Bode & re-step.
- Cable A/B; log ΔVdrop and Clamp%.
| Case | Cable | Iload | CDC | Vload Error (mV / %) | Comp% | Tcable/conn (°C) | Pass Band |
|---|---|---|---|---|---|---|---|
| Baseline | Short | Typ | Off | — | 0% | — | ±1–3% |
| Tune-1 | Long | Max | On | … | …% | … | Hit? |
Accept if within band and RS/CDC-ON phase margin ≥ 45–60°.
Layout Checklist (Copy-Paste)
- Sense pair coupling: tight diff/Kelvin; length mismatch ≤ 5 mm.
- No SW crossing: keep ≥ 2–3 mm from the SW polygon; route along a ground corridor.
- RC placement: 22–68 Ω series + 1–3.3 nF to AGND; symmetric; at the IC pins.
- AGND–PGND tie: single point near the sense/EA pins.
- Paired vias: adjacent; never share with load current paths.
- Fallback: provide jumper/0 Ω path to local sense; label RS/LS clearly.
Mini IC-Selection Pointers
Controllers (diff RS + programmable load-line / comp gain)
- TPS53667 / TPS53681 — multiphase, PMBus, AVP + diff RS.
- LM5146-Q1 — controller with flexible RS/CDC externalization.
- ISL68127 / ISL68224 — digital multiphase, PMBus, AVP/diff RS.
- NCP81233 / NCP81231 — multiphase with load-line options.
- NCP3235 — high-current sync buck (friendly to RS add-ons).
- MCP19124/5 — analog power + digital control, programmable droop.
- MCP16502 — multi-rail PMIC, RS-friendly distribution.
- VR5510 — automotive PMIC, multi-rail with robust telemetry.
- PF8100 — multi-rail PMIC with regulation features.
- STPMIC1 — companion PMIC, multi-rail remote sensing/tracking.
- L7987A — buck controller; pairs well with diff sense amps.
- MLX91220 / MLX91221 — isolated Hall current sensing for I×R chains.
Sense / Measurement (low-Vos)
- INA2180 / INA229 — dual & digital shunt monitors.
- INA828 — low-drift instrumentation amplifier.
- MCP6C02 / MCP6C04 — high-side current sense, low Vos.
- ISL28022 — current/voltage/power monitor.
- NCV21875 / NCS333 — precision op-amps, AEC-Q options.
- TSC2010 series — high-side current sense amplifiers.
- Use platform-matched INA-class monitors or PMIC telemetry.
Frequently Asked Questions
When is remote sense / cable-drop compensation “worth it”?
Use RS/CDC when expected drop at maximum load exceeds 1–3% of Vout, or when regulation at the load is mandated by specs or compliance. Start with a quick estimate: ΔVdrop = Imax·Rline (round-trip). If the result breaches your accuracy budget or brown-out margins, enable compensation and validate stability.
What is a sensible short-run cutoff where RS/CDC is unnecessary?
For harnesses under 0.3–0.5 m with low current such that ΔVdrop < 1% of Vout, local sense generally suffices. Still, reserve a jumper or 0 Ω option to upgrade later. If future peripherals raise current or cable length, you can enable RS/CDC without respinning the PCB.
How do I size Rline when current varies across modes?
Sweep load current and log Vload. Estimate Rline ≈ ΔV/ΔI over the region of interest, then add connector/contact resistance. Capture temperature by running hot-box tests and regressing R(T) = R0[1+αΔT]. Use the round-trip value in your I×R target and clamp calculations.
How should I include temperature derating for cables and connectors?
Copper’s temperature coefficient is about 0.0039/°C. Connector resistance also rises with heat and wear. Soak for 30 minutes at cold/room/hot, then measure 4-wire at the load. Fit R(T) and verify compensation across temperatures; reduce clamp if light-load overshoot appears at elevated temperature.
What clamp percentage is appropriate for I×R compensation?
Begin with ≤ 4–6% of Vout as a soft clamp on the compensation term. Tune to meet DC accuracy without provoking light-load overshoot. Always record A/B data: compensation off vs on, including transient peaks, settling, and steady-state error, before committing values to production firmware or trims.
Where do I place the sense RC without losing phase margin?
Put series 22–68 Ω and 1–3.3 nF shunts at the IC pins, symmetrically to AGND. Set the corner below fsw/10 and away from primary compensation poles/zeros. Keep the path passive and short; do not insert active buffers unless their bandwidth is well below loop corner and properly clamped.
How can I detect a broken or miswired sense lead safely?
Use window comparators or firmware checks on RS pins, add weak pull networks, and implement an RS_OK status. On fault, fail over to local sense and freeze compensation. Ensure the fallback does not oscillate by verifying phase margin with forced local sense during validation steps.
What about noisy environments such as automotive or USB-PD?
Route a tight differential/Kelvin pair along a ground corridor, avoid SW copper by ≥ 2–3 mm, and keep RC components at the IC pins. During PDO changes or crank events, use a strict clamp and log error vs time. If needed, insert small series damping at the summing node to tame ringing.
Can I combine AVP (load-line) with cable-drop compensation safely?
Yes. Normalize both as slopes versus load: AVP contributes a negative slope, I×R an upward slope. Sum them into an equivalent reference, then verify Bode plots and load-step results. Set AVP first for transients, add I×R gradually, and watch phase margin and light-load overshoot carefully.
Shunt, inductor DCR, or Hall: which current sense is best for CDC?
Shunts are accurate and wide-band but add loss; DCR is low-loss yet needs temperature compensation; Hall or CT provides isolation with modest bandwidth. Choose based on noise budget, isolation needs, and loop bandwidth, and retune the scaler and clamp after switching sense technology.
What sampling rate should I use to log load-voltage errors?
Use a rate that captures brown-outs and step edges cleanly. A practical guide is ≥10× the fastest event bandwidth you must observe. Synchronize scope and logger triggers to a shared marker, and apply pre-trigger history to diagnose cause-and-effect around PG, PLL, and load transitions.
How do I validate with different cables and connectors reliably?
Create a matrix: short/long/aged cables and at least two connector types. For each, sweep load, log ΔVdrop, compensation percentage, and cable/connector temperature. Accept only if all points fall within your ±1–3% Vout pass band and the compensated loop maintains ≥45–60° phase margin.
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