Capacitive/magnetic isolators, opto-replacements, multi-channel and low-jitter clock isolation; isolated interfaces (SPI/I²C/UART/RS-485/CAN/Ethernet/USB); isolated modulation/ADCs; gate drivers & isolated bias; isolated DC-DC; safety & compliance; key specs; design hooks; and quick pairings.
Digital Isolator Device Classes
Capacitive Digital Isolator
High speed/low latency with low power and strong CMTI for MCU↔AFE/driver control.
Magnetic / Inductive Isolator
Wide-temp stability with aging immunity and excellent transient robustness for industrial drives.
Opto-Replace Isolator
Optocoupler drop-in timing/pin compatibility with zero aging calibration for legacy upgrades.
Multi-Channel / Mixed Direction
2–8 channels, bi-dir mixes, independent/shared supplies and optional low-jitter clock lanes.
Low-Jitter Clock Isolator
<100s of fs jitter for JESD/ADC/DAC clock isolation.
Low-Power / Auto-Wake Isolator
µA sleep with automatic wake for battery/portable isolated nodes.
Isolated Interfaces
Isolated SPI / QSPI / OSPI
High-speed MOSI/MISO/CLK with multi-CS; for BMS and fast data-acq chains.
Isolated I²C
Bi-directional open-drain with stretch handling and UVLO fail-safe states.
Isolated UART / GPIO
Low-latency isolation with safe states for PLC/field I/O.
Isolated RS-485 / CAN / LIN
PHY+isolation in one; high CMTI with fail-safe receivers.
Isolated Ethernet PHY/Magnetics
Integrated transformers/CMCs simplify port EMC and isolation.
Isolated USB (2.0 FS/HS)
Data/VBUS separation for medical HMI and industrial service ports.
Isolated Modulation & ADC
Isolated ΔΣ Modulator
Bitstream output for use with external digital filters; motor phase/HV bus currents.
Isolated Differential Amplifier
High linearity and strong CMTI for inverter/drive measurements.
Isolated ADC
On-chip isolated digital interface simplifies sync/EMC for high-side sensing.
Gate Drivers & Isolated Bias
Isolated Gate Driver (IGBT/SiC/GaN)
Fast drive with Miller clamp, DESAT/SC protection and soft turn-off.
Dual / Half-Bridge Isolated Driver
Top/bottom interlocks, dead-time control, UVLO and per-side monitoring.
Driver with Integrated Isolated Bias
Built-in secondary bias/sync-rectification to simplify gate-drive power.
High-CMTI / High-dv/dt Driver
100–200 kV/µs-class immunity to suppress common-mode spike injection.
Isolated Power (DC-DC & Bias)
Flyback / QR Flyback
Wide-VIN with secondary regulation (opto or PSR) and auxiliary winding options.
Push-Pull / Half-Bridge / Full-Bridge
Medium-to-high power with sync-rect and low ripple for drive/control rails.
Transformer Driver for Bias
Drives tiny isolation transformers for ±5/±12/±15 V analog bias.
Isolated Power Module
Transformer+control+rectification integrated with creepage/clearance compliance.
PoE Isolated PD Converters
PD control plus isolated DC-DC; minimal BOM to pass 802.3 and EMC.
Milliwatt Isolated Bias
mW-class bias sources for isolated amps/comparators and tiny loads.
Safety & Compliance
Basic / Reinforced Insulation
Per VDE 0884-11/UL 1577/IEC 62368/60601-1 with defined VIORM/VIOTM.
Creepage & Clearance / Pollution Degree
PCB slots/coating and altitude derating for safe separation.
Impulse / Surge Withstand
10/1000 µs and 1.2/50 µs stress classes with clear test paths.
Fail-Safe State
Define UVLO/power-down defaults and diagnosable single-point failures.
Key Specs & Selection
CMTI & dv/dt
≥50–150 kV/µs for high-voltage switching environments.
Propagation Delay / Skew / Jitter
Tight channel matching for JESD/ADC/DAC clock and data timing.
Barrier Capacitance & CM Emission
Lower capacitive coupling to reduce EMI; tailor edge rates.
Working Voltage & Lifetime
VIORM with lifetime models (chemical/electrical treeing aging).
Power & Thermal
Bias efficiency/no-load loss; driver dissipation vs gate-charge.
ESD / Surge / EMC
Coordinate device ratings with port layout for system-level immunity.
Design Hooks & Pitfalls
Layout & Grounding
Strict primary/secondary partition; no return across gaps; use slots/guard rings.
Y-Cap & Leakage
Use safety Y-caps sparingly for EMC; watch leakage for medical/portable limits.
Power–Signal Co-Design
Regulate→isolate vs isolate→regulate trade-offs for noise/efficiency.
Sync & Timing
Match delays across channels; budget skew for JESD204 SYSREF/CLK paths.
dv/dt Injection & Protection
Minimize gate loops; add Miller clamp; keep current loops compact.
Thermal & Aging
Transformer heating/resin aging; design for power density and airflow.
Production Test & Docs
Hi-pot/partial-discharge tests, CTI, certificates and CB reports.
Fault & Black-Box
Log UV/OT/SC events for field diagnostics with latch/clear policy.
Quick Pairings
Motor / Inverter
Isolated gate driver + isolated ΔΣ modulator + small isolated bias.
BMS / HV Systems
Isolated CAN-FD + isoSPI/daisy chain with reinforced insulation & high VIORM.
High-Precision Sampling
Low-jitter clock isolation + FDA/isolated driver + low-noise isolated power.
Medical HMI
Isolated USB plus 60601-1 compliant power with leakage-current limits.
