Robustness & Compliance for eFuse/Hot-Swap/OR-ing

ESD is a charge event dominated by peak current and very short duration, while Surge carries far more energy and often couples through cabling and grounds. A design tuned only for low residual via a TVS may still overheat or overstress power devices during Surge. Validate both residual and energy window.

Place the ESD array pad-adjacent to the connector, keeping the loop length within a few millimeters. Parasitic inductance is roughly ~1 nH per millimeter, which directly adds overshoot at fast edges. Short, direct return to ground is as important as proximity; avoid meandering or crossing sensitive zones.

For most high-speed links, place the TVS closest to the connector pads to shunt fast transients with minimal inductance, then the CM choke. Upstream chokes may create additional residual if the path to ground is long. Balance SI needs with protection by selecting low-capacitance arrays and verified layouts.

Start with ILIM at peak load times a safety factor and ensure downstream SOA. Set dv/dt from permissible inrush and rail capacitance, then verify against EFT burst trains. If nuisance trips occur, slightly increase dv/dt, confirm short-trip thresholds, and verify that PG/FAULT semantics remain deterministic under bursts.

A practical starting window is 10–30 mV, tuned to source impedance, harness resistance, and thermal drift. Too small causes chatter under small disturbances; too large wastes headroom. Sweep with real wiring and measure reverse current and switchover time to confirm stable, single-edge transitions.

Pulses with steep edges and negative excursions—such as Pulse 1 and 3a—challenge reverse blocking. Also consider load dump variants where supply rises quickly. Characterize I_rev peak and t_sw under each case, ensuring thermal limits are not exceeded and no chatter occurs during recovery.

Use two-stage clamping for long cables, outdoor runs, or high-energy surge paths. A GDT diverts bulk energy and common-mode stress; a fast TVS limits residual on sensitive rails. Provide spacing, creepage, and follow-on insulation clearances appropriate to the GDT’s holdover and follow current behavior.

Probe at the port pad, the TVS ground pad, and the nearest ground stitching. Use the same reference as measurement ground. Compare V_peak and ringing while injecting near, mid, and far points. Larger loop areas increase overshoot and residual; photos with rulers document geometry for regression.

Set a margin target (e.g., 10–20%) on residual and energy windows, considering aging, temperature rise, cable variability, and material drift. Document exact setups and probe conditions so future regressions compare apples to apples rather than nominal Pass at a single fixture configuration.

Record CTI class, Pollution Degree, altitude correction, and minimum creepage/clearance. Fill the T3 table with measured values and photos including a scale. Link T3 to the change-control process so laminate, soldermask, or coating substitutions automatically trigger an insulation review and minimal regression.

You may skip the full matrix only when parameter parity is proven: equal-or-better V_peak residual, t_sw, and I_rev at the same injection points, plus unchanged layout geometry and T3 insulation factors. Even then, run the minimal regression set and attach side-by-side waveform evidence.

Use sufficient bandwidth, appropriate attenuation, and short ground loops; prefer differential probes for floating measurements. Keep sampling high enough to capture rise times without aliasing. Fix trigger modes and levels across runs so comparisons reflect the circuit, not changing measurement conditions.