SOA & Thermal: MOSFET Selection, Parallel, I²t

Why SOA Comes Before Steady-State Ratings

Move from a steady-current mindset to a SOA + thermal time-constant mindset. Short and repetitive pulses during hot-plug, capacitive inrush, or rising contact resistance must sit inside the device SOA and remain safe under Zθ(t)-based junction estimates—before any steady-state RθJA checks.

• Steady current ratings cover only the thermal steady limit; transients dominate real failures.
• Same RMS, different pulse width/duty → very different T_j peaks.
• Protection strategy must bind to SOA: ILIM (CC/foldback), I²t fast-trip, and thermal foldback.

Rule A — Check SOA first: SOA_margin ≥ 25% on worst pulse; then verify steady-state RθJA.
Rule B — Junction margin: Tj_peak ≤ Tj_max − 15°C (allowing process/ambient drift).
Rule C — Validate at extremes: narrowest pulse & highest duty points must pass.

Scope note: No basic definitions (see Basics). No OR-ing priority (see Ideal-Diode/OR-ing).

Map Real Pulses to SOA

Build a repeatable method to convert measured or estimated inrush/plug pulses into SOA coordinates and envelopes. Treat capacitive inrush as a two-segment event (spike + ramp), and prefer vendor Repetitive SOA curves when available.

• SOA layers: DC / Single Pulse / Repetitive Pulse; match your pulse width to the correct curve.
• Segment the waveform: spike (C/L injection) and ramp (Vout rise) → project both.
• If no repetitive SOA, use a conservative duty-based approximation, then confirm by lab limits.

Single-pulse projection:  (V_DS, I_D, t_pulse)  → compare to vendor SOA at that t_pulse.
Repetitive approximation (if needed):  I_eff ≈ I_peak · sqrt(D)   (conservative; defer to vendor Repetitive SOA).
Checklist: sweep t = {100µs, 1ms, 10ms, ...}; record worst-case SOA margin and duty/frequency.

Scope note: Detailed I²t dual-window and foldback live in their own sections; layout/thermal via design is covered later.

MOSFET & Controller Co-Selection

Turn device picking into an executable co-design flow: ensure VDS headroom, validate ID(pulse) against SOA, trade R_DS(on)-vs-T with thermal spreading, match Zθ_JC/JA and package to copper area, and bind controller capabilities (ILIM, I²t fast-trip, gate drive) to the worst pulses.

• VDS headroom ≥ 1.25 × V_bus,max; consider surge and reverse conditions.
• ID(pulse) couples to SOA with pulse width/duty; verify on the worst point from #soa-map.
• R_DS(on)-vs-T: lowest isn’t always coolest—spreading & package matter.
• Zθ path & package (QFN/LFPAK/DPAK) differ greatly; copper and via matrix dominate Rθ_JA.
• Controller: ILIM (CC/foldback/instant), I²t window, and gate drive current must align with device SOA.

Screening:
  VDS_min ≥ 1.25 × Vbus_max
  SOA_margin ≥ 25% on the worst pulse (width & duty)
Thermal/junction:
  Tj_peak ≤ Tj_max − 15°C (via Zθ(t) convolution); confirm steady-state RθJA
Trade-off:
  Slightly higher RDS(on) is acceptable if package + copper deliver lower ΔT (better spreading)
Gate drive sizing:
  I_gate,pk ≥ Qg / t_r,target  (use split RG and source resistor if dv/dt or ringing is an issue)
Bind protection to SOA:
  ILIM soft window + I²t fast-trip are set from the #soa-map worst point; log trips with timestamps

Scope note: Parallel current sharing lives in #parallel; detailed layout/thermal via design will be covered later.

Parallel Devices & Current Sharing

Make parallel FETs reproducible with a simple SOP: symmetric gate drive, source resistors with Kelvin sense, and thermal coupling. Validate under cold/hot and still/forced-air conditions; target ΔI/I ≤ 10%.

• Positive temp-co helps but doesn’t auto-share: Vth scatter and thermal path mismatch cause current hogging.
• Source resistors (mΩ) & Kelvin pick-off suppress hogging and measurement bias.
• Symmetric gate RC, equalized trace lengths; split RG if ringing/dv/dt issues arise.
• Thermal coupling: adjacent placement, shared copper, symmetric via fields.

First-order sharing error:
  ΔI/I ≈ ΔR/R + (TCR × ΔT)
Initial source resistor sizing:
  R_s ≈ ΔV_allow / I_branch   (start with ΔV_allow = 5–10 mV)
Gate timing symmetry:
  |Δt_gate| ≤ 10%  (referenced to rise time under actual load)

BOM constraint — Parallel FETs:
  • Must include source resistors + Kelvin sensing + symmetric gate RC
  • Target ΔI/I ≤ 10% under cold/hot and still/forced-air conditions
  • Layout requires adjacent placement, shared copper, symmetric via fields
  • Validation must include gate ringing capture and which branch trips I²t/foldback first

Scope note: I²t dual-window and thermal foldback are covered in their dedicated sections; layout/via density is expanded later.

Two-Window I²t Protection

Combine a soft window for capacitive charging/soft-start with a fast I²t window for hard faults. Set thresholds from the worst SOA point, then verify thermal behavior against Zθ(t).

• Constant-current window: allows inrush/soft-start to complete without nuisance trips.
• Fast-trip window: rejects very short, high-amplitude pulses by I²t.
• Telemetry: count and timestamp each window’s events, log I_peak and duration.

Budget (rolling window T_roll):
  Σ(I² · Δt) ≤ I²t_limit_total
Fast window (hard-short cut):
  I_peak² · t_peak ≤ I²t_fast  → if false, trip immediately
Soft window (inrush/soft-start):
  I_LIM² · t_softstart ≤ I²t_soft  → else foldback/timeout
Priority & logging:
  Fast window has higher priority; debounce ≤ a few hundred µs
  Log: window_type, timestamp, I_peak, t_event, Vbus, Temp, reason_code

Scope note: Foldback implementation detail is covered in its own section; layout aspects are deferred to the layout chapter.

Rθ and Zθ(t) Time-Domain Thermal Model

Convert power waveforms into junction temperature using a discrete convolution with Zθ_JA(t). Fit vendor curves with a multi-RC ladder, sample both P(t) and Zθ(t), then check T_j,peak and settling time.

• Do not use steady-state Rθ for transients—use Zθ(t) with appropriate sampling.
• Use 3–5 RC segments to approximate Zθ(t); publish the discrete table with Δt.
• Acceptance: T_j,peak ≤ T_j,max − Margin, with Margin ≥ 15–25 °C.

Core relation:
  Tj(t) ≈ Ta + P(t) ⊗ ZθJA(t)
Discrete convolution (Δt = 100 µs / 1 ms as needed):
  ΔTj[k] = Σ_{i=1..k} P[i] · (Z[k−i+1] − Z[k−i])
  Tj[k]  = Ta + ΔTj[k]
Peak criterion:
  Tj_peak = max(Tj[k]) ≤ Tj_max − Margin   (Margin ≥ 15–25 °C)

Scope note: PCB layout/via density and airflow modeling are detailed in the layout chapter; foldback control is addressed separately.

Thermal Foldback Strategy

Configure foldback as a three-tuple—trigger, hysteresis, cooldown—then bind state changes to PG/FAULT and telemetry. Keep enough thermal margin from SOA/Zθ(t) peaks so the loop is stable and auditable.

• Trigger: Tj_up; Recovery: Tj_down = Tj_up − Δ; Δ = 15–25 °C.
• Cooldown delay: t_recover ≥ 3 × τ_th to avoid hunting/chatter.
• Logging: stamp FB_ENTER / FB_HOLD / FB_EXIT with I-set step and reasons.

Thresholds:
  Tj_up = min( Tj_max − 20°C, Tj_peak_from_Zθ + 10°C )
  Tj_down = Tj_up − Δ,  where Δ = 15–25°C
Cooldown:
  t_recover ≥ 3 × τ_th   (τ_th from dominant Zθ(t) time constant)
Current steps:
  I_next = max( I_min, I_prev × k ),  k ≈ 0.7–0.85
Priority:
  I²t fast-window > Foldback > Soft-window
Audit log (required):
  ts, state(FB_ENTER/HOLD/EXIT), Tj, I_set, Vbus, Temp, reason_code, duration

Scope note: I²t windows and SOA checks are defined in their chapters; layout-dependent τ_th is detailed later.

Layout / Package & RθJA

Treat copper as the primary heatsink: spread heat with planes and a dense via field, choose thermally capable packages, isolate Kelvin sensing, and keep the gate network symmetric and decoupled from the power loop.

• Planes: top/bottom copper tied to exposed pad; stitch with a thermal via matrix.
• Packages: QFN (exposed pad), LFPAK large pads reduce RθJA vs small pads.
• Kelvin sense: dedicate the Rsense loop; land near component leads, not in the copper middle.
• Gate routing: star/equal-length; split RG if needed; avoid parallelism with high di/dt loops.

Thermal via matrix:
  pitch = 1.0–1.2 mm, drill = 0.30–0.35 mm, fully tiled under exposed pad (paste window per package note)
Copper area:
  ≥ 1000–2000 mm² aggregated top+bottom as a starting point (scale with power)
Kelvin sense:
  6–8 mil min width/spacing, dedicated return, avoid crossing current slots, take-off at Rsense leads
Gate network:
  equal length ±10%, star topology, minimum loop area; separation ≥ 1.5× trace width from power loop
Grounding:
  measurement ground island with single-point tie, away from switching nodes

Scope note: Thermal convolution and peak checks are handled in the thermal-model chapter; parallel sharing metrics are detailed in #parallel.

Validation Matrix

A minimal yet executable matrix covering single and repetitive pulses, hot-plug into capacitive loads, parallel imbalance, steady run, and degradation. Record waveforms and thermal data for every point, then check SOA margin, ΔI/I, and T_j,peak.

• Single pulse: t = 100 µs / 1 ms / 10 ms; I = 0.5× / 1× / 2× nominal inrush.
• Repetitive pulse: D = 1% / 5% / 10%, f = 1–10 Hz.
• Hot-plug capacitive: C = 100–4700 µF; cable length 0.2–1 m.
• Parallel imbalance: cold/hot × low/high airflow.
• Steady run: 30–60 min.
• Degradation: contact resistance +50% / +100%.

scene,t_us,I_ratio,C_uF,L_m,D_pct,f_Hz,Ta_C,airflow,VDS_pk,ID_pk,Vout_min,ILIM_trace,Tj_pk_C,SOA_margin_pct,deltaI_over_I_pct,fast_trips,foldback_count,ts_first,ts_last,notes

Scope note: Worst-pulse projection and thermal convolution live in their chapters; layout tags (copper/vias/airflow) come from the layout section.

BOM Hooks (Copy-Ready)

• SOA margin ≥ 25% under actual pulse/duty; peak Tj evaluated with Zθ(t). Provide the worst-pulse report.
• Enable dual-window I²t: constant-current soft window + fast-trip window. Log triggers with timestamps and reason codes.
• For MOSFET paralleling, use source resistors + symmetric gate RC + thermal coupling; target ΔI/I ≤ 10% across temp/airflow.
• Thermal foldback: ΔT = 15–25 °C; recovery delay ≥ 3× τ_thermal. Bind ENTER/EXIT states to PG/FAULT telemetry.
• RθJA verification: report temperature rise under declared copper/via/airflow; publish Zθ/Rθ references; steady run ≥ 30 min.
• Before cross-brand alternatives, update cloud-side semantics for PG/FAULT/foldback to keep the analytics schema consistent.

Scope note: These are enforcement clauses only; technical details live in their respective chapters to avoid overlap.

Seven-Brand Selection Rules

Use the unified rule-fields below to evaluate candidates across the seven core brands. We list representative part numbers per brand with a brief reason for inclusion; the full cross-brand tables live on brand-specific pages. Fields are aligned with SOA & Thermal policy for easy spreadsheet/JSON export.

Fields:
  Category (eFuse / Hot-Swap Ctrl / OR-ing FET Ctrl / Smart High-Side / SOA-MOSFET / Sensor-Companion)
  Vin/VDS Range · ILIM Strategy (CC/Foldback/Fast-Trip) · I²t Window(s)
  SOA (DC/Single/Repetitive) · Repetitive policy notes
  Thermal Features (foldback, temp pin, Tj class) · Zθ data availability
  Package & AEC (QFN/LFPAK/DPAK…) · AEC-Q100/-Q101 grade
  Telemetry/Interface (PG/FAULT, I²C/PMBus; semantics)
  Layout Notes (EP pad tie, via matrix pitch, Kelvin sense)
  Typical Use (hot-plug, OR-ing, parallel capability)

brand,category,vin_vds,ilim_strategy,i2t_windows,soa_policy,thermal_features,package_aec,telemetry,layout_notes,typical_use,rep_pn,why_selected

Frequently Asked Questions