123 Main Street, New York, NY 10001

Architectures (1-phase/3-phase SoCs, AFE+MCU, PQ/harmonics, sub-metering), current/voltage sensors (shunt/CT/Rogowski/Hall/fluxgate), measurements & accuracy, communications and security, power & hold-up, key specs, design hooks, applications, and quick cheats.

Architectures

Single-Phase Metering SoC

On-chip ΣΔ/SAR ADC + DSP for P/Q/S, kWh/kvarh, RMS, PF and line frequency; smart plugs and household meters.

Three-Phase Metering SoC

Synchronous sampling with phase compensation, phase-loss/sequence detection for industrial/utility meters.

Metrology AFE + MCU

Discrete metrology AFE plus comms/application MCU for protocol/security customization.

Current / Voltage Sensors

Shunt Resistor

High precision/low phase shift; needs isolation (iso-ADC/isolators). Power loss P=I²R.

Rogowski Coil

Wideband, non-saturating (output ∝ di/dt); needs accurate integrator for large/dynamic currents.

Hall / Fluxgate

Measures DC/low-frequency with isolation; higher BOM cost but versatile.

Measurements

Accuracy & Standards

Accuracy Class

Class 0.2S / 0.5S / 1.0 under IEC 62053 series and ANSI C12.20.

Dynamic Range

2000:1–10000:1; maintain error at low currents (e.g., 10 mA).

Safety / Isolation

Over-voltage categories, creepage/clearance and UL/IEC 62368/61010 compliance.

Comms & System

TOU / RTC

Multiple tariffs (peak/valley) with retained RTC over power-fail.

Security & Protection

Power & Hold-Up

Key Specs

ADC

Resolution (16–24-bit), ≥2–8 kS/s per channel, SINAD/ENOB and channel synchronicity.

Harmonics & PQ

THD, harmonic order support and windowing (e.g., 10/12 cycles for 50/60 Hz).

NVM

Endurance (write cycles), atomic commits on power-fail and long retention.

Design Hooks & Pitfalls

CT Saturation

Select burden/core to avoid distortion under harmonics/surges.

Phase Compensation

Voltage/current path delay mismatch → PF error; use on-chip correction plus field calibration.

AFE Layout

Kelvin connections, short loops and A/D ground partition; isolate mains crosstalk & HF noise.

Power-Fail Writes

PFAIL → debounce → atomic commit of key counters; ensure restart consistency.

Calibration Flow

Multi-point (current/PF/temp) → solve gain/phase/offset → lock & write-protect.

Application-Focused

EV Charger

Legal-metrology AFE + contactor control + OCPP comms + leakage/thermal monitoring.

PV / Storage

Four-quadrant metering + anti-tamper (bypass/reverse) + grid-tie interfaces.

Quick Cheats

CT Range

Secondary voltage Vsec=Ipri/N × Rburden; avoid core saturation.

Power & Energy

Active power P=⟨v(t)i(t)⟩; energy E=∫P dt (discrete integration in metering ICs).

Power Factor

cosφ=P/S; low-PF accuracy depends on low noise & phase correction.

Harmonic Windowing

Configure window length vs. Fs (e.g., 10/12-cycle windows for 50/60 Hz).