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Freq/Sync & Spread Spectrum for Buck/Boost Regulators

Quick Browse · Freq/Sync & Spread Spectrum

Use external sync and controlled spread spectrum to flatten EMI peaks and plan phase/frequency to avoid beat interference and audible noise—without sacrificing transient response or efficiency.

External Sync & Spread-Spectrum for Buck/Boost — labeled cover Shows a chip synchronized to an external clock, spectrum bands labeled Audio and AM, and a title panel listing External Sync, Spread-Spectrum and Beat Avoidance. Audio band < 20 kHz AM band 0.5–1.6 MHz External SYNC Freq/Sync & Spread Spectrum • External Sync (PLL lock, capture/hold-in) • Spread-Spectrum EMI (down/center, PR dither) • Beat Avoidance (phase → freq → spread)
Cover with labels: Audio band, AM band, External SYNC, and key bullets (External Sync, Spread-Spectrum, Beat Avoidance).

Introduction

Context

Modern systems combine multiple rails and clocks—MCU, FPGA, SerDes, PLL, and ADC—driven by buck/boost regulators. In tight layouts and shared harnesses, switching harmonics easily couple into clock trees and sensitive analog front-ends.

Problem Patterns

  • Beat/audible noise: the difference between rails’ switching frequencies falls into 20 Hz–20 kHz.
  • EMI peak stacking: line spectra from fixed fsw hit regulatory windows (QP fail).
  • Unstable lock: jitter/ppm mismatch causes drop-out and transient glitches.
  • Measurement friction: spread-spectrum complicates loop bandwidth and PM reads.

Objectives

  • Achieve stable lock-in with clear capture/hold-in margins.
  • Reduce EMI peaks via controlled spread without entering new sensitive bands.
  • Plan frequencies and interleaving to avoid beat interference.
  • Preserve transient response and efficiency under light/heavy loads.

What You Get

  • Principles: sync, spread, and beat—spectrum-first explanations.
  • Frequency Planning: windows to avoid (AM/audio/clock harmonics) and interleaving rules.
  • Spread Strategy: down vs center vs pseudo-random—depth/rate selection.
  • Validation: lab and chamber A/B checks (QP/AVG; conducted/radiated).
  • IC Selection: capability map placeholders; filled in later.
  • FAQs: 12–15 engineer-tone answers with JSON-LD.

Principles (Control & Spectrum Models)

External sync aligns switching to a clean reference, spread spectrum redistributes energy to lower EMI peaks, and careful interpretation of loop measurements keeps dynamics accurate under dither.

2.1 External Sync — PLL / Phase Detector Basics

  • Capture vs Hold-in: define frequency error tolerated to lock (capture) and drift tolerated while locked (hold-in).
  • Clock quality matters: honor reference tolerance (ppm/%) and jitter (RMS/pp) when selecting fsync.
  • Fan-out discipline: one master → multiple slaves requires buffering/termination to avoid reflections and dropouts.
  • Fallback policy: define unlock behavior—revert to internal osc, flag PG/INT, and re-lock strategy.
External Sync PLL Chain for Buck/Boost Regulators Blocks with labels: Reference Clock → Phase Detector → Loop Filter → Controlled Oscillator → Regulator. Arrows indicate the signal flow. Reference Clock / CLKIN Phase Detector / PFD Loop Filter (RC) Controlled Oscillator fSW / VCO Regulator Buck / Boost
External sync PLL chain: Reference Clock → Phase Detector → Loop Filter → Controlled Oscillator (sets fSW) → Regulator.

2.2 Spectrum View — Line Spectrum vs Spread Spectrum

Fixed switching produces discrete lines (fundamental + harmonics). With spread-spectrum, energy distributes over a band so quasi-peak readings fall while total energy remains similar. Choose down-spread or center-spread and set depth/rate to avoid sensitive windows.

Before/After Spectrum: Fixed Frequency vs Spread Spectrum Left panel shows discrete spectral lines at harmonics for fixed switching frequency; right panel shows a broadened band under spread spectrum with reduced quasi-peak. Amplitude Frequency Fixed frequency (lines) Spread spectrum (band) QP peak ↓ Discrete lines (fixed) Broadened band (spread)
A/B spectrum: fixed-frequency switching shows narrow lines; spread spectrum distributes energy into a broader band and reduces the quasi-peak reading.

2.3 Beat Interference — Envelope & Audible Band

When two rails differ by |Δf| within the audible band (< 20 kHz) or overlap AM windows, amplitude envelopes rise and fall audibly and EMI peaks stack over time. PFM/Burst modes aggravate this by drifting instantaneous frequency.

  • If |fsw1 − fsw2| < 20 kHz, adjust phase first, then frequency, then apply spread.
  • Avoid aligning beats with board reference clocks and SSC sidebands.

2.4 Loop Impact — Measuring Ts, ωc, PM Under Dither

  • Baseline first: characterize bandwidth/PM at fixed frequency, then validate with spread enabled using load/input steps.
  • Mind readout bias: sweep-based analyzers may under-read bandwidth under dither; prefer time-domain checks.
  • PFM/COT caveat: variable period breaks linear models—treat loop metrics as qualitative.

Frequency Planning & Phase Management

Pick a primary switching window that avoids sensitive bands, set interleaving phases, check harmonic/ subharmonic overlaps, and define light-load policies to keep audio quiet.

3.1 Choose the Primary Frequency

  1. List sensitive windows: audio (< 20 kHz), AM 0.5–1.6 MHz, board references (and ± tolerance).
  2. Pick a mid-band candidate inside the device range, reserving ±5–10% trim margin.
  3. Reserve spread depth: ensure planned down/center spread will not sweep into sensitive bands.
Frequency Planning Map: Avoid Audio & AM; Choose a Safe Window and Set Spread Diagram shows two sensitive bands (Audio <20 kHz and AM 0.5–1.6 MHz), a green candidate window for switching frequency, and two spread bars indicating center/down spread planning. Frequency → Audio < 20 kHz AM band 0.5–1.6 MHz Candidate window Keep ±5–10% margin Down-spread Center-spread
Windows map: avoid the Audio and AM bands, pick a green “candidate window,” then set spread as down or center with margin for tolerance and temperature drift.

3.2 Phase Interleaving (2/3/4/6 Phases)

Target lower input/output ripple by distributing phases evenly within the same voltage domain and separating sensitive analog rails from noisy neighbors.

  • 2 rails → 180°; 3 rails → 120°; 4 rails → 90°; 6 rails → 60°.
  • Prefer uniform phase spread; keep the rail nearest analog front-ends as phase-separated as possible.
Phase Interleaving: 2/3/4/6 phases with angles and ripple reduction Central ring shows 4-phase (90°) in blue and 3-phase (120°) as a ghost. Labels indicate common phase sets and the ideal input ripple factor ≈ 1/√N with a conservative ×0.8. Ripple ≈ 1/√N (×0.8 conservative) 4-phase: 90° 3-phase: 120° (ghost) Common phase sets 4 phases → 90° 2 phases → 180° 3 phases → 120° 6 phases → 60° N Angles Ideal ripple factor Conservative (×0.8) Notes 2 180° 0.707 ≈ 0.57 Mismatch/layout skew 3 120° 0.577 ≈ 0.46 Unequal rail loading 4 90° 0.500 0.40 Magnetics tolerance 6 60° 0.408 ≈ 0.33 Routing complexity
Phase interleaving: 2→180°, 3→120°, 4→90°, 6→60°. Ideal input ripple scales ≈ 1/√N (use ×0.8 as a conservative field factor for mismatch and layout).

3.3 Harmonics & Subharmonics — Avoid Overlaps

  • Check N × fsw and fsw / N (N=1…5) against board references and SSC sidebands.
  • Define a minimum separation rule (e.g., ≥ 30–50 kHz) between switching-related lines and critical clocks.

3.4 PFM / Light-load — Audio Quieting

PFM/Skip/Burst can drift into the audible band. Prevent coil/capacitor “chirp” with PWM-forced light load or by setting a minimum frequency/on-time when necessary.

  • Enable light-load PWM or specify a minimum fsw.
  • Add small output RC damping to tame high-Q coupling.
  • Tune inductor ripple factor (ΔIL) to balance losses and acoustics.
PFM / Light-load — Audio Quieting Labels show Min fSW, RC damping, and PWM-force to avoid audible chirp. Enable light-load PWM or set a minimum fSW. Add small output RC damping to tame high-Q coupling. Tune inductor ripple factor (ΔIL) to balance losses & acoustics.
Audio quieting tips: PWM at light load or min fSW, small RC damping, and ripple tuning.

Beat-Avoidance Flow

  1. Adjust phases (interleave / separate sensitive rails).
  2. Trim fsw by ±2–5%.
  3. Enable spread (prefer pseudo-random); set depth/rate.
  4. If required, move one rail to a different frequency window.

External Sync (Interfaces & Electrical Details)

Define a clean SYNC/CLKIN path, respect capture/hold-in limits and jitter budgets, distribute one master to many slaves correctly, and specify robust unlock/fallback behavior.

4.1 SYNC / CLKIN Interface Forms

  • Levels & thresholds: CMOS/TTL/open-drain; verify VIH/VIL, input clamp, and protection resistor.
  • Tolerance & duty: honor reference ppm/% and minimum tHIGH/tLOW (often 40–60% duty window).
  • Pull-ups/downs: open-drain needs external pull-up (to logic rail) sized for rise-time < device limit.
  • AC/DC coupling: AC across domains uses series C plus bias network; DC needs a solid ground reference.
SYNC/CLKIN Interface Options and Thresholds Three side-by-side panels with labels: CMOS/TTL thresholds, Open-Drain with pull-up, and AC-coupled with bias. Shows VIH/VIL bars, a pull-up resistor, AC coupling capacitor and bias/divider to meet the SYNC input window. CMOS / TTL Thresholds VIH(max) VIH(min) VMID VIL(max) VIL(min) GND Meet SYNC VIH/VIL window at target logic level. Open-Drain + Pull-Up Open-Drain VDD RPU SYNC Input Set RPU so rise time meets jitter spec and VIH margin. AC-Coupled + Bias CAC RB1 Bias Node RB2 SYNC Schmitt Choose Cac & bias to center the waveform within the SYNC VIH/VIL window.
Three SYNC/CLKIN options with labels: (1) CMOS/TTL thresholds with VIH/VIL markers, (2) Open-Drain driver with pull-up to VDD, and (3) AC-coupled input with bias network and Schmitt buffer.

4.2 fSYNC Tolerance & Jitter (Capture/Hold-in)

Operate within device capture/hold-in ranges and ensure the reference’s jitter (RMS/pp) does not exceed loop tracking ability. Respect minimum tHIGH/tLOW sampling constraints.

Parameter Unit Guideline Notes
Capture range % Start within ±1–2% of nominal Faster lock and fewer retries
Hold-in range % Keep drift < capture range Account for SSC if used
Jitter (RMS) ps / % Keep within loop tracking bandwidth Bandwidth shrinks at low fsw
tHIGH, tLOW min ns Meet sampling window (e.g., > 30–60 ns) Avoid too-narrow pulses
Capture/Hold-in Windows vs Jitter Envelope Diagram shows a center sync frequency fSYNC with a green capture window, a dashed hold-in window, and a gray jitter envelope trace. Labels indicate ±Δf and the relationship between jitter (RMS/pp) and the lock ranges. Frequency Hold-in window Capture window Jitter envelope (~RMS / peak-to-peak) Center: fSYNC −Δf +Δf
Capture window (solid green) sits inside the wider hold-in window (dashed). The gray trace shows the jitter envelope; keep jitter (RMS/pp) within the capture/hold-in ranges around the center frequency fSYNC.

4.3 Fan-out & Cascading (One Master → Many Slaves)

  • Prefer star with a clock buffer when traces are long or loads are many; avoid heavy capacitive stubs.
  • Use series or parallel termination to tame reflections and ringing at each branch.
  • Budget skew from length mismatch; keep return paths short and quiet.
SYNC Fan-Out: Star (Buffered) vs Daisy-Chain with Termination Left panel shows buffered star fan-out; right panel shows daisy-chain with end termination. Labels mark source, buffers/receivers, slaves, and terminator. Star (Buffered Fan-Out) SYNC Source Buffer Slave A Buffer Slave B Buffer Slave C Daisy-Chain (with Termination) SYNC Source Receiver Slave A Receiver Slave B Terminator RT Pro: matched delays, low crosstalk; Con: needs buffers / fan-out power Pro: simple wiring; Con: skew / reflections without proper RT
SYNC fan-out topologies: buffered star vs daisy-chain. Star drives each slave via buffers and matched paths; daisy-chain needs correct end termination to avoid reflections and skew.

4.4 Unlock Strategy & Relock Flow

  • Fallback to internal oscillator; decide soft-start vs immediate resume.
  • Indications: PG/Fault/INT events; log unlock thresholds and recovery time.
  • Relock policy: debounce, retry count/interval, and host coordination.
Timing Swimlane: Unlock → Fallback → Retry → Relock Three lanes labeled SYNC Status, Control State, and Telemetry/Logging. Bars show UNLOCK event, fallback window, retries with delay/backoff, and final relock. A monitoring bar spans the bottom lane. SYNC Status Control State Telemetry / Logging time → UNLOCK detected jitter / phase error > threshold Fallback to fINT Retry #1..#N Retry delay / backoff Relock Monitor PG / faults / temp / VIN / event count
Swimlane with labels: SYNC Status shows UNLOCK; Control State moves through fallback, retries, and final relock; Telemetry logs PG/faults, temperature, VIN, and counters across the monitoring window.

Spread-Spectrum Modes (Choices & Trade-offs)

Pick down-spread or center-spread, consider pseudo-random dither to avoid tonal artifacts, and tune sweep depth/rate to balance QP reduction with ripple/audio and measurement fidelity.

5.1 Down-spread

  • Only shifts lower; keeps upper bound fixed—good for conducted windows.
  • Ensure the lower edge won’t enter audio/AM or system harmonics.
  • Too deep may increase low-frequency ripple perception.
Down-Spread Spectrum: fixed upper limit, energy spreads downward A main band with a fixed upper edge, plus a broader band extending downward. Labels: Down-Spread, Fixed upper bound, Energy broadened downward, Center fc. Down-Spread (down only) Fixed upper bound Energy broadened downward Center fc
Down-spread keeps the upper bound fixed while spreading energy to lower frequencies; the center frequency fc shifts only downward.

5.2 Center-spread

  • Symmetric around the center; often lowers peaks more uniformly.
  • Both edges must avoid sensitive bands; consider coexistence with SSC.
Center-Spread: symmetric broadening around nominal switching frequency Histogram bars centered at f_c with symmetric width indicating ±X% spread. Labels show Nominal f_c and ±X% bounds. Center-Spread (symmetric) Nominal fc −X% +X% Energy is spread around fc, lowering peak spectral density.
Center-spread: symmetric ±X% around the nominal fc, distributing energy and reducing peak spectral lines.

5.3 Pseudo-random Dither

  • Randomizes period to avoid tonal “sweep stripes”, stabilizing QP reduction over time.
  • Loop measurements by frequency sweep may read low; validate in time-domain with steps.
Pseudo-Random Dithered Switching Frequency Switching frequency vs time with center frequency and ±spread bounds. Solid polyline shows pseudo-random dither; dashed curve is a linear sweep reference. fSW time + spread (e.g., +5%) − spread (e.g., −5%) center fSW PR dither (preferred) Linear sweep (may create stripes)
Pseudo-random dither spreads energy around the center switching frequency without creating visible spectral stripes.

5.4 Sweep Rate & Depth

  • Depth: ±1–10% (or down-spread 1–10%). More depth → lower peak but higher edge-intrusion and ripple perception risk.
  • Rate: few hundred Hz to a few kHz. Too slow → audible “breathing”; too fast → instrument/loop readout bias.
  • Typical: mid depth (±3–6%) at ~0.5–2 kHz balances QP benefit vs artifacts.
Sweep Depth vs Rate — QP Benefit, Audio Risk, and Measurement Bias X-axis: sweep rate in Hz. Y-axis: spread depth in percent. Labeled regions show “Good QP reduction”, “Balanced”, and “Audio risk / measurement bias”. Diagonal guides illustrate increasing low-frequency content and measurement bias. Sweep Rate (Hz) Spread Depth (%) 0 100 300 500 1k 2k 5k+ ±1% ±2% ±3% ±4% ±6% ±8% ±10% Good QP reduction Balanced Audio risk / bias Shallow depth, moderate rate Medium depth & rate Deep + slow sweep → audible and measurement bias bias ↑ / low-freq content ↑
Depth vs rate map for spread spectrum: shallow/medium settings give QP benefit; deep & slow sweeps increase audio risk and measurement bias.

Design Rules (From Planning to Implementation)

Apply a three-step frequency rule, route SYNC cleanly, validate compensation with and without spread, quiet light-load acoustics, and co-exist with system clocks and USB-PD transitions.

6.1 Frequency Selection — Avoid Window → Tolerance → Margin

  1. Avoid windows: audio (< 20 kHz), AM 0.5–1.6 MHz, board refs/SSC sidebands.
  2. Add tolerance: device fsw error, temp drift, reference ppm/%, SSC amplitude → form an effective sweep region.
  3. Reserve margin: keep ±5–10% trim room for beat/harmonic avoidance and spread planning.
  • If center-spread ±X% is planned, ensure [fc(1−X), fc(1+X)] does not overlap forbidden bands; for down-spread, check the lower edge.
  • Prefer mid-band candidates; record 2–3 options before layout.
Frequency Planning Ruler Labeled Audio band <20 kHz and AM band 0.5–1.6 MHz, candidate center frequency with spread margins, and tick labels at 0.8/1.2/2.2 MHz. 0.8 MHz 1.2 MHz 2.2 MHz 3.0 MHz Audio band < 20 kHz AM band 0.5–1.6 MHz Candidate fc ≈ 1.2 MHz −5% margin +5% margin Center ±5%
Frequency ruler with readable labels: Audio band, AM band, a 1.2 MHz candidate, and center-spread ±5% margins.

6.2 Layout & Routing — SYNC Integrity

  • Separate SYNC from SW nodes and power loops; route on inner layer with solid ground reference.
  • Keep loops short; decouple near source and sink; avoid long parallel runs.
  • Use source-series or end termination on long/multi-branch lines to reduce reflections.
  • Across connectors/boards: AC-couple and establish bias; verify ground continuity.
SYNC Routing Layout Hints Shows a quiet SYNC path separated from the noisy SW area, with series termination, short return, and decoupling/ground zones labeled. Quiet SYNC corridor SW (noisy) area — keep away SYNC trace Series termination Decoupling / solid ground Short return path Keepout near SW node
SYNC routing tips: place the clock line in a quiet corridor, add series termination, keep short returns over solid ground, and keep clear of the SW node with a defined keepout.

6.3 Compensation & Verification

  • Baseline with spread off: Bode (ωc, PM) and load-step (ΔV, settling).
  • Then enable spread and re-check stability window and transient targets.
  • Verify PFM/CCM transitions at light/heavy loads; watch audible artifacts.
  • Beware sweep analyzers under dither; validate in time domain.
Metric Spread Off Spread On Tolerance
Bandwidth (ωc) — — ±10% (project)
Phase margin — — ≥ 45–60°
Load-step ΔV / settling — — per rail spec

6.4 Audio Noise Mitigation (Light Load)

  • Set minimum on-time or minimum fsw to avoid dropping into 1–20 kHz.
  • Force PWM in light load when acoustics matter more than efficiency.
  • Add small RC damping at output to reduce high-Q electro-mechanical coupling.
PFM Risk Band with Minimum fSW Guardrail Shows the audible band (1–20 kHz) as a risk zone, a green bar indicating the minimum switching frequency guardrail, and a grey curve illustrating a PFM trajectory that should stay above the guardrail. PFM Risk Band & Minimum fSW Guardrail Audible band 1–20 kHz Min fSW guardrail PFM trajectory (avoid) Keep PFM floor above the audible band or force PWM at light load to remove acoustic noise.
PFM risk band with labeled “Audible 1–20 kHz”, a green “Min fSW guardrail”, and a PFM trajectory—keep the floor above the audible zone or use Forced PWM.

6.5 System Coupling — USB-PD & SerDes SSC

  • Re-test transient/EMI at each USB-PD PDO; input voltage jumps can change control modes.
  • If board refs use SSC (±0.5–0.8%), ensure lock window > SSC amplitude; keep spread edges out of SSC sidebands.
  • Plan Boost (upstream) and Buck (downstream) frequencies before enabling sync to avoid tug-of-war.
USB-PD PDO Steps, SSC Sidebands, and Safe Switching Frequency Window Shows four USB-PD power steps (PDOs), an SSC sideband zone to avoid, and a central green safe fSW window for regulators. PDO1 — 5 V PDO2 — 9 V PDO3 — 15 V PDO4 — 20 V Avoid: SSC sidebands / ref-clock harmonics Safe fSW Window (plan center & depth to stay clear) Use down-spread near upper limits; check capture/hold-in
Coexistence map: USB-PD PDO step points, SSC sidebands to avoid, and a safe switching-frequency window for regulators.

Validation & Compliance (Near Field → Chamber)

Move from bench to chamber with consistent setups. Compare A/B curves, log lock status and environmental drift, and document repeatable criteria.

7.1 Near-End: LISN (Conducted) & Near-Field Scans

  • Use LISN + spectrum analyzer to observe line spectra vs spread bands (QP/AVG/PEAK).
  • Scan board with H/E probes; localize hotspots (SW node, inductor, slot gaps).
  • Keep identical RBW/step/detector for A/B comparability.
Conducted-EMI Bench: DUT → LISN → Spectrum Analyzer, with Near-Field Probe Labeled blocks show the measurement chain for conducted EMI: Device Under Test (DUT) connects to a LISN, then via coax to a Spectrum Analyzer. A near-field probe scans hotspots on the DUT. Flow arrows indicate the signal path. DUT Device Under Test LISN Line Impedance Stabilization Network Coax / Cables 50 Ω path to SA Spectrum Analyzer QP / AVG / Peak Near-Field Probe Hotspot scan (H-field) mains/DC feed LISN output coax input
Conducted-EMI bench chain: DUT → LISN → coax → Spectrum Analyzer, with a near-field probe for hotspot scanning on the DUT.

7.2 Chamber & Standards — QP / AVG / PEAK

  • Chamber tests: antenna scan, height sweep, cable layout per standard.
  • Detectors: QP for limit lines, AVG for duty-cycled content, PEAK for quick checks.
  • Pre-align bench settings (RBW, step, detector) to reduce surprises.
Detector Behavior Comparison: PEAK vs AVG vs QP Quasi-Peak shows the highest reading due to CISPR weighting; Average is lower; Peak is instantaneous. Labeled bars and legend explain the detectors. PEAK AVG QP Quasi-Peak PEAK Instantaneous maximum (fast detector) AVG Average over detector bandwidth QP — Quasi-Peak CISPR weighted detector (charge/discharge) Penalizes repetitive pulses → tends to read highest
Detector comparison: QP (Quasi-Peak) typically reads highest due to CISPR weighting; AVG is lower; PEAK shows instantaneous maxima.

7.3 Criteria — A/B Curves & Expectations

  • Target ΔQP improvement (e.g., ≥ 3–6 dB) with spread enabled.
  • No new out-of-band peaks exceeding limits.
  • Consistency across voltage/temperature/load corners.
EMI A/B Overlay — Spread OFF vs Spread ON Line plot comparing quasi-peak levels across frequency. The blue line (Spread ON) shows reduced peak amplitudes versus the gray line (Spread OFF). Peak level (QP) Frequency → Spread OFF (narrow lines, higher peaks) Spread ON (energy spread, lower peaks) Higher peak (OFF) Lower peak (ON)
A/B overlay: enabling spread-spectrum widens the spectrum and reduces quasi-peak amplitudes across frequency.

7.4 Run-Log & Traceability

Record lock status, unlock events, environmental drift, and configuration snapshots for every change of fsw/spread/phase.

Field Unit Example Notes
Lock status / recovery time flag / ms locked / 12 after jitter injection
fsw / spread (depth, rate) MHz / %, Hz 1.2 / ±4%, 1 kHz center-spread
Environment (VIN, load, temp) V, A, °C 12, 2.5, 45 at PDO #3
A/B result (ΔQP) dBµV −4.5 limit margin +3 dB

Multi-Rail Coordination (Phase, Beat, Hierarchy)

Distribute phases to lower input ripple, avoid low-frequency beats by order of operations (phase → frequency → spread), and define a clear Boost→Buck sync hierarchy to manage jitter transfer.

8.1 Phase Interleaving Matrix (2/3/4/6)

  • Evenly distribute phases within the same voltage domain: 2→180°, 3→120°, 4→90°, 6→60°.
  • Ideal input ripple RMS scales ~ 1/√N; apply a conservative factor (×0.8) for mismatch/imbalance.
  • Keep the rail closest to sensitive analog front-ends maximally separated in phase from noisy neighbors.
Phase Interleaving Wheel (2/3/4/6 phases) Wheel showing interleaving angles: 2→180°, 3→120°, 4→90°, 6→60°. Legend explains line colors and the ideal ripple scaling of 1/√N. Phase Interleaving Angles & ripple scaling (ideal RMS ≈ 1/√N) 0° / 180° 90° 270° 4-phase (90° spacing) 3-phase (120° spacing) 6-phase markers (60°) N=2 → 180°  ·  ideal RMS ≈ 0.707 N=3 → 120°  ·  ideal RMS ≈ 0.577 N=4 → 90°  ·  ideal RMS = 0.500 N=6 → 60°  ·  ideal RMS ≈ 0.408 Field tip: apply ×0.8 as a conservative mismatch factor.
Interleaving angles: 2→180°, 3→120°, 4→90°, 6→60°. Ideal input-ripple reduction scales as 1/√N (use ×0.8 conservatively for mismatch).
Phases (N) Ideal RMS Factor Conservative (×0.8) Notes
2 ≈ 0.707 ≈ 0.57 Mismatch and layout skew
3 ≈ 0.577 ≈ 0.46 Unequal rail loading
4 0.500 0.40 Magnetic tolerance
6 ≈ 0.408 ≈ 0.33 Routing complexity

8.2 Beat Avoidance — Phase → Frequency → Spread

  • If |fsw1 − fsw2| < 20 kHz or envelopes appear, first adjust phases.
  • If beats persist, trim one rail by ±2–5% within planned windows.
  • Finally enable spread (prefer pseudo-random) with controlled depth/rate.
Beat Avoidance Flow: Phase → Frequency Trim → Spread Three labeled steps to avoid low-frequency beats between rails: first interleave/phase shift, then trim one switching frequency slightly, finally enable pseudo-random spread with controlled depth and rate. 1) Phase Interleave rails 2→180°, 3→120°, 4→90° Goal: reduce input ripple overlap 2) Frequency Trim Offset one rail ±2–5% within plan window Keep clear of audio/AM & refs 3) Spread Enable PR dither Depth ±1–10%, rate 200 Hz–2 kHz Verify QP/AVG & acoustics
Beat-avoidance sequence: Phase (interleave) → Frequency Trim (±2–5%) → Spread (pseudo-random dither; set depth/rate).

8.3 Hierarchical Sync — Boost Master, Buck Slaves

  • Use a single master reference; avoid two masters pulling each other.
  • If the master uses SSC, ensure slave lock window > SSC amplitude and slave spread edges avoid SSC sidebands.
  • Distribute with buffered star fan-out; control return paths and bias when crossing boards.
Hierarchical Sync Topology: Boost Master → Buffered Fan-out → Buck Slaves A Boost converter acts as the master clock. Its SYNC signal is buffered in a star fan-out and distributed to Buck A/B/C slaves. Arrows show the SYNC routing. Labels indicate each role. Boost (Master) Master SYNC source SYNC Buffer SYNC Buffer SYNC Buffer Buck A (Slave) Locked to master Buck B (Slave) Locked to master Buck C (Slave) Locked to master Star fan-out Matched length Termination
Hierarchical sync: one Boost acts as the master clock, feeds buffered star fan-out, and three Buck converters lock as slaves. Labels mark each role and key routing hints.

IC Selection Guide (Fields & Buckets — Placeholder)

This section defines the field matrix and application buckets. Replace placeholder rows with real parts across seven brands when ready.

IC Selection Guide — Seven Brands / Representative Parts

Representative buck / boost / buck-boost devices that support External Sync and/or Spread Spectrum (where applicable). Replace dashes with project-specific values after datasheet review.

IC Selection Guide — Brand Tiles and Key Features Seven labeled tiles for vendors (TI, ADI/LTC, Infineon, Renesas, NXP, onsemi, MPS) and a wide tile for feature hints: External Sync, Spread-Spectrum, Phases/Interleaving, AEC-Q100. Texas Instruments Analog Devices / LTC Infineon Renesas NXP onsemi MPS Key Features • External Sync (capture/hold-in window, jitter tolerance) • Spread-Spectrum (down / center, pseudo-random dither) • Phases & Interleaving (1/2/3/4/6), AEC-Q100 options
Vendor tiles (TI, ADI/LTC, Infineon, Renesas, NXP, onsemi, MPS) and a feature strip highlighting External Sync, Spread-Spectrum, and Interleaving/AEC-Q100.
Brand Part Topology External Sync Spread Type Phases Light-load Mode fsw Range (MHz) ton,min (ns) Unlock Strategy AEC-Q100 Notes
Texas Instruments LM5143 (Q1) Buck Controller (Dual) Yes Option (Spread) 2 (multiphase capable) FPWM/Auto — — Fallback/INT Yes (Q1) 90° phase outputs
Texas Instruments LMR38020 / LMR38015 Buck (Integrated) Yes Spread (Option) 1 PFM/FPWM — — PG/INT — Wide VIN
Texas Instruments LM5141-Q1 Buck Controller Yes Spread (Option) 1 (multiphase via sync) PFM/FPWM — — PG/INT Yes (Q1) Automotive AM focus
Analog Devices (LTC) LTC7872 Multiphase Buck Controller Yes (SYNC) Spread via SYNC option Up to multi-phase FPWM/Auto — — PG/INT — SYNC=V5 → Spread mode
Analog Devices (LTC) LTC7878 Buck-Boost Controller Yes (100–600 kHz) — Multi-phase capable Auto/FPWM — — PG/INT — Wide power stages
Infineon (OPTIREG) TLS4125D0EPV Buck (Automotive) Yes Spread (SSFM) 1/2 (via sync) PFM/FPWM — — PG/Diag Yes AM band aware
Infineon (OPTIREG) TLS4120D0EPV Buck (Automotive) Yes Spread (SSFM) 1 PFM/FPWM — — PG/Diag Yes —
Renesas RAA211650 Buck (Integrated) Yes Spread (Option) 1/2 PFM/FPWM — — PG/INT — 60 V VIN
Renesas ISL78263 Buck (Automotive) Yes Spread (Programmable) 1/2 PFM/FPWM — — PG/Diag Yes AM window focus
NXP VR5510 (PMIC) Multi-Rail PMIC Yes (PLL sync) — Multi-rail Auto/FPWM — — INT/Diag Automotive System PMIC
NXP PF5300 / PF5301 / PF5302 PMIC Family Yes (Clocking) Spread (SSC) Multi-rail Auto/FPWM — — INT/Diag Automotive SSC coexistence
onsemi NCV881930 Buck (Automotive) Yes (SYNC input) via external SYNC 1/2 PFM/FPWM — — PG/Diag Yes SYNC must exceed ROSC
onsemi NCV890104 Buck (2 MHz) — Internal Spread 1 PFM/FPWM 2.0 — PG/Diag Yes EMI-oriented
onsemi NCV97200 (PMIC) PMIC (Multi-Rail) Yes* Internal Spread (disabled when ext sync*) Multi-rail Auto/FPWM — — INT/Diag Automotive *Common coexistence rule
MPS (Monolithic Power) MPQ4423C-AEC1 Buck (Automotive) — FSS (Spread) 1/2 Auto/FPWM — — PG/Diag Yes AEC-Q100
MPS (Monolithic Power) MPQ4228 Buck (Integrated) Yes (ext sync) Internal Spread (off when ext sync) 1/2 Auto/FPWM — — PG/INT — Coexistence rule
MPS (Monolithic Power) MP9928 (Controller) Buck Controller Yes (External Sync) — Multi-phase capable — — — PG/INT — —
* Replace “—” after checking the latest datasheets. Some devices disable internal spread when locked to an external clock; confirm per part.

9.2 Application Buckets

High-Freq Miniaturization (> 2 MHz, Mobile/Wearable)

  • High fsw ceiling, small ton,min, Forced PWM preferred; mild or no spread.
  • External sync optional; prioritize efficiency and size.
Placeholder parts: —

AM-Band Avoidance (~1 MHz Edge, Automotive)

  • Down-spread, robust external sync, AEC-Q100 grade, unlock reporting.
  • Guard lower edge vs AM/audio; stable PG behavior required.
Placeholder parts: —

Multi-Rail FPGA/SerDes (Interleaving/Sync/SSC)

  • Multi-phase, tight lock windows, PR dither support, clean fan-out.
  • Spread edges planned vs SSC sidebands; phase matrix enforced.
Placeholder parts: —

Noise-Sensitive Analog Front-Ends (ADC/PLL/Clock)

  • Forced PWM + shallow spread; explicit min fsw/on-time; low ripple priority.
  • Phase separation from AFEs; avoid low-frequency beats.
Placeholder parts: —

9.3 Selection Steps

  1. Choose an application bucket (size/efficiency/EMI/acoustics priorities).
  2. Filter by must-have fields: External Sync, Spread Type, Phases, AEC-Q100, etc.
  3. Balance size vs efficiency under fsw and ton,min constraints.
  4. Decide light-load mode (PFM vs Forced PWM) and unlock reporting.
  5. Shortlist 2–3 parts → BOM & proto validation.
IC Selection Flow — from buckets to a 2–3 part shortlist Four labeled steps: Choose Bucket → Must-Have Filters → Trade-offs (fsw, t_on,min, efficiency) → Validate/Review, feeding into a Shortlist box. Curved arrows show narrowing. Step 1 Choose Bucket size / EMI / acoustics Step 2 Must-Have Filters External Sync · Spread · AEC-Q100 Step 3 Trade-offs fsw · t_on,min · efficiency Step 4 Validate & Review EMI · load-step · acoustics Shortlist 2–3 candidate parts BOM + prototype
IC selection flow: Choose application bucket → apply must-have filters → make trade-offs → validate, then form a 2–3 part shortlist.

Worked Examples (Reusable Flows)

Three copy-and-run flows for frequency planning, phase interleaving, and unlock fallback. Each includes inputs, steps, quick math cues, and verification notes.

10.1 Flow A — Frequency Selection with Spread

Inputs

  • Sensitive bands: Audio < 20 kHz; AM 0.5–1.6 MHz; board refs/SSC sidebands.
  • Device fsw tolerance (e.g., ±6%), temp drift, reference ppm/%.
  • Candidate fc: 0.8 / 1.2 / 2.2 MHz; Spread plan: center ±X% or down Y%; sweep rate a few hundred Hz–kHz.

Steps

  1. Avoid windows: remove candidates whose spread edges invade sensitive bands.
  2. Add tolerance: include fsw error + temp + SSC to expand the actual sweep envelope.
  3. Reserve margin: keep ±5–10% trim room for later beat-avoidance.
  4. Select: prefer mid-band; near AM edge use down-spread.
  5. Verify: QP/AVG, audio monitoring, load-step; log ΔQP and new-peak status.
  • Center: work band ≈ [fc(1−X), fc(1+X)] ; Down: [fc(1−Y), fc].
  • If fc near AM upper edge → choose down-spread with safe lower bound.
Candidate Spread Plan Envelope Check Result
0.8 MHz center ±4% Clear of AM; margin OK Pass
1.2 MHz down 6% Upper edge near AM → down only Pass*
2.2 MHz center ±5% Both edges clean; smallest magnetics Pass (size-favored)
Frequency Planning Ruler — Sensitive Bands & Spread Envelopes Axis with labeled Audio and AM windows, plus three candidate switching-frequency envelopes: 0.8 MHz center ±4%, 1.2 MHz down-spread 6%, and 2.2 MHz center ±5%. 0.5 MHz 0.9 MHz 1.2 MHz 1.6 MHz 2.2 MHz Frequency → Audio < 20 kHz AM band 0.5–1.6 MHz 0.8 MHz center ±4% 1.2 MHz down-spread 6% 2.2 MHz center ±5%
Frequency ruler with labeled sensitive windows (Audio < 20 kHz, AM 0.5–1.6 MHz) and three candidate switching-frequency envelopes: 0.8 MHz ±4% (center), 1.2 MHz −6% (down), 2.2 MHz ±5% (center).

10.2 Flow B — Phase Interleaving (2/3/4/6)

  1. Assign phases evenly: 2→180°, 3→120°, 4→90°, 6→60°.
  2. Estimate input ripple RMS: ideal ≈ 1/√N; apply conservative factor ×0.8 for mismatch.
  3. Keep the rail near AFEs phase-separated from the noisiest neighbor.
  4. Verify: input ripple and near-field before/after interleaving.
N Phases Angles Ideal RMS Factor Conservative
2 180° 0.707 0.57
3 120° 0.577 0.46
4 90° 0.50 0.40
6 60° 0.408 0.33
Phase Interleaving Wheel A wheel showing recommended phase offsets: 2-phase 180°, 3-phase 120°, 4-phase 90°, and 6-phase 60°. Labels and a legend explain the ideal RMS reduction ~ 1/√N (use ×0.8 conservative factor). Ideal RMS ≈ 1/√N • Use ×0.8 conservative 4-phase 90° / 90° / 90° / 90° 3-phase 120° spacing 2-phase 180° 6-phase 60° ticks Legend Primary example: 4-phase (90°) Ghost: 3-phase (120°) Ticks: 6-phase (60°) Keep AFE rails far from the noisiest neighbors.
Phase interleaving wheel with labels: 2-phase 180°, 3-phase 120°, 4-phase 90°, and 6-phase 60° ticks; ideal input-ripple reduction ≈ 1/√N (apply ×0.8 conservative).

10.3 Flow C — Unlock Fallback & Relock

  1. Detect jitter/phase error beyond threshold → set UNLOCK flag.
  2. Fallback to internal oscillator fINT (soft-start optional).
  3. Log PG/fault status, timestamp, temperature, VIN, load.
  4. Retry N times with delay; else derate/limit power and raise alarm.
  5. Recover and restore spread/phase once lock is stable.
Unlock → Fallback → Relock — event flow for external sync Three swimlanes labeled Monitor, Control Logic, and Output. Steps: Detect UNLOCK, Fallback to internal oscillator, Retry attempts, and Stable Relock. Bottom lane shows logging window. Monitor Control Logic Output / Logging Detect UNLOCK Fallback to fINT Retry #1 Retry #2 Stable Relock PG/Fault flags · Timestamp · VIN · Temp · Event count t0 tN time →
Swimlane with labels: Monitor, Control Logic, Output/Logging. Steps—Detect UNLOCK → Fallback to internal clock → Retry attempts → Stable Relock; bottom lane records PG/fault and telemetry over time.

FAQs (Engineering Q&A)

Expand each item for concise, field-tested guidance and how to verify it.

Does spread-spectrum reduce efficiency or increase ripple?
  • Moderate depth usually has negligible efficiency impact; low-frequency content may rise slightly.
  • Verify with a load step and ripple spectrum. If audible noise increases, reduce depth or raise sweep rate.
Down-spread or center-spread — what’s the rule of thumb?
  • Near an upper sensitive edge → choose down-spread. If both sides are clean → choose center-spread (lower peak).
  • Ensure neither edge sweeps into AM/audio or SSC sidebands.
How do I terminate the external SYNC line? Any length/topology limits?
  • For long or multi-drop runs: use source-series or far-end parallel termination; prefer star fan-out with buffering.
  • Route on one layer with solid ground reference; avoid running parallel to the SW node. Across boards: AC-couple with bias.
How to diagnose phase-lock failures in multi-rail systems?
  • Check capture/hold-in range, minimum on-time, jitter RMS, and line skew.
  • Mitigate coupling: keep SYNC away from SW node; add buffer/termination as needed.
How to measure loop bandwidth and phase margin with spread enabled?
  • Frequency sweep instruments may read low; cross-check with a time-domain step, or temporarily disable spread for measurement.
  • Log on/off differences and tolerances; target PM ≥ 45–60°.
How to eliminate light-load PFM “chirp”?
  • Set a minimum fsw/min on-time or force PWM; add output RC damping to reduce Q.
Why is the AM band particularly sensitive?
  • Detector method and bandwidth make narrow spectral lines exceed limits more easily. Prefer down-spread and keep distance from AM edges.
How to stay stable during USB-PD PDO switching?
  • Re-test transient & EMI at each PDO; limit slew or power if needed.
  • Configure unlock fallback and retries; log events.
When must I use fixed frequency instead of spread?
  • When strongly coupled to higher-level clocks or when regulations mandate a fixed frequency. Prioritize function/stability first.
Will unlock fallback cause output glitches?
  • It depends on device/strategy; soft-start and proper output ESR help. Always measure recovery time.
Do spread-spectrum and board SSC add up?
  • Yes. Ensure lock window > SSC amplitude and plan spread edges away from SSC sidebands.
Sync at 1 MHz vs 2.2 MHz — trade-offs?
  • 2.2 MHz shrinks magnetics but raises loss; easier to avoid AM band. Evaluate thermals and magnetics.
Side effects of changing interleaving from 0° to 180°?
  • Input ripple drops, but resonance peaks may shift. Re-test near-field and output ripple.
When to choose a 4-switch buck-boost?
  • For wide VIN, continuous current, and low ripple. It coexists well with SYNC + spread and improves EMI control.
Production consistency: drift of lock/spread with batch or temperature?
  • Establish run-log fields; re-validate lock and spread depth/rate across batches and temperature; set engineering margins.

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