What CMTI target suits buck high-side paths?

Aim for ≥100 V/ns with 150–200 V/ns margin for robust immunity in GaN/SiC buck converters.

How to check driver thermal headroom above 1 MHz?

Estimate Pdrv ≈ 2·Qg·Vdrive·fsw and verify with IR; keep junction temperature at least 20 °C below the rated limit at steady state.

GaN/SiC Buck Driver ICs – Fast Gate & dv/dt Control

Q: How much negative gate bias is required at ~100 V/ns dv/dt?

Most GaN/SiC buck stages need around −2 to −3 V to ensure margin versus Miller-induced lift; validate under worst dv/dt and temperature with zero false-trigger events.

Q: Does a Miller clamp replace negative Voff?

No. They are complementary: the clamp mitigates transient lift while negative Voff improves static immunity and speeds turn-off. Use both where possible.

Q: What if a GaN FET is driven by a generic MOSFET driver?

Risk of under/over-drive, insufficient CMTI, and poor deadtime control can cause ringing or cross-conduction. Check gate waveforms and EMI/efficiency.

Q: How to validate safe switching margin under worst-case parasitics?

Capture HS/LS gate and SW at max bus and temperature; ensure overlap time is zero and VGS peak stays at least 1 V below the threshold.

Q: How to choose split Rup/Rdown for slew control?

Start with 2–10 Ω; increase Rup to reduce EMI. Re-tune deadtime after each change and choose the Pareto point of EMI vs efficiency.

Q: Is bootstrapping viable above 1 MHz?

It depends on duty cycle and losses; high-frequency or high-duty applications often prefer dedicated or isolated high-side supplies.

Q: What deadtime resolution is needed for GaN half-bridge buck?

Prefer ≤2–5 ns resolution with temperature-stable calibration or adaptive control to avoid overlap and minimize diode-like conduction windows.

Q: Where to place oscilloscope test points?

Place Tp_Gate at the device leg with a differential probe and short ground spring, plus Tp_SW and Tp_DRV± near the driver rails.

Q: Can ferrite beads be used on a GaN gate?

Generally not recommended because they distort edges; prefer series resistance or small RC damping along with layout improvements.

Wide-bandgap switches (GaN HEMTs and SiC MOSFETs) are replacing silicon in high-performance buck regulators due to higher switching frequency, lower loss, and better power density. Yet generic MOSFET drivers often fail in these environments: strong EMI and high dv/dt can induce Miller-triggered shoot-through, gate ringing, and timing collapse. This page focuses on buck-topology drivers engineered for GaN/SiC: split source/sink paths, negative turn-off, robust Miller clamp, and disciplined dv/dt control.

>1 MHz switching >100 V/ns dv/dt immunity Ultra-low Q_g gate control Negative V_off (−2~−3 V) Miller clamp & split outputs

Architecture of GaN/SiC Buck Drivers

Scope limited to single-phase and multiphase buck. GaN/SiC drivers differ from silicon MOSFET drivers by using split source/sink outputs (independent rise/fall control), dual rails (e.g., +5~6 V / −2~−3 V) for noise immunity, and very short gate loops. High-side paths may use bootstrapping or an isolated/aux supply depending on frequency and duty-cycle constraints.

Split OUT_H / OUT_L: separate resistors to tune rise/fall slew for EMI vs. loss.
Dual rail: positive gate drive for speed; negative turn-off to suppress Miller turn-on.
Protection hooks: UVLO, shoot-through prevention, adaptive dead-time, OC/Desat.
SR pairing: timing interface to synchronous rectification (details on SR page).

Buck-topology driver with split outputs and dual rails driving a GaN half-bridge; LC filter produces V_OUT. Dashed line illustrates dv/dt coupling awareness.

Key Design Challenges

GaN/SiC buck driver · dv/dt & Miller

dv/dt Induced Miller Turn-On

Mechanism: Fast SW node edges inject charge via C_gd, lifting V_GS above V_th.
Mitigation: Miller clamp near Kelvin source, negative turn-off (−2~−3 V), split R_up/R_down, shortest gate loop.
Validation: Worst-case >100 V/ns; probe V_GS differentially at the device; ensure V_GS peak < (V_th − 1 V).

Loop inductance · Resonance

Gate Ringing from Package/Loop Inductance

Mechanism: L_s/L_g with C_g forms a resonant tank → overshoot/undershoot.
Mitigation: Minimize loop area, small series R_g, optional RC damping; avoid ferrite beads on GaN gate.
Validation: 1 GHz probe; verify 10–90% edges free of secondary crossings and within V_G,max.

Noise immunity · Fast turn-off

Need for Negative Turn-Off Voltage

Value: Suppresses Miller; accelerates turn-off and reduces loss.
Ranges: Typical −2~−3 V; observe device V_GS ratings, UVLO, and power-up/down sequencing.
Validation: Sweep dv/dt and temperature (−40~125 °C); false-trigger count must be zero.

Power dissipation · CMTI · Layout

Thermal & PCB Constraints for Wide-Bandgap Drivers

Driver loss: P_drv ≈ 2·Q_g·V_drive·f_sw (half-bridge).
CMTI target: ≥100 V/ns (prefer 150–200 V/ns margin) for high-side/isolated paths.
Layout: Multi-via thermal stitching, solid copper islands, keep sensitive nodes away from SW.
Validation: IR thermography + loss calc; keep T_j within rating minus ≥20 °C margin.

dv/dt coupling from the SW node back to the driver through parasitics; mitigation via Miller clamp, negative V_off, split R_up/R_down, and a short gate loop.

Essential Driver Features (Selection Criteria)

GaN/SiC buck driver ICs — selection features, reasons, and engineering impact
Feature	Why it matters for GaN/SiC	Engineering impact
Miller Clamp	Prevents V_GS lift from C_gd injection under high dv/dt.	Avoids false turn-on and shoot-through; place clamp close to Kelvin source.
Negative V_off	Speeds turn-off and increases noise immunity against dv/dt.	Improves reliability; common range −2~−3 V with proper UVLO and sequencing.
Slew Rate Control	Balances EMI vs. switching loss using split source/sink paths.	Enables per-edge tuning via R_up/R_down or internal control.
Deadtime Optimization	Prevents cross-conduction; GaN lacks a body diode and needs precise timing.	Boosts efficiency; requires ns-level resolution and temperature stability.
Dual Gate Outputs	Independent control for high/low side and SR pairing.	Supports half-bridge matching; check peak source/sink current and output impedance.

Design Knobs

R_up/R_down Start 2–10 Ω; increase rise-edge resistance to trade EMI vs. loss.
V_off Begin at −2.0 V; extend to −3.0 V if false-trigger risk persists; verify V_GS ratings.
Deadtime Sweep 10–30 ns; minimize diode-like conduction window while keeping overlap = 0.
Layout Short gate traces; Kelvin source return; keep sensitive nets away from SW copper.

Validation

Miller: At steepest edge, V_GS peak < V_th − 1 V; false-trigger count = 0.
Slew: Tune R_up/R_down vs. EMI peak and efficiency rise; log the best pair.
Deadtime: Dual-channel HS/LS gate capture; overlap time = 0, no secondary turn-on artifacts.
Negative V_off: Worst bus/temperature; ensure no spurious conduction during shut-off.

Brand-Neutral Targets

CMTI ≥ 100 V/ns (prefer 150–200 V/ns margin)
Peak source/sink ≥ 2–4 A for GaN half-bridge
Gate rails: +5~6 V / −2~−3 V with proper UVLO
Deadtime resolution ≤ 2–5 ns; stable across temperature
Low OUT-to-ground impedance; gate path length < 10 mm where possible

Application Examples

EV auxiliary rail: 400 V → 12 V buck using GaN/SiC driver with negative V_off and strong CMTI.

EV 400V → 12V DC Buck

Driver needs: −2~−3 V turn-off, Miller clamp, high CMTI.
Design notes: Kelvin source return; short OUT→gate; ns-level deadtime.
Quick checks: V_GS margin at worst dv/dt; thermal image of driver; cold crank / load dump transients.

48 V → 12 V interleaved multiphase buck with GaN-ready drivers and per-edge slew control.

AI Server 48V → 12V Multiphase Buck

Driver needs: split source/sink, fine deadtime, CMTI margin for interleaving noise.
Design notes: align gate timing across phases; short gate loops per phase.
Quick checks: EMI peak vs efficiency while sweeping R↑/R↓; phase current balance.

_OUT

High-voltage solar optimizer buck stage with robust CMTI and negative turn-off.

Solar Inverter DC Optimizer

Driver needs: strong CMTI, reliable HS drive; isolation/bootstrap trade-offs.
Design notes: temperature-resilient deadtime; keep sensitive nets away from SW copper.
Quick checks: dv/dt limits under hot/cold; UVLO sequencing; thermal hot-spot scan.

Avionics/space buck: disciplined ringing control, margin on CMTI and deadtime.

Satellites / Avionics Rail Conversion

Driver needs: margin-first timing; ringing suppression; robust −V_off.
Design notes: select packages with small loop inductance; formal margin accounting.
Quick checks: V_GS overshoot stats = 0; timing overlap = 0; ≥20% margin across temp.

Layout & Testing Guidelines

Practical PCB and probing guidance for GaN/SiC buck driver stages: minimize gate/power loop inductance, isolate gate-source paths, tune dv/dt via split resistors, and place robust, reproducible test points.

Loop · Layout · Parasitics

PCB Loop Inductance Minimization

Separate power loop and gate loop; keep the gate driver adjacent to the FETs.
Short & wide copper for the gate path; stitch vias to reduce return inductance.
Kelvin source return for the driver ground; avoid sharing with power return.
Target: gate path length < 10 mm where possible; loop area minimized.
Quick check: reduced V_GS ringing and cleaner current edges.

Routing · Return path

Gate–Source Trace Isolation

Route gate and its return as a tight pair to the Kelvin source pin.
Keep gate traces away from the SW copper and slot/void boundaries.
Shield with quiet reference copper; avoid via stubs on the gate.
Quick check: near-field EMI peak drops after isolation pass.

Slew · Split source/sink

dv/dt Control via External Resistor Tuning

Use split R_up/R_down to tune rise vs. fall independently.
Start with 2–10 Ω; increase R_up to trade EMI for loss as needed.
Re-evaluate deadtime after each change; maintain overlap = 0.
Quick check: find Pareto point (EMI peak ↓ vs. efficiency ↑).

Probing · Safety · Repeatability

Oscilloscope Test Points Placement

Tp_Gate at the device leg; differential probe with short ground spring.
Tp_SW at the switching node; guard from accidental shorts.
Tp_DRV+ / Tp_DRV− near driver rails; verify UVLO and −V_off.
Quick check: under worst dv/dt, false turn-on events = 0.

Gate loop kept short to the Kelvin source; power loop separated. Test at Tp_Gate, Tp_SW, and driver rails; dashed path marks dv/dt coupling awareness.

IC Selection — GaN/SiC Buck Driver Part Numbers (7 Brands)

Brand-by-brand part number list for GaN/SiC-ready buck drivers. Check datasheets for CMTI, peak source/sink current, gate rails, UVLO, isolation type, and qualified voltage class before committing.

TITexas Instruments

LMG1205 — 200 V — +5/−1 V — Miller clamp · split outputs

Half-bridge GaN driver; buck stages in EV/industrial.

LMG1210 — 200 V — +5/−1 V — 1 MHz-class half-bridge

High-side/low-side GaN driver with adjustable deadtime.

LMG1020 — Low-side — +5/0 V — Ultra-fast GaN low-side drive

Narrow pulse capability; useful for synchronous legs or pilot stages.

NXPNXP Semiconductors

GD3160 — 1200 V — +15/−3 V — SiC optimized · DESAT

Isolated gate driver; robust for high-voltage buck.

GD3100 — 1200 V — +15/−3 V — High CMTI isolated

Automotive/industrial SiC MOSFET driver.

GD3162 — 1200 V — +15/−3 V — DESAT · protection suite

Enhanced protection set for SiC power stages.

onsemionsemi

NCP51820 — 650 V — +12/−4 V — Ultrafast SiC drive

Given reference for industrial buck stages.

NCP51705 — 1200 V — +15/−5 V — High-voltage half-bridge

Suited for SiC MOSFETs with negative turn-off.

NCP51561 — 650 V — +12/−4 V — High-side/low-side driver

Half-bridge driver for WBG buck applications.

STSTMicroelectronics

STGAP2GS — 1200 V — up to +20/−3 V — SiC-focused isolated driver

Optimized for SiC with strong CMTI performance.

STGAP2S — 1200 V — +15/−3 V — Single-channel isolated

High-voltage isolated driver for SiC MOSFETs.

L6491 — 600 V — +12/0 V — Half-bridge high-voltage driver

MOSFET/GaN-compatible with proper gate rail selection.

RenesasRenesas Electronics

ISL78434 — 1200 V — +15/−3 V — Isolated SiC driver

Automotive-focused; supports negative turn-off.

ISL78420 — HV — +15/−3 V — Dual-channel gate driver

SiC-ready timing and protection features.

HIP2103 — 600 V — +10/0 V — Half-bridge driver

General half-bridge; pair with GaN/SiC per device limits.

MicrochipMicrochip Technology

MIC4606 — 85 V — +10/0 V — Adaptive deadtime half-bridge

Low/medium voltage buck phases; GaN pairing with proper rails.

MCP14E10 — Low-side — up to +18/0 V — 10 A peak drive

Low-side GaN/SiC assist with external −V_off supply.

MCP14C1 — Low-side — +9/0 V — Fast MOSFET/GaN low-side

Use in synchronous leg; confirm device limits.

InfineonInfineon Technologies

1EDF5673K — GaN — 5 V class — CoolGaN™ driver

Dedicated GaN gate driver for high-speed buck.

1EDN7550B — Low-side — up to +20/0 V — Miller clamp low-side

Low-side driver with strong pulsed current.

2EDF7275F — Dual — 5 V class — Dual-channel GaN driver

Two low-side GaN channels for interleaved buck legs.

Part numbers are representative and commonly used for GaN/SiC buck stages. Always cross-check official datasheets (CMTI, rails, ratings, timing) for your exact device and operating point (>1 MHz, >100 V/ns).

Engineering FAQs — GaN/SiC Buck Drivers

Practical answers for GaN/SiC buck driver design and validation. Each entry gives the takeaway and a quick validation step.

How much negative gate bias is required at ~100 V/ns dv/dt? −V_off

Typical range is −2 to −3 V depending on package/loop parasitics; ensures margin against Miller-induced lift.
Validate: worst dv/dt and temperature; log false-trigger events = 0 and V_GS,peak < (V_th − 1 V).

Does a Miller clamp replace negative V_off? Clamp + −V

No—complementary mechanisms. Clamp mitigates transient lift; −V_off increases static immunity and speeds turn-off.
Validate: compare clamp-only vs −V-only vs both; record V_GS,peak and shoot-through incidence.

What if a GaN FET is driven by a generic MOSFET driver? Compatibility

Risks include under/over-drive, insufficient CMTI, inaccurate deadtime → ringing or cross-conduction.
Validate: inspect gate waveforms and efficiency/EMI curves; look for overshoot and timing overlap.

How to validate safe switching margin under worst-case parasitics? Margin

Capture HS/LS gates and SW at max bus, hottest temp, steepest edges; ensure overlap = 0 and V_GS,peak < (V_th − 1 V).
Validate: compute margin chart vs load and temperature.

What CMTI target is appropriate for buck high-side paths? CMTI

Aim for ≥100 V/ns with margin (150–200 V/ns) for robust immunity in GaN/SiC buck converters.
Validate: inject disturbances/fast load steps and track mis-trigger counts.

How to choose split R_up/R_down for slew control? Slew

Start at 2–10 Ω; raise R_up to reduce EMI; re-tune deadtime after any change.
Validate: plot EMI peak vs efficiency to find the Pareto optimum.

Is bootstrapping viable above 1 MHz? HS supply

Depends on duty cycle and losses; high-freq/high-duty often prefers dedicated/isolated HS supply.
Validate: verify no HS undervoltage events and acceptable driver thermal rise.

What deadtime resolution is needed for GaN half-bridge buck? Deadtime

Prefer ≤2–5 ns resolution with temperature-stable calibration or adaptive control.
Validate: confirm zero overlap and minimized diode-like conduction window.

Where to place oscilloscope test points? Probing

Near the device: Tp_Gate at the leg (differential probe, short ground spring), Tp_SW, and Tp_DRV±.
Validate: reproducible waveforms across operators (variance <10%).

Can ferrite beads be used on a GaN gate? Damping

Generally not recommended; can distort edges unpredictably. Prefer series R or small RC damping plus layout fixes.
Validate: A/B compare overshoot and spectrum with/without bead.

How to size peak source/sink current for the driver? I_pk

Use Q_g and target edge rates; ≥2–4 A is common for GaN half-bridge buck (often higher).
Validate: meet edge-rate targets without excessive overshoot or driver overheat.

Do I need a Kelvin source return for the driver? Return path

Highly recommended. It reduces common-mode injection and loop inductance, improving noise immunity.
Validate: observe V_GS ringing/false-trigger count before vs after Kelvin routing.

What UVLO thresholds are recommended for ± gate rails? UVLO

Ensure positive-rail UVLO prevents under-drive; negative-rail UVLO avoids power-down mis-triggering.
Validate: power-up/power-down sequencing with no spurious conduction.

How to check driver thermal headroom at >1 MHz? Thermal

Estimate P_drv ≈ 2·Q_g·V_drive·f_sw; verify with IR and keep T_j ≥20 °C below rating.
Validate: soak test at worst load; confirm steady-state temperature margin.

All guidance assumes buck or multiphase buck topologies using GaN HEMTs or SiC MOSFETs.

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