Low-speed serial & logic, industrial/automotive fieldbuses, Ethernet/TSN, high-speed backplane links, multimedia camera/display, USB & bridges, isolation blocks, CDR/equalization, protocol bridges, co-design protection & test hooks, and key selection metrics.
Low-Speed Serial & Logic Layer
I²C / I³C Buffers & Switches
Bus segmentation/cap loading relief, arbitration hold, and timing shaping.
SPI / I²S Bridges & Mux
Level/clock-domain conversion, serdes bridges and audio TDM interop.
UART / 1-Wire / Multichannel UART
Low-power with auto-baud, wake features and optional IR modulation.
Level Translators / Voltage Translators
Bi/uni-directional with auto-direction sensing across multiple rails.
Industrial & Automotive Buses
RS-485 / RS-422 Transceivers
Fail-safe, ±15 kV ESD, short-tolerant with thermal shutdown for long lines.
CAN/CAN-FD & Automotive Ethernet PHY
Common-mode control, wake/TC10 sleep; chassis and e-drive networks.
LIN Transceivers (Master/Slave)
Fault-tolerant low-speed nodes with wake/sleep for body modules.
IO-Link Master/Device PHY
COM1/2/3 support, short/open diagnostics and robust port protection.
HART FSK Modem
4–20 mA FSK overlay with isolated front-end and noise mitigation.
Profibus-DP/PA & FF H1 PHY
31.25 k/1.5 Mbit PHYs, isolated coupling and strict timing compliance.
Powerline Communication PHY (G3/PRIME)
Narrowband OFDM with coupling networks and grid-noise robustness.
Industrial Ethernet / TSN & Switching
Ethernet PHY (10/100/1G/2.5G/TSN)
Low-jitter clocks, EEE power save and PTP timestamps for TSN.
Industrial Ethernet Slave/Master
EtherCAT/PROFINET/SercosIII with HW timestamps and dual-port switching.
TSN Switch / Bridge
802.1AS/Qbv/Qbu with HW PTP, QoS and traffic shaping for determinism.
High-Speed Serial & Backplane
PCIe Retimer / Redriver
CTLE/DFE equalization, SRIS/SRNS and strong jitter tolerance.
SATA / SAS TxRx / Redriver
EQ & pre-emphasis with CDR and OOB compatibility for storage fabrics.
CXL Retimer / Bridge
Low-latency forwarding, link training and hot-plug for servers.
JESD204B/C SerDes
Multi-lane alignment with SYSREF/LMFC (Subclass-1) for ADC/DAC chains.
Multimedia · Camera & Display
HDMI / DisplayPort Tx/Rx/Redriver/Retimer
HDCP/EDID, EQ/retiming and jitter/eye compliance.
SDI (3G/6G/12G) SerDes
Coax EQ, timing embed and return-channel support for broadcast.
MIPI D-PHY/C-PHY · CSI-2/DSI
Bridges/repeaters, lane extension and robust clock recovery.
LVDS / FPD-Link / GMSL SerDes
Single-coax/twisted, power/control multiplex and remote-power options.
CoaXPress / SLVS-EC PHY
Industrial camera links with trigger/genlock and long-run capability.
USB & General Bridges
USB 2.0/3.x Redriver / Hub / Repeater
EQ/pre-emphasis, BC1.2 detection (data-side) and Type-C orientation.
USB↔UART/I²C/SPI/GbE Bridges
CDC/FT/ECM drivers with EEPROM config for debug and device bridging.
Ethernet Controllers / MAC-PHY
RGMII/SGMII, checksum offload and Wake-on-LAN support.
Isolation & Compliance Modules
Isolated Transceivers (RS-485/CAN/Profibus)
Reinforced insulation, high CMTI and fail-safe receivers for noisy HV sites.
Digital Isolators (Capacitive/Magnetic)
Multi-channel with delay matching (SPI/I²C/UART isolation).
Isolated Ethernet PHY/Magnetics
Integrated magnetics/CM chokes for stronger ESD/surge robustness.
Clock/Data Recovery & Equalization
CDR / Retimer
Jitter clean-up with programmable loop BW for cables/backplanes.
Linear Redriver / Equalizer
CTLE/FFE with adaptive gain for long-reach extension.
Glitch-Free Clock Mux / Fan-Out
Hitless switchover and skew-controlled multi-domain distribution.
Protocol Bridges & Format Conversion
SerDes Bridge (Parallel↔Serial)
Extend FPGA I/O with peripheral SerDes; smooth legacy→new interface transitions.
Video Format Bridges
HDMI↔MIPI, DP↔LVDS, CSI↔Parallel with EDID/HPD and clean domain crossing.
Industrial Protocol SoC/Bridge
Multi-protocol firmware, holdup retention and rich diagnostics.
Interface Co-Design: Protection & Test
High-Speed ESD / TVS Arrays
Ultra-low C arrays meeting IEC 61000-4-2/-4-5 with tight differential matching.
CM Chokes & Impedance Matching
Differential terminations and matching to open eye diagrams.
Loopback / PRBS / BIST
Built-in BER testing and field-diagnostics hooks.
Compliance Hooks
SSC/jitter templates, CTLE/DFE presets and EDID/HDCP/PCI-SIG artifacts.
Key Specs & Selection
Electrical Layer
Swing/common-mode, de/pre-emphasis, Rx sensitivity and eye/jitter budgets.
PHY Robustness
ESD/surge, EMI emissions/immunity and long-run/temperature stability.
Timing & Synchronization
CDR/retimer options, jitter clean-up and PTP timestamps (TSN).
Power & Thermal
Per-Gbps power, thermal resistance and cooling/package choices.
Protocol Compatibility
Version/data-rate support, backward compatibility and redundancy modes.
