Practical index for board-level serial buses: I²C (incl. I³C hooks), SPI (1/2/4-bit, QSPI/OSPI), UART (w/ RS-232/485), plus level shifting, isolation, protection, topology planning, bridges/extenders, debugging, key specs and design pitfalls.
I²C (Inter-Integrated Circuit)
Standard / Fast / Fast+ / Hs-Mode
100/400/1,000/3,400 kbps modes; pull-up sizing with RC time-constant budget for compliant rise times.
7-bit / 10-bit Addressing & Multi-Master
Arbitration loss handling, clock synchronization and conflict/bus-stall recovery strategies.
Repeated START & Page Write
Combined transactions for EEPROM/register access with correct page-write timing.
Clock Stretching
Slave response delay, master timeout policies and robust error handling.
Open-Drain & Pull-Up Network
Wired-AND signaling, pull-up to system/isolated rails, EMC and edge-rate shaping.
I³C Compatibility Hooks
HDR/mixed-bus operation, dynamic addressing and hanging legacy I²C devices safely.
Buffers / Isolators / Switches
Segment long buses, isolate capacitance and bypass address conflicts.
Long-Reach I²C over Cabling
Use CMCs/differential extenders with port protection and health monitoring.
SPI (Serial Peripheral Interface)
CPOL/CPHA Modes (0–3)
Master/slave alignment and cross-vendor compatibility to avoid bit-slip.
1/2/4-bit SPI, QSPI/OSPI
Bandwidth scaling with XIP, command/address phase considerations and timing windows.
Chip-Select & Fanout
Length matching across many slaves, CS decode trees and daisy-chains.
Full/Half/3-Wire
MISO/MOSI multiplexing and direction-control for 3-wire variants.
SCLK Quality & Skew
Edge placement and skew control with proper buffering/termination.
DMA & High Throughput
Large-block transfers, bursts/framing and latency for real-time use.
Isolated SPI / isoSPI
High-CMTI isolation and long-chain comms for BMS/industrial networks.
Long-Trace SI
Driver strength & termination, pre-emphasis/clamping and return-path planning.
UART (Universal Asynchronous Receiver/Transmitter)
Baud Rate & Error Budget
Keep combined clock error within typical ±2%; choose XTAL/PLL and add calibration hooks.
Frame Format
Start/data/parity/stop configuration; LIN/RS-232/485 layering considerations.
HW Flow Control (RTS/CTS, DTR/DSR)
Prevent overruns and secure long-frame transfers with hardware handshaking.
Break/Wake & Idle Detect
Low-power wake-up via break/idle detection and coordination with LIN-style stacks.
Framing/Parity Errors & Noise
Use oversampling and de-glitch filters for noise-tolerant reception.
Voltage Levels & PHY
Bridge LVCMOS to RS-232/RS-485/CAN transceivers safely with protection.
Multi-UART Bridges
USB/Ethernet to UART bridges with deep buffers, timestamping and traffic shaping.
Common Topics Across Buses
Level Translation
Multi-voltage domains (1.2–5 V), auto-direction handling and open-drain preservation.
Port Protection
Low-C ESD arrays, series-R/RC damping and surge/over-voltage clamps.
Topology Planning
Budget bus capacitance/fanout, manage trace length and avoid star topologies.
Error Handling & Recovery
Recover from hung buses with timeouts, reset sequences and watchdogs.
Clock & Grounding
Design return paths across split grounds; suppress common-mode noise.
EMC & Edge Control
Right-size pull-ups/terminations, control slew and manage shielding/crosstalk.
Isolation Strategy
Safety/functional isolation with delay budgets and CMTI requirements.
Low-Power Hooks
Clock gating, sleep/wake schemes and bus-hold/sticky-state considerations.
Bridges & Extenders
I²C ↔ SPI Bridge
Extend low-pin MCUs with external peripherals using register maps and command queues.
UART ↔ SPI/I²C Bridge
Remote console/debug links with buffering and back-pressure control.
I²C Expander / Hub / Mux
Resolve address conflicts, isolate channels and cascade deep fan-outs.
SPI Expanders / Repeaters
Multi-board SPI with re-timing/re-drive for cleaner edges.
UART Multiplexer / Selector
Share a single UART among many devices while avoiding collisions.
Debug & Analysis
Logic / Protocol Analyzer
I²C/SPI/UART decode with useful triggers and timing alignment methods.
Bus Health & Stats
Track retries/NAKs/CRC, throughput and latency; log notable events.
BIST / Loopback Test
Power-on self-tests, interface acceptance and production test pins.
Key Specs & Selection
Speed / Timing
tSU/tHD/tR/tF budgets, SCLK frequency/duty, sampling windows across buses.
Bus Capacitance & Fanout
Typical I²C ≤400 pF designs; SPI trace capacitance vs edge rates.
Voltage Compatibility
VIH/VIL levels, 5-V tolerance and open-drain vs push-pull drivers.
Robustness
ESD/surge ratings, EMI emission/immunity, hot-plug and UVLO behaviors.
Power
Pull-up power vs duty cycle, transceiver Iq and sleep/wake strategies.
Reliability
Lock-up recovery, watchdog/timeout hooks and redundant/bypass channels.
Design Hooks & Pitfalls
I²C Pull-Up Sizing
Compute RC from bus capacitance; too small → power loss, too large → slow edges/eye collapse.
I²C Arbitration & Stretching
Master timeouts and recovery with long-cable, slow-slave compatibility.
SPI Routing & Termination
Shortest SCLK, MISO near master; source/endpoint matching for integrity.
SPI Mode Mismatch
Mis-set CPOL/CPHA causes bit shift; define safe power-up defaults.
UART Baud Error Budgeting
Sum both-end clock drifts; prefer calibration or adjustable divisors.
Common-Mode & Ground
Long cable common-mode rise; add isolation/differential PHY when needed.
Hot-Plug / Brown-Out
Limit inrush/TVS at ports and avoid “ghost-powering” with proper sequencing.
Firmware Robustness
Timeout/retry/CRC, power-fail write-protection and recovery state-machines.
