← Back to Low Dropout Regulators (LDOs)
We cascade LDOs to clean up what the upstream DC/DC cannot; we parallel LDOs only when we can keep their loops from fighting. This page focuses on small-power, noise-sensitive rails such as sensor, RF front-end, ADC reference, and camera/bias supplies.
Scope
Only LDO→LDO and DC/DC→LDO→LDO chains for low-noise use. No eFuse/hot-swap, no pack-level protection.
Key reminder
Two 3.3 V LDOs cannot be hard-paralleled. Use OR-ing or load-share to avoid control-loop conflicts.
What to log
VIN(min), Vpre, Vout, dropout@load, thermal rise, and start-up interaction → add to BOM for cross-vendor replacement.
Cascading LDOs for Noise / PSRR
Typical situation: the upstream DC/DC regulator still leaves ripple or high-frequency spikes around 500 kHz–2 MHz, or its PSRR drops too early. We insert a pre-LDO to slice off these residues, and then a final low-noise LDO close to the load. This only works if we plan for voltage headroom and thermal dissipation on both stages.
Why we cascade
- Upstream DC/DC ripple or spikes are still present.
- PSRR of a single LDO is not flat at 1–2 MHz.
- Final rail is noise-critical (sensor, RF, ADC, camera bias).
- Two-stage LDO is supported by major vendors (TI, ST, NXP, Renesas, onsemi, Microchip, Melexis) for automotive/industrial lines.
Voltage headroom planning
Example path: VIN(DC/DC) = 5.0 V → Pre-LDO = 3.6 V → Final LDO = 3.3 V.
Requirements:
- Vpre ≥ Vout + Dropoutfinal(Iload, Tmax)
- VDC/DC,min ≥ Vpre + Dropoutpre(Ipath, Tmax)
- Include tolerance of DC/DC, LDO setpoint, and wiring drops.
Thermal budget
Both LDOs dissipate linearly:
Ppre ≈ (Vin_dc/dc − Vpre) × I, Pfinal ≈ (Vpre − Vout) × I.
Record these powers and estimated ΔTj in the BOM so purchasing can switch between TI / ST / NXP / Renesas / onsemi / Microchip / Melexis without re-measuring everything.
Loop / transient notes
A step load on the final LDO is seen as a dynamic load by the pre-LDO. Check pre-LDO phase margin and soft-start. If the pre-LDO collapses during final-LDO load steps, either raise Vpre, select a pre-LDO with better transient, or reduce the load step.
Cascading checklist (copy/paste)
- VIN(DC/DC), VIN_min
- Vpre target and dropout of pre-LDO @ I
- Vout target and dropout of final LDO @ I & T
- Ppre, Pfinal, θJA, est. ΔTj
- Start-up: DC/DC → Pre-LDO → Final LDO
- Noise target met? (measure after final LDO)
3) Dropout & Headroom Planning (for Cascades)
In a cascaded LDO chain, the fastest way to fail is to ignore three stacked losses: the downstream dropout, the wiring/trace drop, and the temperature-induced increase of dropout. If headroom is not guaranteed under worst-case VIN and highest temperature, you should not cascade; instead use a higher-PSRR single LDO or a DC/DC + LC filter.
Why this matters
Every LDO in the chain needs its own dropout margin. When you stack two LDOs after a DC/DC, any VIN dip, cold crank, or high-temperature operation steals this margin first from the upstream LDO and then from the downstream one.
Minimal check formula
Use this as the first gate:
Upstream LDO Vout,min ≥ Downstream LDO Vout + Downstream Dropoutmax @ load
And if the upstream LDO is powered from a DC/DC:
VDC/DC,min ≥ Vupstream,set + Upstream Dropoutmax @ I, T
Check these conditions
- High temperature (up to 125 °C): dropout can be larger.
- Automotive cold crank: VIN from DC/DC may sag temporarily.
- DC/DC tolerance and LDO tolerance both included in the budget.
- Board/connector drop (tens of mV) counted as real loss.
Cascaded LDO headroom checklist
- VINdc/dc,min
- Vupstream,set and Vupstream,min (incl. tolerance)
- Vdownstream,set
- Dropoutdownstream(Iload, 125 °C)
- Trace / connector drop (mV)
- Automotive? → cold-crank window checked
- Fail any → do not cascade; use high-PSRR single LDO / DC/DC+LC
4) Paralleling LDOs – Why Loops Clash
Two LDOs set to the same output voltage still have their own error amplifiers, references, and pass elements. Even a small Vout mismatch of 20–30 mV can make one LDO take almost all the current, or make both LDOs hunt. Parallel LDOs without isolation is effectively shorting two control loops.
Why loops clash
- Each LDO tries to regulate the rail to its own reference.
- Compensation / bandwidth are not identical.
- A 20–30 mV difference at the load makes the higher LDO supply most of the current.
- This can create oscillatory behavior (hunting).
What to do instead
Use a weak-isolation scheme to let one LDO win without fighting:
- Diode OR-ing (Schottky): simplest, but with drop.
- Ideal-diode / FET OR-ing: good for low-drop bias rails.
- Passive load-share (ballast resistor): small resistor on each LDO output to make current sharing resistive.
- Controller-based share: possible, but usually overkill for small LDO rails.
6) Stability & Loop Interaction Notes
In cascaded rails, the downstream step stresses the upstream LDO. In paralleled rails, the isolation element adds a small impedance that actually helps stability. avoid loop sharing when paralleling — use OR-ing/load-share schemes.
Cascaded case
- Step load on final LDO → upstream sees a dynamic load.
- Measure: upstream Vout, downstream Vout, PG/EN.
- If upstream sags → increase upstream setpoint or choose LDO with better phase margin.
Paralleled case
- OR-ing / ballast adds a small pole/zero but prevents two error amps from fighting.
- Check voltage across the OR-ing device for HF chatter.
- Test failover: disable LDO A, confirm LDO B owns the rail.
Minimal validation matrix
- Cascade: 10→100 mA step on final rail (room & high temp)
- Cascade: VIN(min) from DC/DC + same step
- Parallel: LDO A off → B holds rail
- Parallel: observe OR-ing drop for oscillation
- Log worst waveforms in BOM notes
8) Seven-Vendor Pointers
Use the validation numbers you just logged (Vin, Vout, Iout, ΔV, which LDO was active, at which temperature) to pick one of the following vendor parts. This keeps your cascade/paralleling page consistent with the LDO hub at Low Dropout Regulators (LDOs).
Texas Instruments (TI)
TPS7A47-Q1 – 36 V max in, low noise, good as “pre-LDO after DC/DC”, automotive grade.
LP5907-Q1 – 250 mA, ultra-low noise, perfect for sensor/camera final stage.
TPS7A83A / TPS7A85A – up to 2 A, use as the bigger first LDO, then cascade to a quieter one.
Parallel only with OR-ing or ballast — do not hard-tie two TPS7A parts.
STMicroelectronics (ST)
LD39100PU33 – 1 A, low-noise 3.3 V, can sit as the very final LDO.
LDQ40 / LDL40 系 – wide-input, automotive/sensor bias, good as the upstream LDO in a cascade.
LDLN025 – 250 mA ulp-noise, when your final load is RF/ADC.
For parallel use diode/FET OR-ing; ST does not recommend blind output-to-output tie.
Renesas
ISL78302 – dual 300 mA, automotive, intended as clean post-reg rails → fits LDO→LDO pages.
ISL78310 – up to 1 A, good as the first LDO after a buck in camera/IVI domains.
RAA2121x / RAA2140x family can also be used when you need higher VIN tolerance.
Note in BOM: “tested as cascaded final → 3.3 V, see waveform.”
NXP
UJA1169TK/F – LIN/CAN SBC with integrated 3.3/5 V LDO; treat it as the “already clean” rail → do not force a second external LDO in parallel.
MC33903 / MC33904 – automotive system basis chips, have internal regulators for MCU/sensor bias.
If you must add external redundancy, do it with FET-OR outside the SBC output.
onsemi
NCV8730 – wide-VIN, 150 mA, very good as the “first” LDO before your low-noise tail.
NCV8170 – ultra-low Iq, 300 mA, for always-on sensor rails.
NCV8705 / NCV8706 – for higher current, still automotive temp.
Parallel with ideal-diode controller if you need failover in harsh temp.
Microchip
MCP1700T-3302E/TT – 3.3 V, very low quiescent, easy final stage for small loads.
MCP1754S-3302E/DB – 300 mA class, can be the “second” LDO after a bigger one.
MCP1824T-3302 – when you need bit more current but still low noise.
Note: write test temps in BOM, Microchip industrial ≠ automotive by default.
Melexis
MLX90393 / MLX90395 – magnetic position sensors with internal regulator; treat them as “final load with own LDO”.
MLX90614 – IR sensor, also expects a clean supply; your external LDO should stop before the sensor and feed through a diode if redundancy is needed.
MLX81330/32 (LIN driver/actuator) – has supply conditioning on board, so use external LDOs in cascade only up to the connector.
Rule: don’t parallel an external LDO with Melexis’ internal one — OR it.
Put these numbers into your BOM notes so we can map to TI / ST / NXP / Renesas / onsemi / Microchip / Melexis parts.
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Frequently Asked Questions
Can I cascade two LDOs to reduce noise from a DC/DC?
Yes, if you still have voltage headroom. The first LDO removes most of the ripple and spikes the DC/DC cannot, and the second low-noise LDO cleans the last tens of microvolts. If headroom is tight, use a single higher-PSRR LDO instead.
Is cascaded LDO always better than a single high-PSRR LDO?
Not always. Two LDOs in series double the dissipation and reduce your margin at high temperature. If your rail has very little Vin–Vout budget, a single high-PSRR device or DC/DC + LC is safer than forcing a cascade.
How do I test that the downstream LDO is not pulling down the upstream one?
Apply a step load on the second LDO while probing the first LDO output. If the upstream falls below its guaranteed Vout(min), your headroom is too small or the upstream phase margin is low. Log both waveforms in the BOM note.
How much voltage headroom do I need between cascaded LDOs?
As a rule: Upstream Vout(min) ≥ Downstream Vout + Downstream Dropout(max @ load, 125°C). Then add DC/DC tolerance and cable loss. If this stack cannot be met, do not cascade — choose a better PSRR part.
What happens if the headroom is not enough at 125°C or cold crank?
The downstream LDO will fall out of regulation first, then the upstream may oscillate or pull PG low. At automotive temperatures this shows up earlier. That is why we check the budget at hot and at the lowest expected VIN.
Can I still cascade if the DC/DC output tolerance is wide?
Only if you include that tolerance in the upstream Vout(min) term. A ±5% DC/DC can easily eat the whole headroom. Sometimes it is cleaner to tighten the DC/DC or raise the first LDO by 100–200 mV before cascading.
Why can’t I parallel two LDOs directly on the same rail?
Because you are shorting two closed loops. Even 20–30 mV mismatch makes one LDO take almost all the load and the other start hunting. Parallel LDOs without isolation is effectively shorting two control loops.
What is the simplest OR-ing method for dual LDO outputs?
Two Schottky diodes after the two LDOs is the simplest, most obvious method. It lets the higher rail win and gives you natural backup. The trade-off is the diode drop, so it is fine for 5 V or 12 V but tight for 3.3 V.
When should I use ideal-diode OR-ing instead of Schottky OR-ing?
Use ideal-diode / FET OR-ing when you cannot afford the forward drop or you are feeding a precision / sensor / camera bias rail. It preserves redundancy but keeps the effective drop in the tens of millivolts instead of hundreds.
How big should the ballast resistor be for current sharing?
Start with tens of milliohms per LDO (for tens to hundreds of mA) and tune so the higher-voltage device does not take all the current. The formula is Ishare ≈ ΔV / Rballast. Do not oversize it on precision ADC or reference rails.
How do I validate stability when the downstream LDO makes a fast load step?
Do a 10→100 mA step (or your worst case) on the downstream LDO and watch the upstream LDO output. If the upstream sags or rings, your cascade margin is too small. Repeat at VIN(min) and at hot, because dropout grows with temperature.
What scope signals should I record in the BOM notes for requalification?
Capture: upstream LDO Vout, downstream LDO Vout, and the voltage across the OR-ing / ballast element. This lets purchasing compare another vendor’s LDO under the exact same dynamic load without redoing the whole bench.
Does adding OR-ing or ballast introduce new poles or zeros I should care about?
Yes, it adds a small series impedance, so a small pole/zero pair appears, but it is much less dangerous than two loops fighting. This is the reason we say: avoid loop sharing when paralleling — use OR-ing/load-share schemes.
Do automotive LDOs support cascading with discharge or tracking enabled?
Many AEC-Q100 LDOs do, but discharge/tracking consumes part of your headroom. When you enable those functions in a cascade, recheck the upstream-to-downstream voltage budget at hot and crank. Document the test result with the LDO part in the BOM.
For small-batch sensor bias rails, is ideal-diode OR-ing the safest option?
Yes, because it keeps redundancy but does not waste the few tens of millivolts you have. Small-batch automotive/sensor designs often have very narrow margins, so FET/ideal-diode OR-ing is preferred over Schottky.
