Introduction & Scope
This page explains how to combine an LDO with a load switch to achieve inrush-limited soft-start, active discharge (QOD), and downstream rail control (PG→EN). It targets small-batch prototypes and cross-brand replacements—actionable thresholds and validation, not a generic theory class.
- Topology: DC-DC → LDO → Load Switch → Load; control by PG → EN.
- Use cases: portable/industrial/automotive sub-systems needing controlled power-up/down and cross-rail safety.
- Out of scope: eFuse/Hot-Swap deep protection, ultralow-noise/ultrawide-PSRR pages, ultralow-Iq LDO extremes, radiation-tolerant space pages.
Key thresholds
- Inrush: choose dV/dt or ILIM so that
I_inrush ≤ I_source_limit × 0.7at worst caseC_load. - QOD: discharge time
t_dis ≈ R_eq × C_load—fast enough to be safe, slow enough to avoid cross-rail drag. - RCB: reverse current block enabled; specify
I_rev@V_revceiling for cross-rail safety. - PG/EN: verify
PG delayandEN VIH/VILcompatibility with the MCU family. - LDO stability: ESR window still valid after the downstream capacitor stack (phase margin ≥ 45°).
Combo Patterns
Three practical patterns—output-side switch, input-side switch, and dual switches—plus a simple rule for when to use only the output-side switch. Each option lists when to use it, trade-offs, thresholds, and what to validate.
Output-side (default)
- Use for C_load ≥ 100 µF, hot-plug, hard 0 V off.
- dV/dt or ILIM matched to source limit; RCB on; QOD sized.
- Validate: inrush peak, discharge to 0 V, cross-rail impact <5% Vnom.
Input-side (protect upstream)
- Use for weak sources, long cables, connector sparks.
- Set ILIM by source capability; add RCB or ideal diode.
- Validate: ΔVIN droop vs reset threshold; reverse leakage.
Dual switches
- Use for big Cload + hot-plug + fragile source.
- PG/EN ordering: PG_LDO→EN_out; power-down reverse.
- Validate: combined inrush, zero-residual window, thermal cycles.
Selection Criteria
Pick parameters that make the LDO + load switch combo predictable: inrush (dV/dt or ILIM), QOD discharge window, RCB against cross-rail reverse current, PG→EN logic compatibility, and thermal/ESD/automotive constraints.
Inrush (dV/dt vs ILIM)
Big Cload/hot-plug → ILIM preferred; sensitive analog → dV/dt.
I_inrush ≈ C_load·dV/dt ≤ I_source_limit×0.7t_rise ≈ C_load·ΔV / I_LIM(constant-current mode)
QOD (Active Discharge)
Reach hard 0 V without dragging neighbor rails.
t_dis ≈ R_eq·C_load- Typical: digital 10–50 ms; analog 50–200 ms
RCB (Reverse-Current Block)
Required when Vout > Vin can happen (multi-rail/USB/battery).
- Specify
V_rev,I_rev@V_revµA-level - Clamp behavior defined
PG→EN & Thresholds
- PG is “in-regulation & stable”, not just “on”
- Check
PG_delay,EN VIH/VIL, level type - RC/Schmitt de-glitch if needed
| Block | Key fields | Threshold / rule of thumb |
|---|---|---|
| Inrush | Mode (dV/dt or ILIM), dV/dt (V/ms) or ILIM (A), C_load (µF) | I_inrush ≤ 0.7×I_source_limit; t_rise ≈ C·ΔV/I_LIM |
| QOD | QOD (Y/N), R_dis (Ω), t_dis (ms) | Digital 10–50 ms; Analog 50–200 ms; cross-rail < 5% Vnom |
| RCB | RCB (Y/N), V_rev (V), I_rev@V_rev (µA), clamp | Enable for any Vout>Vin possibility; define µA ceiling |
| PG→EN & Levels | PG_delay (ms), PG type, EN VIH/VIL (V) | PG = stable; add RC/Schmitt for de-glitch |
| Thermal/ESD/Auto | R_ON (mΩ), ΔT @ I, TSD (°C), HBM/CDM/IEC, AEC-Q/Temp, Pkg | ΔT within limit; IEC for user-exposed ports; AEC-Q when required |
Sequencing & Rail Control
Default order: Core → Analog → IO → Aux on power-up, and the reverse on power-down. Use PG (upstream/LDO) → EN (switch) for each step; verify there is no cross-rail backfeed or residual voltage windows.
Enable order
- Core stable → PG_core triggers EN_analog
- Analog stable → EN_IO
- IO stable → EN_aux
Power-down
- IO → Analog → Core → Aux
- Check QOD t_dis windows don’t drag neighbor rails
- RCB remains enabled at all stages
De-glitch & levels
- PG = stable, not just “on”
- RC/Schmitt on PG if needed
- Match EN VIH/VIL with MCU logic
| Rail | Type | Enable source | PG delay (ms) | EN hold-off (ms) | Power-down order | QOD t_dis (ms) | RCB | Notes |
|---|---|---|---|---|---|---|---|---|
| Core | Core | PG_upstream | 5–20 | — | 3 | 20–50 | On | Phase-margin ok with C_stack |
| Analog | Analog | PG_core + EN_ext | 5–15 | 1–10 | 2 | 50–200 | On | Avoid cross-rail drag |
| IO | IO | PG_analog | 5–30 | 5–50 | 1 | 10–50 | On | RC/Schmitt for PG |
Stability & Layout Rules
Keep the combo stable: control the ESR window, place a minimal current loop, use Kelvin sense to the load node, and ensure QOD/RCB paths do not create backfeed or cross-rail drag.
ESR window
- Total Cout = LDO rec. + Cload
- Add local 1–4.7 µF + 10–100 mΩ ESR if needed
- Phase margin ≥ 45° after stacking
Minimal loop
- LDO OUT → SW_out → Cload → PGND loop shortest
- Cload grounds meet at a single point
Kelvin sense
- Sensing/PG to the load node
- Route away from high-current copper
QOD & RCB paths
- QOD path shortest; add 1–4.7 Ω if dragging neighbor rails
- RCB enabled; avoid OUT→IN copper bypass
Validation Playbook
Verify four essentials: inrush ramp, QOD discharge to 0 V, reverse current with RCB, and PG→EN sequencing under A/B conditions (temp/Cload/source strength).
Inrush
- Iinrush ≤ 0.7×Isource
- No >10% Vout ringing; trise as calculated
QOD
- tdis in target window
- Neighbor rail impact < 5% Vnom
Reverse Current
- RCB enabled; Irev@Vrev within µA ceiling
- No unintended conduction
PG→EN A/B
- PG jitter < 1 ms; EN gated by PG
- Works across temp/Cload/source variants
| Profile | Iinrush / trise | tdis / cross-rail | Irev@Vrev | PG jitter / gating | Verdict |
|---|---|---|---|---|---|
| A (25 °C · C=1× · strong) | ≤ 0.7×Isource / OK | Window hit / <5% | µA ceiling | <1 ms / gated | Pass |
| B (−40/125 °C · C=2× · weak) | ≤ 0.7×Isource / OK | Window hit / <5% | µA ceiling | <1 ms / gated | Pass / Limit / Fail |
Mini IC Matrix — LDO + Load Switch (Real Parts)
Curated pairs for predictable inrush, QOD discharge, RCB reverse blocking, and clean PG→EN sequencing. Cards include one-line rationale and typical use.
Texas Instruments
Combo highlight: Low-noise LDO with automotive-grade switch offering ILIM+QOD+RCB for safe ramps.
Typical use: MCU/FPGA aux rails with hot-plug risk.
STMicroelectronics
Combo highlight: Clean analog rail with reverse-protect high-side switch.
Typical use: Sensor/AFE post-reg with safe hot-plug.
NXP
Combo highlight: One-chip multi-rail with onboard switch and sequence control.
Typical use: i.MX/SoC boards needing compact rail control.
Renesas
Combo highlight: Robust reverse-blocking with gentle soft-start plus quiet LDO.
Typical use: Mixed-signal AVDD/DVDD split rails.
onsemi
Combo highlight: Readily available, balanced specs for common rails.
Typical use: Aux IO, peripheral power gating.
Microchip
Combo highlight: Strong QOD for fast, repeatable soft-off.
Typical use: Portable devices needing guaranteed reset.
Melexis (positioning note)
Combo highlight: Suitable for integrated implementation of power domains inside actuator modules.
Typical use: Automotive actuator nodes.
Texas Instruments (alt)
Combo highlight: 1 A low-noise LDO with tiny low-RON switch for dense layouts.
Typical use: Imaging/FPGA split rails with tight space.
FAQs: Inrush, QOD, RCB, and PG→EN Sequencing
How do I size dV/dt or ILIM to cap inrush without false trips?
Start with C_load and target slope: dV/dt = I_inrush/C. Limit I_inrush to ≤70% of source current or upstream limit. If using ILIM, include cable and ESR tolerance. Verify the scope-measured peak, rise time, and overshoot across temp and C_load = 1×/2× profiles.
When is QOD mandatory, and what discharge window should I target?
Use QOD when the next power-up requires a guaranteed 0 V start or when downstream logic latches on residual charge. Aim for a controlled pull-down to 0 V within 10–50 ms for small rails and 50–200 ms for larger C_load. Confirm no cross-rail drag or ground bounce.
What’s the cleanest way to guarantee reverse blocking when Vout > Vin?
Select a load switch with true reverse current blocking (RCB) active whenever Vout > Vin. Avoid copper bypass from OUT to IN. Test with a bench source forcing Vout above Vin and measure I_rev at defined V_rev. The pass criterion is typically in the microamp range.
Should LDO PG directly gate the switch EN, or pass through logic/RC?
Direct PG→EN is simplest if voltage levels match and PG jitter is low. Add RC or logic gating when debounce is needed, multiple rails vote, or PG polarity differs. Validate with an A/B timing plot: PG stable margin, EN threshold clearance, and <1 ms jitter before enable.
How do stacked capacitors change the LDO’s ESR window and phase margin?
Parallel caps reduce effective ESR and may shift the zero outside the stability window. After adding local C_load at the switch output, recalc ESR bounds and recheck loop phase margin (≥45° recommended). Pay attention to dielectric type and temperature drift of ESR/ESL.
Why does my rail ring at turn-on even with a soft-start switch?
Soft-start limits current, but layout and loop dynamics still matter. Long return paths, shared grounds, or sensing at the wrong node can create underdamped behavior. Minimize the OUT→SW_out→C_load→GND loop, use single-point ground, and Kelvin-sense at the load node.
What is the minimal current loop in LDO + load-switch placement?
The shortest loop is LDO OUT → switch OUT → local C_load → PGND back to the LDO. Physically cluster these components and meet grounds at one point. Keep high-current copper away from PG/EN traces. This reduces ringing, crosstalk, and false PG transitions.
Where should I Kelvin-sense PG/monitor lines to avoid mis-trips?
Sense at the actual load node, not at the regulator pins. Route monitor lines away from high-current paths and add a quiet ground guard. This captures the true delivered voltage and prevents switching spikes from toggling PG or tripping comparators during transients.
How do I test reverse leakage I_rev@V_rev and set a pass limit?
Back-bias the output above input using a precision source. Measure steady-state reverse current with RCB enabled at defined V_rev steps (e.g., 0.2, 0.5, 1.0 V). Set a microamp-scale ceiling matching datasheet or system budget, and confirm no thermal rise or latch conditions.
What PG jitter is acceptable before enabling the next rail?
Keep PG jitter under 1 ms for tight sequences unless the downstream device tolerates more. Validate at −40/25/125 °C and with C_load = 1×/2×. Gate EN only after PG is high for a defined margin (for example 2–5 ms), then confirm stable thresholds across process variation.
How do I prevent cross-rail drag during QOD discharge?
Ensure the QOD path is short and returns to the same ground node. If neighbor rails droop, add a small series resistor in the QOD path, separate return routes, or delay adjacent QOD events. Verify with a two-rail scope capture and limit neighbor drop to under five percent.
What CSV fields should I log for an A/B validation matrix?
Record profile (A/B), temp, C_load, source strength, dV/dt or ILIM setting, peak inrush, rise time, ringing percent, t_dis to 0 V, neighbor rail droop, I_rev@V_rev, PG jitter, EN delay, and verdict. This enables fast regressions and clear pass/limit/fail decisions.
When do I use pre-reg LDO before the switch vs switch-then-LDO?
Choose LDO→switch when you need a quiet rail that is power-gated after regulation. Use switch→LDO for upstream gating with a final cleanup stage per load domain. The latter improves isolation but doubles startup interactions. Model sequences and verify both inrush and QOD.
Does active discharge affect stability or noise at the next power-up?
Active discharge itself is off during the next start, but residual charge paths and partial bias can alter the initial conditions. Insert a brief re-arm delay after 0 V confirmation, and verify the first milliseconds for overshoot or false PG. Keep measurement bandwidth consistent.
What layout traps commonly destabilize an otherwise stable combo?
Split grounds without a defined meet point, long OUT traces before C_load, monitoring sensed at the regulator instead of the load, and copper “shortcuts” that bypass RCB. Fix by shrinking the current loop, single-point grounding, Kelvin-sensing, and avoiding OUT→IN leakage paths.
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