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Light-Load Efficiency Modes in Buck/Boost Regulators

Buck / Boost / Buck-Boost Regulators

Introduction & Search Intent Mapping

This page focuses on light-load efficiency behavior and mode orchestration for Buck / Boost / Buck-Boost / SEPIC / Zeta rails. We center on CCM control and call out light-load PFM specifics where behavior diverges. The goal is to minimize idle loss, avoid audible/EMI issues, and keep transitions stable.

Scope: peak/valley current-mode control (CMC), voltage-mode, and digital loops; slope compensation, VIN feed-forward, load-line (AVP/D-LAV); and Bode injection & measurement targets.
Control Core Peak CMC Valley CMC Voltage Digital Slope Comp VIN Feed-Forward AVP / D-LAV Light-Load Trilemma Efficiency EMI / Acoustics Transient Bode Injection & Measurement Targets • Inject at COMP (PWM/CCM); disable PFM/skip/burst during sweep • Phase margin ≥ 45–60°, gain margin ≥ 6 dB • Crossover ≈ 0.1–0.2 × fsw; re-check at VIN extremes & near mode boundary

Search Intent Coverage

  • Know: what PFM/skip/burst/SR-off/hiccup mean; CCM↔DCM boundaries.
  • Compare: peak vs valley CMC; voltage-mode vs current-mode vs digital (noise, transient, complexity).
  • Select/Do: set entry/exit thresholds; decide slope comp; enable VIN feed-forward; pick AVP; plan Bode tests.

Applicable to Buck / Boost / Buck-Boost / SEPIC / Zeta. CCM is the baseline; PFM specifics are highlighted at light load.

Control Modes Overview

Compare peak vs valley sampling, loop architectures, and when slope compensation is mandatory. Includes practical rules for Boost/Buck-Boost and guidance for AVP/D-LAV & Bode testing.

Peak-CMC vs Valley-CMC

Sampling instant: Peak samples at the end of on-time (rising current), Valley samples at the start of on-time (falling current).

Peak-CMC (sample at end of on-time) Rising inductor current; compare at the peak Needs slope comp when D > 0.5 (Buck) Valley-CMC (sample at start of on-time) Falling inductor current; compare at the valley Mirror condition near low duty; often tolerant at high duty in Buck
Aspect Peak-CMC Valley-CMC
Sample instant End of on-time (rising current) Start of on-time (falling current)
Subharmonic condition (Buck) Needs slope comp when D > 0.5 Mirror tendency at low duty; more tolerant at high duty
Noise sensitivity On-time jitter & SW-node coupling Off-time accuracy & DCM boundary detect
Transient character Crisp step-down, strong current limiting Smoother near light-load transition/burst
Use cases Fast transient, tight protection Mode-boundary comfort, light-load orchestration

Voltage-Mode vs Current-Mode vs Digital (PID/Type-III)

ArchitectureStrengthsTrade-offsWhen to use
Voltage-Mode Low noise injection; simple hardware; pairs well with VIN feed-forward Weaker current limiting; often needs Type-III in Buck CCM EMI predictability, moderate dynamics, fixed-PWM preference
Current-Mode (Peak/Valley) Inherent line feed-forward; strong current limit; often simpler outer loop Requires slope comp; sense-RC design critical Fast transients, robust protection, mode-boundary control
Digital Adaptive gain; non-linear burst/skip; telemetry; easy AVP/D-LAV Clock/quantization noise; latency; firmware validation Multi-rail coordination, PMBus/telemetry, field configurability

When Slope Compensation Is Mandatory

  • Peak-CMC (Buck): if D > 0.5, add comp such that effective comp slope meets practical need; noisy sense path → stronger comp + carefully chosen sense-RC.
  • Boost / Buck-Boost: asymmetric current ramp; subharmonic artifacts appear earlier than Buck intuition—verify/tune even at moderate duty.
  • Valley-CMC: watch low-duty mirror; coordinate comp with valley detect blanking near DCM/CrCM.
  • With PFM/skip/burst: set entry/exit hysteresis to prevent chatter; ensure PWM resumption isn’t over-damped.

Feed-Forward & Load-Line (AVP / D-LAV)

VIN feed-forward stabilizes PWM gain vs VIN, improving line-step performance across mode changes.

Load-line (AVP/D-LAV): set droop \(V_{droop}=I_{load}\cdot R_{LL}\) to trade overshoot for static error; modest RLL widens the safe zone when exiting burst.

Bode Injection & Measurement Targets

  • Inject at the error-amp/COMP in PWM/CCM; disable PFM/skip/burst during the sweep.
  • Targets: PM ≥ 45–60°, GM ≥ 6 dB, fc ≈ 0.1–0.2 × fsw.
  • Re-check at VIN min/max, temperature corners, and near the mode boundary.

Power Stage Poles/Zeros by Topology

Set a stable crossover and phase margin by understanding the plant. Lock the converter in PWM/CCM for loop measurements; PFM/burst/hiccup makes the system time-variant.

Buck f0 ≈ 1/(2π·sqrt(L·C)) fz_ESR ≈ 1/(2π·C·ESR) Set fc ≈ 0.1–0.2 × fsw Boost / 4-Switch BB fRHPZ ≈ Rload·(1−D)^2 / (2π·L) Non-minimum phase (step-up) Keep fc ≤ 0.2 × fRHPZ SEPIC / Zeta Coupled/series L → effective double-pole Dual ESR zeros (Cout, Cseries) Start Type-II; tame HF features Light-Load Modes & Measurement • Force PWM/CCM during Bode injection • PFM/Burst/Hiccup → time-variant loop (invalid sweep) • After tuning, re-enable light-load mode and re-check transients
Topology Dominant Poles Zeros RHPZ? Safe fc Rule Notes
Buck LC double-pole at f₀ ≈ 1/(2π√(LC)) ESR zero fz,ESR ≈ 1/(2π·C·ESR) No fc ≈ 0.1–0.2·fsw Ceramic C → high fz,ESR; don’t rely on ESR phase boost
Boost Plant pole near LC ESR zero Yes (step-up) fc ≤ 0.2·fRHPZ Non-minimum phase: duty ↑ → Vout dips initially
4-Switch Buck-Boost Quadrant dependent ESR zero Boost quadrant: Yes Respect boost-side fRHPZ Buck quadrant behaves like Buck
SEPIC Effective double-pole (coupled/series L) Two ESR zeros (Cout, Cseries) Can behave like step-up Keep fc below lowest HF feature Model coupling factor k for accurate pole split
Zeta Similar to SEPIC (inverting flow) Dual ESR zeros Step-up characteristics Start conservative fc Tame peaking from dual zeros
Measurement rule: For PFM/burst/hiccup, force PWM/CCM during Bode injection; after tuning, re-enable the light-load mode and validate transient/ripple.

Compensation Types & Design Recipes

Target PM ≥ 55–65°, GM > 6–10 dB, and fc ≤ fsw/5. With very low ripple inductors or strong sense filtering, reduce noise gain and consider a lower fc.

Type-II (Buck/Boost baseline) • Pole at origin · one mid-band zero · one HF pole Place zero near f₀; HF pole near fz,ESR or 0.5·fsw Type-III (Buck high bandwidth) • Two zeros around f₀ · pole at origin · two HF poles Bracket f₀ with zeros; add HF poles for noise roll-off Digital PID/Type-III • Discretize (Tustin / matched-PZ); pre-warp around fc • Budget latency (ADC + compute + PWM); lower fc if needed • Watch comb/spur clusters from clocks; keep bandwidth below spurs
Topology / Situation Preferred Type fc Rule Zero Placement HF Pole Placement Notes
Buck (high bandwidth, ceramic C) Type-III 0.1–0.2·fsw Two zeros bracketing f₀ Near fz,ESR and ~0.5·fsw Don’t rely on ESR zero for phase with MLCC
Boost / Buck-Boost (step-up region) Type-II ≤ 0.2·fRHPZ Zero near f₀ (adds phase) One HF pole to suppress noise Never cross RHPZ with fc
SEPIC / Zeta Type-II (start) Below lowest HF feature Zero near effective LC pole At ESR zeros / 0.5·fsw Consider pseudo Type-III if phase shortfall
Digital loop (PMBus/telemetry) Digital PID/Type-III 0.05–0.15·fsw (latency aware) Mirror analog targets (pre-warped) Roll-off to avoid quantization noise gain Account for ADC + PWM update delay

Quick Design Recipe

  1. Estimate plant: f₀, fz,ESR, and fRHPZ (if step-up).
  2. Choose fc: 0.1–0.2·fsw; for step-up, keep ≤ 0.2·fRHPZ.
  3. Place zeros: Type-II → near f₀; Type-III → bracket f₀ for +phase.
  4. Place HF poles: near fz,ESR and/or ~0.5·fsw to reduce noise gain.
  5. Set DC gain to hit fc; verify PM ≥ 55–65° and GM > 6–10 dB.
  6. Force PWM/CCM, run Bode; re-enable light-load mode and validate transient/ripple.
Guardrails: With very low ripple inductors or heavy sense filtering, lower fc and keep compensation noise gain modest to avoid jitter amplification.

Slope Compensation (CMC Essentials)

Address subharmonic oscillation in PWM/CCM by adding an artificial ramp to the sensed current. Provide portable ratios so designs migrate cleanly across ICs and brands.

Peak-CMC (D > 0.5): subharmonic risk Rising m₁ Falling m₂ Period-doubling without artificial ramp Add ramp ma to stabilize ma ≈ α·m2 Portable Rules • Minimal condition (Buck ref.): ma ≥ (m2 − m1)/2 • Ratio α ≡ ma/m2 ≈ 0.6–0.8 (robust default), up to 0.9–1.0 for noisy paths • Valley-CMC: smaller α; ensure valley detect blanking near DCM/CrCM • Boost/BB: asymmetric ramp → need slope comp earlier than Buck intuition

Design Notes & Migration

  • Buck mapping: m1 = ((VIN − VOUT)/L)·ks, m2 = (VOUT/L)·ks.
  • Boost/BB: treat step-up quadrant with stricter α; verify across duty and VIN extremes.
  • Starting point: set α = 0.7; raise toward 0.9–1.0 for high-fsw or noisy sense.
  • Sense filtering: keep RC time constant ≈ Tsw/10 to limit phase lag; add leading-edge blanking.
Topology CMC Type Suggested α = ma/m2 Notes
Buck Peak 0.6–0.8 (start 0.7) D > 0.5 needs comp; verify across VIN
Buck Valley 0.4–0.6 Watch low-duty edge; add valley blanking
Boost / Buck-Boost Peak 0.7–1.0 Asymmetric ramp; treat earlier than Buck
SEPIC / Zeta Peak 0.6–0.9 Coupled L affects sensed slope; re-check poles

Implementation Patterns

  1. Injection resistor (Rinj): feed an internal ramp into the sense summing node; tune ma via Rinj.
  2. External RC ramp: clock/driver → Rfeed → Cramp to GND; scale via divider into sense node.
  3. COMP/SLOPE pin networks: Rc–Cc core, optional Cp for HF pole; some ICs expose SLOPE program by a resistor to VREF/GND.
  4. Validate: force PWM/CCM for Bode; confirm PM≥60° near mode boundary; then re-enable PFM/burst and verify transients.
Boost inner loop caution: Even with strong slope comp, never set loop crossover near a step-up RHPZ; keep fc well below 0.2·fRHPZ.

Feed-Forward & Load-Line (AVP / D-LAV)

VIN feed-forward (VFF) flattens modulator gain vs VIN; AVP/D-LAV trades controlled droop for smaller output capacitance and smoother burst exit/entry.

VIN Feed-Forward (VFF) V< tspan baseline-shift="sub">IN Scaler k·V< tspan baseline-shift="sub">IN PWM Comparator • Flattens modulator gain vs VIN (near-zero phase) • Better line-step, more invariant f< tspan baseline-shift="sub">c/PM across VIN • For Boost/BB: still respect RHPZ bound AVP / D-LAV (Load-Line) V< tspan baseline-shift="sub">droop = I< tspan baseline-shift="sub">load · R< tspan baseline-shift="sub">LL Higher R< tspan baseline-shift="sub">LL → more droop, smaller C< tspan baseline-shift="sub">out Tuning Order 1) Force PWM/CCM, disable light-load modes 2) Enable VFF and tune compensation (respect RHPZ in step-up) 3) Add AVP: choose R< tspan baseline-shift="sub">LL = ΔV< tspan baseline-shift="sub">allow / ΔI< tspan baseline-shift="sub">step 4) Restore burst/skip thresholds; co-tune hysteresis & R< tspan baseline-shift="sub">LL 5) Validate line/load steps, acoustics, EMI

Quick Formulas & Guardrails

  • Load-line sizing: RLL = ΔVallow / ΔIstep (start small: 0.5–1 mΩ/A for low-voltage rails).
  • VFF: scale PWM ramp or duty command by k·VIN; improves line consistency with near-zero extra phase.
  • Step-up quadrants: keep fc ≤ 0.2·fRHPZ even with VFF present.
  • Accuracy note: AVP reduces DC setpoint under load—specify a load-regulation window.
Use Case VFF AVP Target Expected Benefit Risk / Mitigation
Wearable / battery rail Yes (Buck) Small RLL for overshoot control Stable fc vs VIN, smoother burst exit DC accuracy → tighten calibration window
Industrial 24 V front-end Yes (Buck/BB) Moderate RLL, EMI-first thresholds Better line steps, smaller Cout RHPZ in BB boost quadrant → cap fc
Automotive standby rail Yes Small RLL + larger hysteresis Reduced ping-pong at mode boundary Cold-crank transients → verify margins
Digital D-LAV: include sampling/compute latency in the phase budget, pre-warp the discrete compensator near fc, and keep the loop bandwidth below known spur clusters.

Bode Hooks & Measurement Playbook

Choose the right injection hook and fixture path, then sweep to read fc, phase margin, and gain margin—while avoiding errors from light-load PFM, current-limit knees, and soft-start/UV/OTP boundaries.

Hook: COMP (Error Amplifier Output) Freq. Source Injection T/F COMP • Moderate impedance, good signal control • Add a small series resistor if needed for shaping Hook: FB Divider Node Freq. Source Divider Inj. FB • Control the effective impedance at FB • In current-mode, avoid noise pickup from SW node Fixture & Cabling • Injection transformer/divider, 50 Ω matching on source/analyzer • Local star ground, very short ground lead, shield the loop • Keep injection loop away from SW node; add small RC snubbers if needed

Frequency Sweep & Readouts

  • Sweep 10 Hz → ~0.5·fsw (cut earlier if a boost-side RHPZ exists)
  • Force PWM/CCM; disable PFM/burst/hiccup and current-limit modulation
  • Record baseline noise, then closed-loop; open-loop capture is optional for reference
  • Read fc at 0 dB, phase margin (PM), and gain margin (GM)
  • Repeat at VINmin/VINmax and temperature corners

Common Pitfalls & Remedies

Pitfall Symptom Remedy
Light-load PFM active Time-varying loop, non-repeatable traces Force PWM/CCM during sweep
Near current-limit knee Inflated/erratic crossover, false PM/GM Back off load; sweep away from limit
Soft-start/UV/OTP interaction Drifting DC operating point Fully reset SS; ensure margin to UV/OTP
Over/under injection amplitude Nonlinear distortion or poor SNR Adjust injection level for linear response
FB node impedance too high/low Measurement loading or bypass Impedance shaping resistor / buffered hook
Measurement rule: Always validate with light-load modes re-enabled after tuning—check burst/skip entry-exit transients and ripple.

Multiphase & Beat-Avoidance

Arrange phases to minimize combined ripple, then avoid beat notes by changing phase offsets first, fsw/fc second, and enabling spread-spectrum last. Choose shared vs per-phase compensation based on current sharing strategy.

Step 1 Adjust Phase Offsets Step 2 Move f_sw / f_c Step 3 Enable Spread-Spectrum Notes • Light-load phase shedding changes offsets dynamically—set hysteresis windows • Keep current-sharing loop bandwidth ≤ power loop f_c / 3 • Avoid sensor/ADC/audio bands when choosing beat relocation
Phases Recommended Phase Offsets Ripple Attenuation (ideal) Notes
2 180° ~−6 dB on fundamental Simple and robust
3 120°–120°–120° ~−9.5 dB Good harmonic cancellation
4 90°–90°–90°–90° ~−12 dB Even harmonics reduced
6 60° steps (0–300°) ~−15.5 dB Best granularity, watch control bus latency

Shared vs Per-Phase Compensation

Architecture Pros Cons When to Use
Shared Error Amplifier Simpler; natural current sharing via common COMP Drift on one phase affects the group; limited per-phase tuning Uniform phases, modest dynamics, tight BOM
Per-Phase Compensation Per-phase tuning; supports sub-loops and balance control Higher complexity; needs share bus or AVG current loop High-current systems, non-uniform phase hardware
Hybrid (Shared V-loop + Per-phase I-loops) Global voltage stability with local current protection Integration effort; careful bandwidth partitioning Server/auto rails; strict transient & telemetry
Beat-avoidance order: Phase offsets → move fsw/fc → enable spread-spectrum. Re-verify EMI and acoustics after each change.

Special Cases & Edge Conditions

Handle USB-PD PDO switching, pre-bias start-up, temperature/tolerance drift, and spread-spectrum interactions so your loop remains stable and your measurements remain trustworthy.

PDO Switch Window Force PWM/CCM Disable PFM/Skip/Burst Integrator Softening Dwell Crossover & Quadrants • Set fc by the worst quadrant (boost-like RHPZ) • Keep fc ≤ 0.2·fRHPZ during/after PDO transitions Blue: actual crossover; Gray dashed: guard line across PDO steps
Pre-Bias Start-up & Soft-Start No discharge line (SR-off / Diode emulation) Time → Vout
Spread-Spectrum vs Crossover Spread band around fsw frequency → Keep fc away from spread edges (≈ ≥ band/5)
Scenario Primary Risk Strategy Measurement Notes
USB-PD PDO switch Mode flips; worst-case boost quadrant Temporary PWM lock; disable PFM/skip; soften integrator; dwell Set fc by worst quadrant; verify per PDO pair
Pre-bias start-up Reverse discharge / inrush SR-off/diode emulation; gentle soft-start slope Start from 0.2–0.9·Vtarget; ensure “no-discharge”
Temp/tolerance drift fo, fz,ESR shift; L(μ) drop Design PM ≥ 60°; optional lower fc at cold Bode at VIN min/max and T low/high
Spread-spectrum on Ambiguous sweep; low-freq energy clusters Disable during sweep; else keep fc away from edges Use narrowband spread; re-check acoustics/EMI
Guardrail: During any automated mode or PDO transition, enforce a minimum dwell time and hysteresis around thresholds to prevent ping-pong behavior.

Quick Recipes (Copy-Paste Cards)

Three ready-to-use setup cards: Buck-HS (high-speed), Boost (RHPZ-limited), and 4-Switch Buck-Boost (quadrant-aware). Copy, paste, and adapt.

Buck-HS (Type-III) fc ≈ fsw/8 Z1 ≈ fo, Z2 ≈ fz,ESR Boost (RHPZ-limited) fc ≤ fRHPZ/5 Type-II + HF pole for noise roll-off 4-Switch Buck-Boost Set by worst quadrant Buck-like Boost-like

Buck-HS / High-Speed (Type-III)

Target: f_c ≈ f_sw / 8
Comp: Type-III
Z1 ≈ f_o (slightly below), Z2 near f_z,ESR
HF Poles: near f_z,ESR and ≤ 0.5·f_sw
  • Design for PM ≥ 60°, GM > 6–10 dB
  • With low-ripple inductors or strong sense-RC, lower f_c to avoid noise gain
  • Disable PFM/spread during sweep; sweep up to ~0.5·f_sw

Boost / RHPZ-Limited (Type-II)

Target: f_c ≤ f_RHPZ / 5 (≤ 0.2·f_RHPZ)
Comp: Type-II
Zero near f_o; 1 HF pole for noise roll-off
  • Never cross the RHPZ with f_c
  • Validate PM 55–65° across VIN/load
  • Cut sweep before RHPZ; test PDO/line steps

4-Switch Buck-Boost (Quadrant-Aware)

Model Buck-like vs Boost-like paths
Set f_c by worst quadrant
Buck-like → Type-III; Boost-like → Type-II
  • Lock PWM during quadrant transitions; add hysteresis + dwell
  • Re-check EMI/acoustics when spread-spectrum is enabled
  • Scan full VIN/VOUT matrix; track minimum PM/GM
Scenario Crossover Rule Comp Type Zero / Pole Placement Guardrails Measurement Upper Limit Common Pitfalls
Buck-HS fc ≈ fsw/8 Type-III Z1 ≈ fo, Z2 ≈ fz,ESR; HF poles near fz,ESR and ≤ 0.5·fsw PM ≥ 60°, GM > 6–10 dB ~0.5·fsw Noise gain with too-high fc, spread on during sweep
Boost (RHPZ-limited) fc ≤ fRHPZ/5 Type-II Zero near fo; 1 HF pole for noise roll-off Never cross RHPZ; PM 55–65° Stop before fRHPZ Mis-estimating RHPZ; PDO-switch transients
4-Switch Buck-Boost Set by worst quadrant Type-III (buck-like), Type-II (boost-like) Match zeros to fo/fz,ESR; conservative HF poles PWM lock during transitions; hysteresis + dwell ~0.5·fsw (buck-like); pre-RHPZ (boost-like) Beat notes with spread; insufficient dwell; uneven phases
Copy-paste tip: Start from the card that matches your quadrant and power stage. Tune zeros around fo, keep HF poles conservative, and verify PM/GM at VINmin/VINmax with light-load modes disabled during the sweep.

Validation & Sign-off Checklist

Close the loop with repeatable measurements and a fix-forward path. Cover Bode (PM/GM/fc), ±50% load steps, VIN transients, temperature sweep, and tolerance stack-up.

Tests Bode (PM/GM/fc) ±50% load step VIN transients Gates PM ≥ 55–65° GM > 6–10 dB fc per topology Quick Fix Lower fc / add phase HF pole for noise Hysteresis & dwell Long Fix L/C change Rsense/VFF/AVP Phase matrix

Sign-off Gates

  • Bode: PM ≥ 55–65°, GM > 6–10 dB; fc ≤ fsw/5 (buck-like), ≤ 0.2·fRHPZ in boost-like regions
  • ±50% Load Step: overshoot/undershoot within spec; stable re-entry from burst/skip; no ping-pong
  • VIN Transients: USB-PD PDO script or automotive cold-crank; verify with/without PWM lock
  • Temperature Sweep: capture fo, fz,ESR drift; PM at Tlow/Thigh ≥ 55° (≥ 60° preferred)
  • Tolerance Stack: worst-case L/C/ESR/Rsense/Vref; re-run Bode and steps

Record Templates

Bode Record

fsw: ____ kHz | fc: ____ kHz | PM: ____ ° | GM: ____ dB
Hook: COMP / FB | Sweep: 10 Hz → ____ kHz | Light-load modes: OFF
Notes: ______________________________________

±50% Load Step

ΔI: ____ A | Slew: ____ A/µs | C_out: ____ µF | R_LL: ____ mΩ
OV/UV: ____ / ____ % | Settling: ____ µs | Burst thresholds: In ____ mA / Out ____ mA

VIN Transient & Temperature

VIN: ____ → ____ V (PDO pair / crank) | PWM lock: ON/OFF
T_low: ____ °C | T_high: ____ °C | PM(min): ____ ° | Notes: _________
Fix-forward path: try quick fixes first (fc/phase/HF pole & thresholds). If still failing, change L/C or sensing, adjust VFF/AVP, or re-partition multiphase bandwidth.

IC Selection Hooks (Concrete Examples)

Pin/register names that matter for compensation, current sense, feed-forward, load-line, mode control, soft-start/sync, and spread-spectrum. Use these as entry points in datasheets.

Generic DC/DC Controller COMP ISEN / CS SS / SYNC MODE VFF AVP / D-LAV Spread PGOOD IMON
Brand Example Parts COMP / Error Amp ISEN / CS VIN Feed-Forward AVP / Load-Line MODE / Light-Load SS / SYNC Spread-Spectrum
Texas Instruments LM5155 (Boost ctrl), TPS63070 (4-Switch BB), LM5116 (Buck ctrl) COMP pin (LM5155/LM5116); internal (TPS63070) CS/ISEN pins on controllers Ramp/VIN scaling on controllers AVP via FB/COMP summing (controller class) MODE/PFM pin (TPS63070); FPWM option SS/TRK; SYNC pin (varies) Available on select devices
STMicroelectronics L5985 (Buck), L7986A (Buck), STBB2 (Buck-Boost) COMP pin (L5985/L7986A) CS/ISEN (controller variants) Internal or divider-based VFF FB summing for droop (selected) MODE/PWM/PFM options SS pin; SYNC on some SKUs Spread on certain families
NXP MC34713 (Buck ctrl), PCA9460 (Buck charger), PF5020 (PMIC) COMP (MC34713); digital loop (PMIC/charger) CS on controller; sense via ADC on PMIC Internal VFF (controller/PMIC class) Digital droop/IMON (PMIC) MODE register (PMIC); PFM/PWM (charger) SS/SYNC (controller); soft-start in regs Spread available on select PMICs
Renesas ISL8117 (Buck ctrl), ISL81601 (Buck-Boost), ISL85410 (Buck) COMP pin (ISL8117/ISL81601) CS/ISEN pins (controller class) Feed-forward via ramp slope FB/COMP summing for AVP MODE/FS pins (FPWM/PFM) SS pin; SYNC/CLK on some parts Spread on selected devices
onsemi NCP3170 (Buck), NCV8876 (Boost ctrl), NCP3065 (Buck/Boost/SEPIC ctrl) COMP (NCP3170 controller-class SKUs) CS/ISEN on controllers Ramp/VIN feed-forward (controller) FB droop injection supported SKIP/MODE/FPWM options SS; SYNC on some industrial/auto Spread on selected lines
Microchip MIC28514 (Buck ctrl), MCP16301 (Buck), MCP16502 (Buck-Boost) COMP pin (MIC28514); internal (MCP16301) CS on MIC28514; sense via R on others VFF/ramp scaling (controller) FB/COMP summing; D-LAV in digital families PFM/FPWM mode pins (varies) SS pin; SYNC on MIC28xxx Spread on selected devices
Melexis MLX81116 (Automotive lighting ctrl), MLX81113 (LIN lighting), MLX81206 (Driver with buck) Digital loop (register-configured) Internal current monitor / sense path VIN-based digital feed-forward (regs) Digital load-line / IMON mapping MODE registers (PFM/SR-off per device) Soft-start timing via registers Spread/dither modes (device-dependent)

Datasheet Navigation (How to Locate Hooks Fast)

  1. Search terms: “COMP / COMPENSATION”, “CURRENT SENSE / ISEN / CS”, “FEED FORWARD”, “LOAD LINE / AVP / D-LAV”, “MODE / PFM / FPWM”, “SPREAD / DITHER”.
  2. Open Pin Descriptions and Functional Block Diagram; cross-check with Typical Application.
  3. Copy default thresholds/hysteresis for PFM/Skip/Burst and SR-off from the Electrical Characteristics.
  4. Confirm recommended compensation values/conditions to avoid conflicts with your fc/PM/GM targets.
Note: “Hooks” can be pins (analog controllers) or registers (digital/PMIC families). For internally compensated parts, treat COMP/VFF/AVP as internal and use available MODE/FS/REG controls.

FAQs — Light-Load Modes & Control

PFM vs Skip vs Burst — how do I choose?

Decide by efficiency, acoustic limits, and wake latency. PFM maximizes idle efficiency but clusters low-frequency energy. Skip suppresses pulses near zero current. Burst groups packets using hysteresis and suits µA–mA rails. Map thresholds to real loads and validate boundary transients per mode rules.

Fast way to set fc without crossing a boost RHPZ?

Estimate RHPZ first from load and L. Set crossover well below it—practically ≤ 0.2·fRHPZ. Use Type-II, place the zero near fo, and add one high-frequency pole for noise roll-off. Verify at VINmin/max and across duty. See PZ guide.

Where should I inject for Bode—COMP or FB?

Prefer COMP: moderate impedance and cleaner excitation. FB works if you control the divider impedance and avoid switch-node noise. In all cases, force PWM/CCM and disable PFM/burst during the sweep. Procedures and fixtures live in the Bode playbook.

How much artificial slope (ma) is enough for peak-CMC?

For a buck reference, use ma ≥ (m2−m1)/2 and start with α ≡ ma/m2 ≈ 0.6–0.8. Increase toward 0.9–1.0 for noisy sense paths or very high fsw. Valley-CMC usually needs less. Design notes in Slope Compensation.

Does VIN feed-forward really flatten loop gain?

Yes—proper VFF scales the modulator gain with VIN, making fc/PM more invariant across line. It adds nearly zero phase if implemented on the ramp or duty command. Still respect RHPZ in boost-like regions and retune PM if spread-spectrum is active.

How do AVP / D-LAV droop values translate to capacitor savings?

Choose RLL = ΔVallow/ΔIstep. Intentional droop reduces overshoot, letting you use smaller output capacitors for the same transient target. Co-tune with burst thresholds to avoid ping-pong near boundaries. Implementation paths are in Feed-Forward & Load-Line.

Why does my sweep look wrong with spread-spectrum on?

Frequency dithering smears the plant response, degrading coherence and phase accuracy. Disable spread during Bode sweeps, or keep fc far from the dither band edges (≥ one-fifth of spread bandwidth). Interactions and workarounds appear in Special Cases and Playbook.

Multiphase beat notes—phase offsets first or spread first?

Adjust phase offsets first (equal spacing: 2/3/4/6 phases), then move fsw/fc, and only then enable spread if needed. Keep current-share bandwidth ≤ power-loop fc/3. Full guidance in Multiphase & Beat-Avoidance.

How do I test safely near current-limit knees?

Back off from the knee during loop sweeps; limit modulation distorts the inner slope and inflates apparent crossover. Validate at multiple loads, then separately characterize the limit behavior with transient steps. See Bode setup and sign-off gates.

Pre-bias start-up—how do I avoid discharging the output?

Start in SR-off/diode-emulation so no reverse current flows. Use a gentle soft-start slope and verify no-discharge from 0.2–0.9×Vtarget. Check inrush and rise-time limits. More in Special Cases.

USB-PD PDO switches—what mode and fc guard should I use?

Lock PWM and disable PFM/skip during the switch window; soften the integrator and enforce dwell. Set crossover by the worst quadrant (boost-like RHPZ), keeping fc ≤ 0.2·fRHPZ. Procedures in PDO strategy.

Ceramic MLCC ESR is tiny—do I still place zeros around fo?

Yes—use Type-III on buck for high bandwidth: place two zeros bracketing fo, and locate high-frequency poles near fz,ESR and ~0.5·fsw. Do not rely on ESR phase boost with MLCCs; verify PM at VIN corners.

Digital loops—how much should I derate fc for latency?

Budget ADC, compute, and PWM update delay, then lower fc to preserve PM. Discretize with Tustin (pre-warp near fc) and keep bandwidth below known spur clusters. More in Digital compensation.

Where should I set burst thresholds for µA–mA loads?

Anchor thresholds to real standby currents with hysteresis and minimum dwell to prevent ping-pong. Validate exit/entry transients, ripple, and audible noise. Tuning order and examples live in Burst thresholds and Validation.

What gates must I pass for sign-off?

Meet PM ≥ 55–65°, GM > 6–10 dB; set fc per topology; pass ±50% load steps; verify VIN transients (PDO/cold-crank); confirm temperature/tolerance corners. Record results with the templates in Sign-off Checklist.

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