# Icnavigator


## Posts

- [Pack Pressure / Leak Detection (Charging Domain)](https://icnavigator.com/pack-pressure-leak-detection/): ← Back to: Battery Charging / Gauging / Protection / BMS Pack Pressure / Leak Detection — Intro & Applicability This page describes low-voltage, pack-internal pressure / leak detection channels that feed charging decisions, not HV insulation monitors. Keep this sentence as-is to prevent mixing with the “Insulation / Leakage Monitor (HV)” page in the same BMS hub. We put this sensing channel inside the Charging domain because most swelling, micro-leak, or vent events are discovered while the pack is being charged, just charged, or charged under high ambient temperature. Charging is the only function that can immediately remove the […]
- [Chassis/Connector Hotspot Guard (Charging Domain)](https://icnavigator.com/chassis-connector-hotspot-guard/): ← Back to: Battery Charging / Gauging / Protection / BMS Chassis/Connector Hotspot Guard in the Charging Branch This page explains a thermal guard that belongs to the charging upper control domain — above the cells/AFE and below the system/USB-C policies. It is not a generic battery over-temperature protection, and it is not a pack FET / eFuse cut-off. Its only job is: when the chassis or the connector gets hot because of charging, make the charger back off safely. The vertical stack here is: charger / power-path / USB-C on top → hotspot guard logic in the middle → […]

## Pages

- [Passenger Information System (PIS) for Rail Vehicles](https://icnavigator.com/applications/rail-transit-locomotive/passenger-information-system-pis/): Passenger Information System (PIS) for Rail Vehicles ← Back to: Rail Transit & Locomotive A rail Passenger Information System (PIS) is a content pipeline—from media source to Ethernet/PoE distribution to display and audio endpoints—where passenger experience depends on evidence-driven uptime across network quality, power continuity, EMC robustness, thermal reliability, and field logging. The practical goal is simple: no black screen, no stutter, no unexpected reboot—and when faults happen, the system must produce measurable counters and timestamps that point to the first fix. What a Passenger Information System is (and is not) in a rail vehicle A Passenger Information System (PIS) […]
- [Train-to-Ground (T2G) Gateway for Rail Backhaul](https://icnavigator.com/applications/rail-transit-locomotive/train-to-ground-t2g-gateway/): Train-to-Ground (T2G) Gateway for Rail Backhaul ← Back to: Rail Transit & Locomotive A T2G gateway is the boundary device between onboard Ethernet/TSN domains and public/private cellular backhaul. It stabilizes connectivity under motion by multi-link aggregation, protects deterministic traffic with QoS, preserves time observability with PTP/GNSS + holdover, and proves integrity through a hardware root-of-trust and signed evidence logs. Connectivity — stable sessions under roaming Determinism — bounded tail latency for critical flows Trust — provable integrity + audit-grade evidence H2-1. Page Promise: What “Good T2G” Guarantees “Good T2G” is not a feature checklist. It is a set of testable […]
- [Train Radio (GSM-R/FRMCS/4G/5G): Modem, RF, TSN & Timing](https://icnavigator.com/applications/rail-transit-locomotive/train-radio-gsmr-frmcs-4g-5g/): Train Radio (GSM-R/FRMCS/4G/5G): Modem, RF, TSN & Timing ← Back to: Rail Transit & Locomotive Train Radio is the on-board, rail-hardened communication node that delivers secure and time-aware IP connectivity between train systems and ground networks. It focuses on modem+RF robustness, deterministic Ethernet/TSN behavior, trusted GNSS/holdover timing, and key-protected security with explainable diagnostics under EN 50155/EN 50121 conditions. H2-1. Scope & Boundary (What this page solves) Train Radio (GSM-R / FRMCS / 4G / 5G) is the on-board cellular/railway radio node that provides secure, time-aware IP connectivity to train subsystems under harsh rail electrical and EMC conditions. The scope is […]
- [Thermal & Mismatch in Gate Driver ICs: Symmetry & Drift Control](https://icnavigator.com/technology/gate-driver-ics/thermal-mismatch/): Thermal & Mismatch in Gate Driver ICs: Symmetry & Drift Control ← Back to: Gate Driver ICs Thermal mismatch is a symmetry problem: the same PWM command produces different switching behavior across arms/phases once temperature gradients and drift alter delay, gate drive, and protection margins. Control it by budgeting ΔT, enforcing arm-to-arm matching rules, and proving correlation at temperature corners—then apply bounded compensation so timing, edges, and protection remain consistent over temperature. H2-1 · Definition: Thermal & Mismatch in Gate Driving Thermal & mismatch issues in gate driving are best defined as symmetry being broken: the same PWM command produces […]
- [SOA & Short-Circuit Energy: DESAT, Blanking, Soft Turn-Off](https://icnavigator.com/technology/gate-driver-ics/soa-short-circuit-energy/): SOA & Short-Circuit Energy: DESAT, Blanking, Soft Turn-Off ← Back to: Gate Driver ICs Core Idea This page turns a device SOA / ESC limit into concrete gate-driver settings—DESAT threshold, blanking/filter, soft turn-off, and clamp policy—so short-circuit energy is kept within a measurable budget. It also standardizes the proof method (timing stack + fixed integration window + pass criteria) to prevent “works in one lab, fails in another” acceptance disputes. H2-1. Definition: SOA vs Short-Circuit Energy (ESC) Unify terms and measurement windows, then map SOA limits to driver-adjustable knobs. Goal SOA is a time-bounded permission window Safe Operating Area (SOA) […]
- [Isolated Bias Noise: Decouple Bias Switching from ADC Sampling](https://icnavigator.com/technology/gate-driver-ics/isolated-bias-noise/): Isolated Bias Noise: Decouple Bias Switching from ADC Sampling ← Back to: Gate Driver ICs Isolated bias noise becomes an ADC problem only when switching energy is coupled (DM/CM) and time-coherent with the sampling window, turning “small ripple” into spurs, steps, or SNR loss. The fix is to control mode & timing first (avoid window hits), then harden return paths and PSRR@fSW so the noise cannot fold into measurement or control decisions. Definition & Scope This page defines isolated-bias noise strictly as the portion of bias switching that becomes measurable ADC error through either coherent sampling hits or low-impedance common-mode […]
- [Layout & Grounding for Gate Driver ICs](https://icnavigator.com/technology/gate-driver-ics/layout-grounding/): Layout & Grounding for Gate Driver ICs ← Back to: Gate Driver ICs Layout & grounding for gate drivers is about controlling current loops and return paths so high di/dt and high dv/dt energy cannot corrupt the driver’s reference. When partitions, Kelvin returns, plane continuity, and measurement references are correct, ringing, false triggers, and “mystery failures” become predictable, measurable, and fixable. Definition & Scope: What “Layout & Grounding” Means for Gate Drivers Layout & grounding is the hidden schematic of a gate-driver system. Most ringing, false turn-on, EMI symptoms, and “random” fault events come from parasitics + return-path mistakes, not […]
- [Interlocking & Vital Logic (Rail) — Redundant MCUs & Voter Design](https://icnavigator.com/applications/rail-transit-locomotive/interlocking-vital-logic-rail/): Interlocking & Vital Logic (Rail) — Redundant MCUs & Voter Design ← Back to: Rail Transit & Locomotive Interlocking & Vital Logic is built to fail safe by design: redundant channels and voters decide “permit vs inhibit” only when inputs, timing, and configuration are provably consistent, otherwise outputs de-energize and faults latch. The core value is evidentiary operation—every trip, mismatch, reset, and recovery is measured and logged with integrity so audits and field replay can reproduce the decision path. H2-1. System Role & Safety Boundary What this module actually “does” Interlocking & vital logic exists to make a single hard […]
- [ATP/ATO/ATS Interfaces: Deterministic, Safe, and Secure Links](https://icnavigator.com/applications/rail-transit-locomotive/atp-ato-ats-interfaces/): ATP/ATO/ATS Interfaces: Deterministic, Safe, and Secure Links ← Back to: Rail Transit & Locomotive ATP/ATO/ATS interfaces are only “safe and deterministic” when they can be measured (latency/jitter), trusted (time-quality + identity), and proven (evidence packets that survive faults and audits). This page shows how to define the telegram model, harden the physical links, synchronize time, and build an end-to-end evidence chain that makes failures reproducible and fixable. Scope & Boundary: What “Interfaces” Means Here This page focuses on interface engineering between ATP, ATO, and ATS: how messages move across domains, how time is shared, and how integrity and identity are […]
- [Axle Counter / Track Circuit Receiver: AFE, BIST, EMC & Timing](https://icnavigator.com/applications/rail-transit-locomotive/axle-counter-track-circuit-receiver/): Axle Counter / Track Circuit Receiver: AFE, BIST, EMC & Timing ← Back to: Rail Transit & Locomotive Core idea: An axle counter / track circuit receiver is a vital “clear/occupied” decision front-end that must stay reliable under harsh railway EMC and changing rail conditions, with false-clear treated as the highest-risk outcome. The winning architecture is the one that pairs interference-hardened sensing and timing with auditable evidence logs, so every decision can be verified, debugged, and defended in the field. H2-1. System Role & Safety Context Axle counters and track circuit receivers sit at a safety boundary where weak sensing […]
- [Train Control & Monitoring System (TCMS)](https://icnavigator.com/applications/rail-transit-locomotive/train-control-monitoring-system-tcms/): Train Control & Monitoring System (TCMS) ← Back to: Rail Transit & Locomotive TCMS is the train’s control-and-evidence backbone: it coordinates vehicle functions through safety compute, isolated I/O, and redundant networks while producing time-aligned logs that make faults explainable and auditable. The core goal is to turn every incident into defensible evidence—so decisions, degraded modes, and field fixes can be verified, replayed, and improved over time. H2-1. TCMS in the Rail Architecture Core takeaway: TCMS is not a “network box”. It is the vehicle-level control-and-evidence hub that makes actions accountable, states trustworthy, and incidents reconstructable. What TCMS must guarantee Command […]
- [CBTC/ETCS Onboard Unit: Safety Compute, Positioning & Security](https://icnavigator.com/applications/rail-transit-locomotive/cbtc-etcs-onboard-unit/): CBTC/ETCS Onboard Unit: Safety Compute, Positioning & Security ← Back to: Rail Transit & Locomotive The CBTC/ETCS Onboard Unit (OBU/EVC) is a safety-critical evidence engine: it turns speed/position, radio sessions, and time into trusted proof, then drives braking/limits deterministically when any evidence becomes unreliable. In practice, stable operation depends on measurable fields (reason codes, counters, latency/timestamps) and a BOM built around safety compute, secure boot/keys, isolation, supervision/holdup, and tamper-evident logging. H2-1. What it is: OBU/EVC role and safety boundary Engineering role: turning movement authority into audited safety actions A CBTC Onboard Unit (OBU) / ETCS European Vital Computer (EVC) is […]
- [Balise / Transponder: RF Demodulation, Diagnostics, Event Timing](https://icnavigator.com/applications/rail-transit-locomotive/balise-transponder-rf-demod-diagnostics-timestamp/): Balise / Transponder: RF Demodulation, Diagnostics, Event Timing ← Back to: Rail Transit & Locomotive A Balise/Transponder link is only “reliable” when it can prove every pass with a consistent RF→decode→timestamp→commit evidence chain—so unreadable, wrong reads, and post-ESD failures are debugged by checking a few key fields (RSSI/AGC/CRC/timebase/commit) and applying the first fix pattern before changing architecture. H2-1. Scope & Interfaces This page locks the scope to the balise/transponder over-the-air read chain: the trackside balise and the onboard BTM (Balise Transmission Module) path that performs coupling, RF front-end processing, demod/decoding, and diagnostic evidence recording. It intentionally avoids broader ETCS/CBTC onboard […]
- [Negative VGOFF & Miller: Prevent False Turn-On in SiC/GaN](https://icnavigator.com/technology/gate-driver-ics/negative-vgoff-miller/): Negative VGOFF & Miller: Prevent False Turn-On in SiC/GaN ← Back to: Gate Driver ICs Negative VGOFF is a controllable “off-margin” knob: hold the gate at −2…−5 V so Miller dv/dt injection cannot lift VGS into the threshold window. The right answer is budget + evidence—choose the minimum −V that keeps VGS_peak below threshold and VGS_min inside abs-max under worst dv/dt, sequencing, and measurement conditions. H2-1 · What Negative VGOFF Solves (Scope & Non-Goals) Negative VGOFF pulls VGS below 0 V during turn-off (typically −2…−5 V) to increase turn-off margin against dv/dt + Miller induced gate bumps and reduce false […]
- [Bootstrap Capacitor Sizing (Cboot) for Gate Drivers](https://icnavigator.com/technology/gate-driver-ics/bootstrap-capacitor-sizing/): Bootstrap Capacitor Sizing (Cboot) for Gate Drivers ← Back to: Gate Driver ICs Core idea: Bootstrap sizing is a charge-budget problem: ensure the refresh window can replenish all required charge (Qg + driver currents + leakage) so VBS never droops below UVLO(off) with margin. If refresh is missing (near-100% duty) or dv/dt/recovery/layout injects spikes, bootstrap becomes structurally unsafe and the design must branch to a charge-pump or isolated-bias solution. What Bootstrap Sizing Solves (Definition & Scope) Bootstrap sizing ensures the high-side driver remains powered by a charge reservoir that is refreshed when the switch node is low. The objective is […]
- [Gate Loop & Parasitics: Kelvin Source & Ringing Control](https://icnavigator.com/technology/gate-driver-ics/gate-loop-parasitics/): Gate Loop & Parasitics: Kelvin Source & Ringing Control ← Back to: Gate Driver ICs Core Thesis Gate-loop stability is primarily a geometry and return-reference problem: minimize loop area, enforce a true Kelvin source return, then apply damping knobs (split Rg / ferrite) with a measurement setup that does not lie. Success is defined by repeatable overshoot/ringing/false-turn-on metrics that meet acceptance thresholds across temperature and real-system conditions. H2-1 · Definition & Boundary Definition & Boundary Gate loop parasitics are the primary root cause of ringing, overshoot, and false turn-on. This page stays strictly inside one scope: the physical gate-drive loop […]
- [Temp, Package & Creepage Selection for Gate Driver ICs](https://icnavigator.com/technology/gate-driver-ics/temp-package-creepage/): Temp, Package & Creepage Selection for Gate Driver ICs ← Back to: Gate Driver ICs Gate-driver “Temp / Package / Creepage” success comes from one loop: set a real junction-temperature margin, make the package thermal path real on the PCB, and protect effective creepage/clearance with documented evidence. If any one of the three is only a datasheet number, reviews fail, labs reject, and field returns happen. Definition & Scope: Temp / Package / Creepage for Gate Driver ICs Purpose A single, review-proof selection loop Temperature sets lifetime limits, package sets the thermal escape path, and creepage/clearance sets safety acceptance. A […]
- [Train Backbone Ethernet TSN Gateway (ECN/WTB/MVB, PTP)](https://icnavigator.com/applications/rail-transit-locomotive/train-backbone-ethernet-tsn-gateway-ecn-wtb-mvb/): Train Backbone Ethernet TSN Gateway (ECN/WTB/MVB, PTP) ← Back to: Rail Transit & Locomotive Key takeaway A Train Backbone Ethernet/ECN/WTB/MVB Gateway is the determinism-and-trust anchor of the onboard network: it preserves TSN latency guarantees, distributes a verifiable time base (PTP/802.1AS), and bridges legacy buses without letting bursts, faults, or maintenance traffic leak into the control domain. What This Gateway Actually Is (and What Problem It Solves) A train backbone Ethernet/ECN/WTB/MVB gateway is a deterministic communications node that (1) forwards time-critical traffic using TSN, (2) bridges legacy train buses without leaking bursts into the backbone, and (3) distributes a coherent time […]
- [Event Recorder / Black Box for Rail Systems](https://icnavigator.com/applications/rail-transit-locomotive/rail-event-recorder-black-box/): Event Recorder / Black Box for Rail Systems ← Back to: Rail Transit & Locomotive Overview This document provides a detailed guide on the functionality, validation, and verification of the Rail Event Recorder / Black Box, ensuring its data integrity, tamper detection, and compliance with industry standards in real-world railway conditions. H2-1. Role & Evidence Grade: “Recording” vs “Evidentiary Record” An event recorder becomes a black box only when its exports can support accident investigation, dispute resolution, and maintenance root-cause analysis with provable time correctness, tamper-evident integrity, and traceable custody. Storing “some data” is not sufficient; the system must prove […]
- [Rail Driver Desk & HMI Design Guide](https://icnavigator.com/applications/rail-transit-locomotive/rail-driver-desk-hmi/): Rail Driver Desk & HMI Design Guide ← Back to: Rail Transit & Locomotive Driver Desk & HMI is a rail-grade operator interface that must remain readable and controllable under power dips, EMI, temperature extremes, and vibration—while producing aligned, signed evidence packets for fast root-cause and compliance. This guide maps failures to measurable fields and first fixes across input, display, audio, networking/time sync, safety states, logging, and validation. H2-1 · System Scope & Boundary System Scope & Boundary The Driver Desk & HMI page defines the operator-facing I/O endpoint that turns train states into actionable displays and turns human inputs […]
- [Gate Voltage Range (+/−): Setting VON/VGOFF Safely](https://icnavigator.com/technology/gate-driver-ics/gate-voltage-range-plus-minus/): Gate Voltage Range (+/−): Setting VON/VGOFF Safely ← Back to: Gate Driver ICs Core idea Gate Voltage Range (+/−) is not a single datasheet number—it is a verifiable voltage window that must remain valid under load, temperature, and dv/dt stress. Define the target VON/VGOFF with margin to Abs Max, then prove it with correct reference measurements, droop control, clamp defenses, and safe-state behavior. Answer focus: window → verify → pass/fail H2-1 · Definition & Boundary: What “Gate Voltage Range (+/−)” Means Intent Make “gate-voltage range” an executable engineering object: separate capability vs recommendation vs hard limits, then turn them into […]
- [Gate Driver Protection Response Time (DESAT to Safe Deactivation)](https://icnavigator.com/technology/gate-driver-ics/protection-response-time/): Gate Driver Protection Response Time (DESAT to Safe Deactivation) ← Back to: Gate Driver ICs Protection response time is the complete timing chain from fault onset to verified safe state (t_safe), not just a fast /FLT. By budgeting t_detect + t_action and verifying with consistent markers and evidence, targets can be set and accepted with clear pass criteria (t_safe, E_sc_meas, and repeatability). H2-1 · One-sentence Thesis Purpose This page defines protection response time as a measurable timeline from fault onset to safe-off, then turns it into an acceptance-ready budget for DESAT detect, filtering/blanking, soft turn-off, and safe deactivation. The goal […]
- [Suspension & Air Spring Control for Rolling Stock](https://icnavigator.com/applications/rail-transit-locomotive/suspension-air-spring-control/): Suspension & Air Spring Control for Rolling Stock ← Back to: Rail Transit & Locomotive Rail air-spring suspension is a closed-loop system that maintains carbody height and ride comfort by combining pressure/height sensing, valve actuation, and evidence-driven fault handling under harsh EMC and transient conditions. This guide shows what to measure, what to log, and what to fix first—from sensing and valve drivers to isolation, validation, and field aging-model updates. H2-1. System Role & Operating Principle Rolling-stock air suspension maintains carbody height (and, when applicable, left/right level) under passenger load changes and track-induced excitation. The loop uses height sensing as […]
- [HVAC Controller for Rolling Stock](https://icnavigator.com/applications/rail-transit-locomotive/hvac-controller-rolling-stock/): HVAC Controller for Rolling Stock ← Back to: Rail Transit & Locomotive A rolling-stock HVAC controller keeps cabin comfort stable by tightly coordinating the compressor, multiple fans, and temperature/humidity/CO₂ sensing while surviving rail power transients, EMI, and vibration. Its real value is “fixability”: layered protections plus evidence-rich event logs that make field faults reproducible and safely tunable instead of intermittent mysteries. H2-1. What a Rolling-Stock HVAC Controller Really Owns Define the responsibility boundary, measurable outcomes, and the evidence-first mindset that makes rail HVAC systems maintainable. A rolling-stock HVAC controller is the owner of a closed-loop electromechanical system, not a simple […]
- [Door Control Unit: Motor Drive, Pinch Sensing, Redundancy & Logs](https://icnavigator.com/applications/rail-transit-locomotive/door-control-unit/): Door Control Unit: Motor Drive, Pinch Sensing, Redundancy & Logs ← Back to: Rail Transit & Locomotive A rail Door Control Unit is not just a motor controller: it combines torque/pinch decision logic, redundant voting, and tamper-resistant event evidence to stop safely under real-world EMI and power dips. This guide focuses on what to measure, what to log, and what to tune first so field failures can be reproduced, diagnosed, and improved through a controlled threshold update loop. H2-1. System Scope & Boundary This page focuses on the Door Control Unit (DCU) as an electronic control-and-evidence subsystem for rolling stock […]
- [CMTI & dV/dt Immunity for Gate Driver ICs](https://icnavigator.com/technology/gate-driver-ics/cmti-dvdt-immunity-2/): CMTI & dV/dt Immunity for Gate Driver ICs ← Back to: Gate Driver ICs CMTI / dv/dt immunity is not just a “datasheet number”—it is the engineering outcome of where displacement current closes and how the driver behaves during the worst dv/dt interval. This page turns CMTI into a measurable acceptance template (X/Y/N/Z/M) and a 30-minute playbook: control return paths and coupling first, then shape gate edges, and only then swap parts. H2-1. Definition & Scope: What “CMTI / dV/dt Immunity” Means (in Gate Drivers) CMTI is the gate-driver’s ability to stay logically correct during high dV/dt common-mode steps—no false […]
- [Delay, Skew & Jitter in Gate Driver ICs](https://icnavigator.com/technology/gate-driver-ics/delay-skew-jitter/): Delay, Skew & Jitter in Gate Driver ICs ← Back to: Gate Driver ICs Delay, skew, and jitter define the real PWM timing resolution and safety margin: keep relative timing (skew/edge spread) within a quantified window across corners, then use that window to set deadtime, verify current sharing, and select matched-channel drivers with confidence. The practical goal is simple: measure timing with a fixed contract, back-calculate allowable skew/spread from Fsw, phases, and min pulse width, and accept only designs that pass worst-case gates (VDD/Temp/load) with data-based criteria. H2-1 · Definition & Scope Definition & Scope: Delay, Skew, and Jitter (Timing […]
- [Onboard PDU & Protection (eFuse, Surge, Telemetry)](https://icnavigator.com/applications/rail-transit-locomotive/onboard-pdu-protection/): Onboard PDU & Protection (eFuse, Surge, Telemetry) ← Back to: Rail Transit & Locomotive An onboard rail PDU keeps the low-voltage bus stable and safe by combining fast electronic protection (eFuse/high-side switching), contactor/relay control, and surge/lightning energy routing, while continuously logging evidence (V/I/state/retry) so every trip or reset can be diagnosed and fixed quickly in the field. The core goal is not only “pass/fail”, but “self-explainable behavior”: when something goes wrong, the PDU’s telemetry proves whether it was inrush, a true short, backfeed/miswire, clamping-induced brownout, contactor issues, or thermal derating—and what to change first. H2-1. What This PDU Page Covers […]
- [HV Insulation & Ground Monitor for Rail Rolling Stock](https://icnavigator.com/applications/rail-transit-locomotive/hv-insulation-ground-monitor-rail/): HV Insulation & Ground Monitor for Rail Rolling Stock ← Back to: Rail Transit & Locomotive Core idea: A rail HV insulation & ground monitor does not “measure ground current” — it estimates the HV network’s effective insulation to chassis (Riso) and proves every alarm with an evidence chain (state snapshot + quality flags + stable recheck), so early warnings and trip decisions stay accurate even under dv/dt switching and surge/EMC stress. Its value is not a single pass/fail result, but reliable trend detection, false-alarm suppression, and forensic-grade logging that turns field returns into safer thresholds and better models across […]
- [Onboard Battery & Charger for Rail Transit](https://icnavigator.com/applications/rail-transit-locomotive/onboard-battery-charger-rail-bms/): Onboard Battery & Charger for Rail Transit ← Back to: Rail Transit & Locomotive Onboard Battery & Charger in rail vehicles is not just “a battery with a charger”—it is the last line of low-voltage stability and safety for critical loads. A rail-grade design must combine isolated measurements, a clear protection state machine, and black-box evidence logging so every abnormal event is explainable, auditable, and continuously improved through field feedback. 24/48/72/110 Vdc low-voltage domains Holdup & brownout survival Insulation / leakage monitoring EN 50155 / EN 50121 / EN 61373 touchpoints H2-1. System Scope & Rail Context Boundary What this […]
- [UVLO Thresholds for Gate Driver ICs (ON/OFF Margins)](https://icnavigator.com/technology/gate-driver-ics/uvlo-thresholds/): UVLO Thresholds for Gate Driver ICs (ON/OFF Margins) ← Back to: Gate Driver ICs UVLO thresholds are not just “undervoltage protection”—they define whether the gate is driven hard enough to stay out of the under-drive danger zone. A correct UVLO_ON/UVLO_OFF window, plus ripple/droop margin and deterministic recovery, prevents half-conduction loss, chatter, and reset storms. ◎ Intent: turn “UVLO” into an engineering threshold for gate effectiveness What UVLO Thresholds Really Mean (and Why “Half-Conduction” Happens) UVLO thresholds are not a generic “low supply” warning. In a gate driver, UVLO defines whether the switch is driven inside a fully-enhanced, low-loss region or […]
- [Peak Source/Sink Current for Gate Drivers: How to Size](https://icnavigator.com/technology/gate-driver-ics/peak-source-sink-current/): Peak Source/Sink Current for Gate Drivers: How to Size ← Back to: Gate Driver ICs Core Idea Peak source/sink current is not a marketing number—it is a practical ceiling that must be translated from Qg and target tr/tf, then verified by waveforms under real Rout/Rg, loop parasitics, and supply droop. The right choice is the smallest peak drive that meets X/Y/Z/N acceptance while keeping ringing, EMI, and gate stress within limits. Definition & Scope (Lock the Boundary) Peak source/sink current is an output-stage capability limit—use it as an engineering input to compute, validate, and select, not as a guaranteed gate-current […]
- [POL/VR/Modular Power Gate Drivers: Multiphase + PMBus](https://icnavigator.com/technology/gate-driver-ics/pol-vr-modular-power/): POL/VR/Modular Power Gate Drivers: Multiphase + PMBus ← Back to: Gate Driver ICs Core Idea POL/VR/Modular Power is a coordinated closed-loop system—not just a gate driver. This page defines how multiphase, remote sense, telemetry/PMBus, and fault orchestration work together to meet transient, accuracy, and operability targets with repeatable acceptance criteria. Definition & Scope Intent Shift the mindset from “gate push” to a VR system coordination loop, and lock the page boundaries. In POL/VR/modular power, the driver is not evaluated only by peak current or edge speed. The real success criteria come from coordination: multiphase energy delivery, remote-sense truth definition, telemetry […]
- [PV/ESS Inverters & DC-DC Gate Drivers: Isolation + iso-ΣΔ Sync](https://icnavigator.com/technology/gate-driver-ics/pv-ess-inverters-dc-dc/): PV/ESS Inverters & DC-DC Gate Drivers: Isolation + iso-ΣΔ Sync ← Back to: Gate Driver ICs Core idea: In PV/ESS power stages, measurement stability and protection reliability depend on treating the gate-drive stack as a system: isolation boundary + clean fault paths + deterministic timing. The practical win is to align switching events and iso-ΣΔ sampling into verified quiet windows, then lock down skew, CMTI, soft turn-off, and recovery policy with measurable pass criteria. Definition & Scope: PV/ESS Inverters & DC-DC Gate-Drive Stack What this page solves A PV/ESS gate-drive stack is treated as a closed engineering chain: command, energy […]
- [Sanding & Anti-Slip Control for Rail Rolling Stock](https://icnavigator.com/applications/rail-transit-locomotive/sanding-anti-slip-control/): Sanding & Anti-Slip Control for Rail Rolling Stock ← Back to: Rail Transit & Locomotive This article covers the design, testing, and maintenance strategies for sanding and anti-slip systems in rail transit. It addresses key topics such as sensor integration, actuator control, slip detection logic, and evidence-based diagnostics. Through detailed analysis and actionable guidelines, the content equips engineers with the knowledge to ensure reliable system performance, minimize false alarms, and maintain long-term operational integrity. H2-1. Scope & Boundary: What this page covers and does not This page focuses on Sanding & Anti-Slip as an onboard adhesion-assist function: detect slip/slide, command […]
- [Brake Control Unit (EBD/EP) for Rolling Stock](https://icnavigator.com/applications/rail-transit-locomotive/brake-control-unit-ebd-ep-for-rolling-stock/): Brake Control Unit (EBD/EP) for Rolling Stock ← Back to: Rail Transit & Locomotive A Brake Control Unit (EBD/EP) is only “safe” when its pressure and wheel-speed signals remain trustworthy under rail harness transients, and every valve/pump action can be proven by evidence fields (resets, drift, CRC, actuation counters) rather than guesses. This page shows how to design the sensing, drive, redundancy voting, EMC hardening, and black-box logging so faults trigger deterministic fail-safe behavior and every field issue can be reproduced and fixed with a bench→rig→train validation plan. H2-1. Role, Boundaries, and What This Page Covers A Brake Control Unit […]
- [Traction Motor & Axle Speed Sensing](https://icnavigator.com/applications/rail-transit-locomotive/traction-motor-axle-speed-sensing/): Traction Motor & Axle Speed Sensing ← Back to: Rail Transit & Locomotive Rail traction does not rely on “a speed number” but on trustworthy time evidence that stays valid under high dv/dt, long cables, and large common-mode noise. This page explains how resolver/encoder and Hall/MR axle chains are built, cross-checked, time-stamped, and maintained so speed remains reliable for traction, braking stability, and protection decisions over a long service life. Why Speed Truth Matters in Rail Traction Speed/position is a safety-critical evidence signal shared by traction, braking, and protection logic. In rail traction, the “speed” signal is not merely a […]
- [Automotive Traction Inverter Gate Driver ICs (ASIL-Ready)](https://icnavigator.com/technology/gate-driver-ics/automotive-traction-inverter/): Automotive Traction Inverter Gate Driver ICs (ASIL-Ready) ← Back to: Gate Driver ICs Central idea In an automotive traction inverter, a gate driver must guarantee a deterministic safe-OFF state through supply transients and high dv/dt, using independent redundant shut-down paths and measurable reaction-time budgets. This page turns ASIL intent into proof-ready design and test criteria for UVLO, fault propagation, controlled turn-off, and validation evidence. H2-1 · Definition & Scope: Traction Inverter Gate-Driver View Define the driver-centric boundary: what this page must solve, what it must not expand into, and what “pass” means in review and validation. Intent Establish a strict […]
- [PFC + HB/FB/LLC Gate Driver Guide (Main Bridge + SR)](https://icnavigator.com/technology/gate-driver-ics/pfc-hb-fb-llc/): PFC + HB/FB/LLC Gate Driver Guide (Main Bridge + SR) ← Back to: Gate Driver ICs This page turns PFC + HB/FB/LLC gate-driving into a measurable engineering playbook: lock ZVS/ZCS timing windows, bias stability, SR windows, and fault paths first—then tune EMI knobs without sacrificing efficiency. The goal is a repeatable pass/fail outcome across line/load/temperature and production variation, using explicit timing, protection, and validation criteria (X/Y/N placeholders). H2-01 · Definition & Scope What this page is about This page focuses on main-bridge gate drivers (HB/FB driving the LLC or hard-switched bridge) and synchronous-rectifier (SR) drivers in a PFC + HB/FB/LLC […]
- [3-Phase Motor / Servo Gate Driver ICs](https://icnavigator.com/technology/gate-driver-ics/3-phase-motor-servo/): 3-Phase Motor / Servo Gate Driver ICs ← Back to: Gate Driver ICs A 3-phase motor/servo gate-drive stack is only “correct” when timing, sensing, and protection behave as one system: PWM update + driver skew + sampling windows stay aligned, and OC/OT/UVLO faults propagate deterministically without flapping. This page turns that requirement into executable wiring templates, validation gates, and acceptance criteria for stable torque, low EMI, and production repeatability. Overview: 3-Phase Motor/Servo Gate-Drive Stack Definition A 3-phase motor/servo gate-drive stack is a closed loop from control to power and back: FOC/servo control → PWM timing → isolation/interface → HS/LS gate […]
- [Gate Voltage & Drive Current: Rails, Peak Drive, and Sizing](https://icnavigator.com/technology/gate-driver-ics/gate-voltage-drive-current/): Gate Voltage & Drive Current: Rails, Peak Drive, and Sizing ← Back to: Gate Driver ICs Gate Voltage & Drive Current is about turning Qg and switching frequency into a gate-rail window and a peak source/sink class that achieves the target edge time without violating Vgs stress limits. The right choice is the smallest drive that still passes the waveform acceptance envelope (Vgs_peak/min, ringing, settling, thermal margin) across all corners—rails first, current second, verification last. Definition & Scope This page defines gate-voltage rails (Vg+ / Vg−) and drive strength (peak source/sink current), then provides a sizing path from Qg and […]
- [CMTI / dv/dt Immunity for Gate Driver ICs](https://icnavigator.com/technology/gate-driver-ics/cmti-dvdt-immunity/): CMTI / dv/dt Immunity for Gate Driver ICs ← Back to: Gate Driver ICs This page turns CMTI / dv/dt immunity from a datasheet number into an auditable engineering flow: identify the dominant coupling path (Input / Isolation / Gate / Return), then apply the minimum fixes and pass/fail criteria. Outcome: a repeatable acceptance template for dv/dt_env (+/−), stable outputs, bounded gate bump/glitch, and consistent results across labs and real inverter cabinets. Scope & Decision Map Fast triage: confirm whether a dv/dt-driven CMTI issue is present, then follow the shortest path to the real victim node. Section intent This section […]
- [Gate Driver Propagation Delay & Matching (Skew/Jitter)](https://icnavigator.com/technology/gate-driver-ics/propagation-delay-matching/): Gate Driver Propagation Delay & Matching (Skew/Jitter) ← Back to: Gate Driver ICs Propagation delay, skew, and jitter must be defined by fixed reference points and measurement contracts, then managed as a budget across the entire timing path. When matching is held within a few nanoseconds across PVT, phase alignment and deadtime margin remain predictable for 3-phase bridges and multiphase VR. H2-01 · Definition & Scope: Propagation Delay, Skew, Matching Intent: Freeze terminology and measurement reference points to prevent mixed definitions later (datasheet vs bench vs system). Timing vocabulary lock Deterministic vs Random split Scope Guard (no overlap) Definitions (what […]
- [Auxiliary Converter (HVAC/Lighting/Charger) for Rail](https://icnavigator.com/applications/rail-transit-locomotive/rail-auxiliary-converter-hvac-lighting-charger/): Auxiliary Converter (HVAC/Lighting/Charger) for Rail ← Back to: Rail Transit & Locomotive Core idea: A rail auxiliary converter is not “just a power supply”—it is an isolated, multi-rail energy-conditioning system that must survive harsh transients and EMC paths while enforcing a clear fault/derating/restart policy. Its real value is operability: PMBus telemetry plus timestamped fault snapshots turn every disturbance (HVAC starts, lighting flicker, charger backfeed, EFT/surge) into measurable evidence that can be reproduced from bench to train and fixed with the smallest actionable change. H2-1. What it is and why rail auxiliary power is different A rail auxiliary converter is not […]
- [Pantograph & DC-Link Control for Rail Traction Power](https://icnavigator.com/applications/rail-transit-locomotive/pantograph-dc-link-control/): Pantograph & DC-Link Control for Rail Traction Power ← Back to: Rail Transit & Locomotive Center of the Topic Purpose: This topic covers the operational dynamics, validation process, and troubleshooting for Pantograph and DC-Link control systems in rail transit. It emphasizes evidence-driven updates, model validation, and safety governance, ensuring reliable performance through structured feedback loops and clear troubleshooting steps. H2-1. Scope & System Boundary Define the pantograph + DC-link front-end control as a self-contained subsystem: actuation + sensing + insulation/arc supervision + event evidence. Design intent: This page focuses on safe HV connection and provable safe exit. The deliverable is […]
- [Traction Inverter: Gate Drivers, Isolated Sensing & Protection](https://icnavigator.com/applications/rail-transit-locomotive/traction-inverter/): Traction Inverter: Gate Drivers, Isolated Sensing & Protection ← Back to: Rail Transit & Locomotive Core Idea A traction inverter is a tightly coupled system of power devices, gate drivers, isolated sensing, thermal paths, and protection logic operating under extreme dv/dt and current stress. Its reliability depends on measurable evidence, disciplined protection strategy, and a repeatable validation workflow that turns failures into controlled engineering updates. H2-1. System Boundary & What “Traction Inverter” Includes Lock the boundary first, so every later decision stays inside measurable, diagnosable inverter hardware scope. A traction inverter is the power-stage boundary that takes energy from the […]
- [Synchronous Rectifier Driver ICs: Flyback & LLC Secondary](https://icnavigator.com/technology/gate-driver-ics/synchronous-rectifier-driver/): Synchronous Rectifier Driver ICs: Flyback & LLC Secondary ← Back to: Gate Driver ICs Core Idea A synchronous rectifier (SR) driver replaces secondary diodes with MOSFETs to cut conduction loss, but the real win only happens when turn-on/turn-off criteria, bias/UVLO refresh, and sensing integrity prevent false turn-on and reverse conduction. This page turns SR design into an executable workflow: waveform windows → decision criteria → bias/boot design → protection/timing/layout → verification gates and acceptance metrics. Definition & Scope Guard Definition (engineering): A secondary-side synchronous rectifier (SR) driver/controller detects a valid conduction window on the secondary rectification path and drives SR […]
- [Differential / Single-Ended Inputs for Gate Drivers](https://icnavigator.com/technology/gate-driver-ics/differential-vs-single-ended-inputs/): Differential / Single-Ended Inputs for Gate Drivers ← Back to: Gate Driver ICs Differential vs single-ended gate-driver inputs is not a “preference”—it’s a measurable noise-margin decision. Choose by noise type, interconnect distance, and isolator output/default state, then validate at the driver pins with margin + PWeff + false-toggle = 0 criteria. Definition & Scope: Differential vs Single-Ended Inputs (for Gate Drivers) Core idea Differential and single-ended inputs define how a gate driver interprets PWM/EN/SD control signals under high dv/dt and strong EMI. The success criteria are simple and measurable: no false turn-on/off, no missing pulses, and pass/fail validation that is […]
- [EMC/ESD/Surge Protection for Instruments](https://icnavigator.com/technology/gate-driver-ics/emc-esd-surge-for-instruments/): EMC/ESD/Surge Protection for Instruments ← Back to: Industrial Sensing & Process Control Core idea: EMC/ESD/Surge robustness in instruments is not achieved by “adding more TVS,” but by routing transient energy into the right reference (chassis) through a low-inductance path, using the right device stack across ns/µs/ms time scales, and then proving it with IEC-aligned tests plus auditable fault records. Outcome: When the return path, zoning, and protection coordination are correct, disturbances become recoverable, measurable events—not random resets, dropouts, or hidden drift. H2-1 · Scope Guard · Boundary & Non-Overlap Rules Scope Guard Intent: This page focuses on instrument interface robustness […]
- [Bypass & Redundant Channel for LED Driver Systems](https://icnavigator.com/technology/gate-driver-ics/bypass-redundant-channel-led-driver/): Bypass & Redundant Channel for LED Driver Systems ← Back to: Industrial Sensing & Process Control Bypass and redundant channel design in LED drivers is not about adding extra hardware—it is about making every transfer evidence-driven, state-controlled, and auditable. A reliable system proves why it switched, how it switched, and that the mechanism still works, through measurable signals, structured voting logic, and verifiable event logs. What “Bypass / Redundant Channel” Means in LED Driver Systems A bypass design removes a failed element from the series energy path so the luminaire can keep operating in a controlled, traceable way. A redundant […]
- [Calibrator / Loop Calibration Station](https://icnavigator.com/technology/gate-driver-ics/calibrator-loop-calibration-station/): Calibrator / Loop Calibration Station ← Back to: Industrial Sensing & Process Control A calibrator / loop calibration station is a traceable measurement system that delivers precision stimulus and verified readback in one closed loop, so calibration results remain consistent across temperature, switching paths, and time. It turns “calibration” into auditable evidence—versioned coefficients, controlled uncertainty, and repeatable verification. H2-1. Center Idea A calibrator / loop calibration station is a traceable metrology loop that generates precision voltage/current stimuli and measures return responses under controlled conditions, so results are reproducible across time, stations, and operators. It closes the loop across reference stability, […]
- [Two-Level Turn-On/Off Gate Drive](https://icnavigator.com/technology/gate-driver-ics/two-level-turn-on-off/): Two-Level Turn-On/Off Gate Drive ← Back to: Gate Driver ICs Core Idea Two-level turn-on/off splits a single switching edge into a fast segment to clear the highest-risk interval, then a gentle segment to cap dv/dt, reduce ringing/EMI, and protect reliability—while keeping efficiency loss within a defined budget. Two-Level Fast “kick” + gentle “finish” shapes switching edges to reduce ringing/EMI while keeping loss and stress within measurable limits. H2-1. Definition & Scope: What “Two-Level” Means Goal: Lock a strict, testable definition of “two-level” gate driving and prevent terminology drift. Covers: What qualifies as two-level, common realizations, where it is most applicable. […]
- [Fault Reporting & Disable: /FLT, /RDY, Safe Fault Paths Across Isolation](https://icnavigator.com/technology/gate-driver-ics/fault-reporting-disable/): Fault Reporting & Disable: /FLT, /RDY, Safe Fault Paths Across Isolation ← Back to: Gate Driver ICs Fault Reporting & Disable is the safety contract of a gate driver: faults must propagate across isolation in a predictable, default-to-off way, and disable must force a verifiable safe state. A robust design proves this end-to-end with measurable timing, correct polarity, fail-safe defaults, and repeatable inject–observe–clear criteria. Define /FLT, /RDY, and EN/nDIS as a measurable safety contract: local gate-off first, then fail-safe reporting across isolation, then hardware-backed inhibit. /FLT (fault) /RDY (ready/PG) EN / nDIS (disable) Fail-safe across isolation Definition & Scope: What […]
- [Cabinet Environment & Security Monitoring](https://icnavigator.com/applications/industrial-sensing-process-control/cabinet-environment-security-monitoring/): Cabinet Environment & Security Monitoring ← Back to: Industrial Sensing & Process Control Cabinet Environment & Security monitoring is built around an evidence-first chain: robust sensing → event rules → local alarms → power-loss-safe logs → trusted uplink. The goal is to prevent false alarms and missed events while keeping every incident auditable (time/sequence/integrity) under real cabinet noise, tamper, and outages. What This Page Covers (and What It Doesn’t) Why this page exists A cabinet monitor succeeds only when it can answer four field questions with evidence: What happened, when it happened, how long it lasted, and whether the record […]
- [Signal Isolator & Conditioner for Lighting Drivers](https://icnavigator.com/applications/industrial-sensing-process-control/signal-isolator-conditioner/): Signal Isolator & Conditioner for Lighting Drivers ← Back to: Industrial Sensing & Process Control Signal isolators and conditioners create a safe, noise-resilient boundary between the high-voltage LED power domain and low-voltage control/measurement electronics, so current/voltage feedback stays accurate and predictable under fast switching and EMI stress. They combine the right isolation technology (digital isolators, isolation amplifiers, or ΣΔ modulators) with scaling, filtering, calibration, and isolated biasing to deliver ADC-ready signals without false triggers, drift, or ripple injection. H2-1. Why Isolation & Conditioning Matter in Lighting Systems In lighting drivers, isolation and signal conditioning define two non-negotiable boundaries: safety separation […]
- [Process Data Logger / Gateway (Integrity-Grade Logging)](https://icnavigator.com/applications/industrial-sensing-process-control/process-data-logger-gateway/): Process Data Logger / Gateway (Integrity-Grade Logging) ← Back to: Industrial Sensing & Process Control A process data logger is not just a recorder—it is an evidence system that keeps records in order, keeps time consistent, survives power loss without silent corruption, and makes tampering detectable with verifiable signatures. A “trustworthy” logger is judged by its proof: monotonic timelines, safe commit markers, recoverable storage, and audit-ready integrity fields—not by how many protocols it can read. H2-1. Center Idea — What Makes a Logger “Trustworthy” This chapter does not describe features. It sets the acceptance bar for what an industrial logger […]
- [Deadtime & Shoot-Through Interlock in Gate Driver ICs](https://icnavigator.com/technology/gate-driver-ics/deadtime-shoot-through-interlock/): Deadtime & Shoot-Through Interlock in Gate Driver ICs ← Back to: Gate Driver ICs Deadtime and hardware interlock exist to guarantee break-before-make at the gate outputs, preventing shoot-through even when PWM timing is imperfect. The engineering goal is to define one measurable deadtime metric, compute a minimum safe value with margins, then tune within an optimum window that meets spike, loss, EMI, and fault-response criteria (X/Y/N). Definition: Deadtime & Shoot-Through Interlock This section locks a single engineering vocabulary for deadtime, shoot-through, and hardware interlock—so timing budgets and pass/fail criteria remain consistent across design, bring-up, and audit. Deadtime: the enforced break-before-make […]
- [Split/Programmable Gate Resistors for Gate Driver ICs](https://icnavigator.com/technology/gate-driver-ics/split-programmable-gate-resistors/): Split/Programmable Gate Resistors for Gate Driver ICs ← Back to: Gate Driver ICs Split/programmable gate resistors turn gate-edge shaping into a controllable, repeatable knob—so EMI, switching loss, and device stress can be balanced with measurable acceptance criteria. The core method is simple: adjust Rg_on / Rg_off and/or drive/slew levels, validate with VDS overshoot, VGS ringing, dv/dt proxy, and ΔT, then lock the configuration for production consistency. H2-1. Definition & Why It Matters Split and programmable gate resistors turn “edge speed” into a controllable, repeatable knob—used to balance EMI, switching loss, and device stress without changing the power stage topology. What […]
- [DESAT Short-Circuit Detection (Blanking, Filter, Soft Turn-Off)](https://icnavigator.com/technology/gate-driver-ics/desat-short-circuit-detection/): DESAT Short-Circuit Detection (Blanking, Filter, Soft Turn-Off) ← Back to: Gate Driver ICs Core Takeaway DESAT short-circuit detection protects power switches by monitoring abnormal VCE/VDS rise during conduction and triggering a controlled shutdown. The winning design is the one that trips fast on real shorts while staying immune to dv/dt noise via correct threshold budgeting, blanking/filter tuning, and a safe fault-handling policy. H2-01. Definition & Scope of DESAT Short-Circuit Detection Boundary + Map Intent: Define DESAT in one minute: it detects an abnormal rise of VCE/VDS during conduction (loss of saturation / hard fault), then initiates a controlled turn-off and […]
- [Active Miller Clamp for Gate Drivers](https://icnavigator.com/technology/gate-driver-ics/active-miller-clamp/): Active Miller Clamp for Gate Drivers ← Back to: Gate Driver ICs Active Miller Clamp exists to prevent dv/dt-induced false turn-on during turn-off—by providing a low-impedance gate-to-source sink path for Miller current. It should be selected and verified quantitatively: clamp strength/threshold/timing must keep Vgs_peak_off below a defined margin under worst-case dv/dt and temperature corners. Protection & Control • Active Miller Clamp Definition & When You Need It Active Miller clamp is a dedicated, low-impedance gate-to-source clamping path that is enabled during turn-off. Its job is not “turn-off faster”; its job is to prevent dv/dt-induced false turn-on by providing a strong […]
- [Batch / Recipe Controller for Sequencing, Metering & Audit Logs](https://icnavigator.com/applications/industrial-sensing-process-control/batch-recipe-controller/): Batch / Recipe Controller for Sequencing, Metering & Audit Logs ← Back to: Industrial Sensing & Process Control Core idea: A Batch/Recipe Controller turns a recipe into a deterministic, auditable execution—sequencing I/O and metering with a reliable timebase, then storing evidence-grade batch records that survive power/network faults across Ethernet/fieldbus integration. Outcome: It makes every run repeatable and explainable: the same inputs yield the same steps, and any deviation can be traced to specific timestamps, mappings, measurements, and approved recipe versions. H2-1. What This Controller Does and Where It Fits A Batch / Recipe Controller is the execution core that turns […]
- [Edge PID / Loop Controller (Precision ADC/DAC, Safety & HMI)](https://icnavigator.com/applications/industrial-sensing-process-control/edge-pid-loop-controller/): Edge PID / Loop Controller (Precision ADC/DAC, Safety & HMI) ← Back to: Industrial Sensing & Process Control Edge PID / Loop Controller is a deterministic “last-mile” control core that closes real-world loops locally by budgeting latency and jitter end-to-end, while keeping measurement/output paths precise and fail-safe under noise, brownouts, and software faults. It focuses on evidence-driven design: measurable timing/ADC/output/PID states and a safe-state supervision policy so tuning and field debugging stay predictable and low-cost. H2-1 · What This Page Covers (and What It Doesn’t) What This Page Covers (and What It Doesn’t) An Edge PID / Loop Controller is […]
- [Industrial Time & TSN: 1588 HW Timestamps and Jitter-Cleaned Clocks](https://icnavigator.com/applications/industrial-sensing-process-control/industrial-time-tsn/): Industrial Time & TSN: 1588 HW Timestamps and Jitter-Cleaned Clocks ← Back to: Industrial Sensing & Process Control H2-1. Center Idea — Deterministic Time Is a Hardware Problem What “deterministic time” means in industrial TSN In an industrial TSN network, determinism is not proven by claiming protocol support. It is proven when time error stays inside a declared budget while traffic is scheduled and faults occur (reference loss, failover, congestion). The deciding factors are physical: where timestamps are taken, how clean and stable the clock tree is, and how redundancy behaves during switchover. The three engineering axes (each must be […]
- [Gate Driver ICs with Current & Temperature Sensing](https://icnavigator.com/technology/gate-driver-ics/driver-current-temp-sensing/): Gate Driver ICs with Current & Temperature Sensing ← Back to: Gate Driver ICs A current/temperature-sensing gate driver turns protection into a measurable loop: it captures current and thermal evidence fast enough to trigger safe turn-off or foldback, while exporting telemetry that controllers can trust for diagnostics and derating decisions. The goal is not “more data,” but valid data in the right window—with defined latency, accuracy, and pass/fail criteria under high dv/dt conditions. H2-01. Positioning & Scope: What “Current/Temp Sensing Driver” Really Means A Current/Temp Sensing Gate Driver is a gate driver that turns current and temperature into actionable telemetry […]
- [UVLO (On/Off Thresholds) for Gate Driver ICs](https://icnavigator.com/technology/gate-driver-ics/uvlo-on-off-thresholds/): UVLO (On/Off Thresholds) for Gate Driver ICs ← Back to: Gate Driver ICs Core Thesis Independent UVLO ON/OFF thresholds (VON/VOFF) turn gate-drive power dips into a deterministic “permission boundary”—preventing half-conduction loss and restart chatter. The goal is simple: disable early, recover cleanly, with behavior that is measurable and defensible in reviews and lab tests. Definition & Scope: UVLO with Independent ON/OFF Thresholds UVLO (Under-Voltage Lockout) is a driver-side protection function that disables gate-drive output when the driver bias rail falls below a defined threshold, preventing insufficient gate drive from causing half-conduction, uncontrolled switching, or thermal runaway. Core requirement: Independent turn-on […]
- [Digital Isolator + Gate Driver Combo for Tight Skew](https://icnavigator.com/technology/gate-driver-ics/digital-isolator-gate-driver-combo/): Digital Isolator + Gate Driver Combo for Tight Skew ← Back to: Gate Driver ICs A Digital Isolator + Gate Driver Combo reduces interface and routing uncertainty so multi-phase/multi-bridge systems can close timing (ΔtPD/skew/jitter) more deterministically under high dv/dt. It helps by tightening the signal path from isolated input to gate output—then the remaining work is to budget, measure, and verify power-noise coupling, CMTI false-trigger immunity, and protection partitioning with clear pass criteria (X/Y/N). H2-01 · Definition & Scope Boundary A Digital Isolator + Gate Driver Combo integrates the digital isolation path and the high-current gate-drive output stage into one […]
- [Driver ICs with Integrated Isolated Bias](https://icnavigator.com/technology/gate-driver-ics/driver-with-integrated-isolated-bias/): Driver ICs with Integrated Isolated Bias ← Back to: Gate Driver ICs Driver with Integrated Isolated Bias integrates an isolated secondary bias supply (+VG/−VG) inside the gate driver, so high-side power, UVLO/OTP/fault actions, and timing become one deterministic loop with less BOM and fewer wiring risks. The key is verifying bias integrity under dv/dt, noise, and thermal limits using measurable pass/fail criteria (X/Y/N), not just no-load rail readings. What It Is: Driver with Integrated Isolated Bias Scope Locked One-line definition: A gate driver IC that integrates an isolated power stage and delivers secondary-side gate-bias rails (+VG and optional −VG) while […]
- [RTU / Station Controller: Ethernet, Isolated I/O, PTP & Secure Boot](https://icnavigator.com/applications/industrial-sensing-process-control/rtu-station-controller/): RTU / Station Controller: Ethernet, Isolated I/O, PTP & Secure Boot ← Back to: Industrial Sensing & Process Control An RTU (remote terminal unit) / station controller is an evidence-grade SCADA edge node: it aggregates isolated I/O, terminates industrial Ethernet/serial, timestamps SOE with PTP, and enforces secure boot with protected keys (TPM/HSM) to keep telemetry, commands, and updates defensible. H2-1. Page Mission & “What must be proven” Design intent: define an RTU as an evidence box, not a feature box. Every subsystem must answer “what happened, when, who requested it, and whether the running code/configuration was authorized.” Process evidence Point […]
- [WirelessHART / ISA100 Gateway Design Guide](https://icnavigator.com/applications/industrial-sensing-process-control/wirelesshart-isa100-gateway/): WirelessHART / ISA100 Gateway Design Guide ← Back to: Industrial Sensing & Process Control A WirelessHART / ISA100 gateway is reliable only when RF + time-sync + redundancy + backhaul + power isolation are designed as one evidence-driven system: every fault must be attributable by telemetry, not guesswork. This guide provides a deployable reference architecture and the exact measurements and first fixes that prevent “works in lab, fails on site.” H2-1. What This Gateway Solves A WirelessHART / ISA100.11a gateway is not a “simple bridge.” It is an OT-critical node that must preserve deterministic behavior across RF, compute, backhaul, and […]
- [HART & Fieldbus (FF/PA/Profibus PA) Modem AFE Guide](https://icnavigator.com/applications/industrial-sensing-process-control/hart-fieldbus-ff-pa-modem-afe-coupling-diagnostics/): HART & Fieldbus (FF/PA/Profibus PA) Modem AFE Guide ← Back to: Industrial Sensing & Process Control This guide shows how HART and bus-powered fieldbuses (FF H1 / Profibus PA) overlay communication on a two-wire power loop, focusing on modem AFE design, coupling/isolation networks, and a measurable diagnostics evidence chain for fast troubleshooting and certification readiness. H2-1. Center Idea This page explains how HART and MBP-class fieldbuses (FOUNDATION Fieldbus H1 / Profibus PA) superimpose communication onto a two-wire, bus-powered loop, covering bus coupling & isolation, modem AFEs, protocol controller roles, and a measurable diagnostics evidence chain. The goal is not protocol […]
- [Low-Voltage MOSFET Driver ICs for Buck & BLDC](https://icnavigator.com/technology/gate-driver-ics/low-voltage-mosfet-driver/): Low-Voltage MOSFET Driver ICs for Buck & BLDC ← Back to: Gate Driver ICs Introduction to Low-Voltage MOSFET Drivers What a Low-Voltage MOSFET Driver Is A low-voltage MOSFET gate driver is the interface that converts logic PWM commands into controlled gate-current pulses that rapidly charge and discharge a MOSFET gate. Gate drive: 5–12V Peak source/sink: 2–10A Focus: Buck + BLDC Key point: the driver does not “provide power” to the load—it provides fast, repeatable gate control so the power stage can switch efficiently and safely. Where It Sits in the Power Stage The driver forms the control boundary between a […]
- [Isolated Gate Driver ICs for SiC/GaN Inverters](https://icnavigator.com/technology/gate-driver-ics/isolated-gate-driver/): Isolated Gate Driver ICs for SiC/GaN Inverters ← Back to: Gate Driver ICs Isolated gate drivers make high-dv/dt SiC/GaN power stages controllable and safe by enforcing reinforced isolation, high CMTI, and deterministic HS/LS drive + fault behavior. The core goal is repeatable switching and predictable protection across corners—so efficiency, EMI, and reliability can be proven, not guessed. H2-1 · Definition & Overview An isolated gate driver transfers PWM/control and fault information across a galvanic isolation barrier, then delivers controlled gate charge/discharge to floating high-side and low-side power switches (SiC/GaN/IGBT/MOSFET) under fast dv/dt and large common-mode voltage swings. Scope (What this […]
- [Digital Output (High-Side / Relay)](https://icnavigator.com/applications/industrial-sensing-process-control/digital-output-high-side-relay/): Digital Output (High-Side / Relay) ← Back to: Industrial Sensing & Process Control Core idea: A digital output is not just an on/off pin—it is an output stage you can trust, because it can protect itself (SC/OT/UV/OV), prove what happened (diagnostics/telemetry), and fail predictably across wiring, inrush, and isolation boundaries. H2-1 · Scope & Non-Scope What This Page Covers (Scope & Non-Scope) Digital outputs are not “a pin that toggles.” They are power-path actuators that must remain controllable under real faults (shorts, opens, overheating) and must provide evidence of what happened. This page defines the boundary: the output stage, its […]
- [TC/RTD Multi-Channel Card (CJC Arrays, 24-Bit ADCs)](https://icnavigator.com/applications/industrial-sensing-process-control/tc-rtd-multi-channel-card/): TC/RTD Multi-Channel Card (CJC Arrays, 24-Bit ADCs) ← Back to: Industrial Sensing & Process Control Precision Temperature Acquisition Front-End Core idea: A TC/RTD multi-channel card becomes “precision-grade” only when switching/settling, leakage/guarding, and CJC placement are treated as first-class subsystems with measurable evidence fields. With calibrated coefficients and production-ready diagnostics (crosstalk + insulation + audit logs), each channel remains traceable, debuggable, and stable across humidity, wiring changes, and scan-rate updates. CJC arrays multi-channel scan guarding & leakage 24-bit ΔΣ ADC channel-to-channel delta H2-1. What This Card Is For (And What “Good” Looks Like) A TC/RTD multi-channel card is a metrology-constrained temperature […]
- [IO-Link Master / Device: PHY, Protection, Isolation & ID](https://icnavigator.com/applications/industrial-sensing-process-control/io-link-master-device/): IO-Link Master / Device: PHY, Protection, Isolation & ID ← Back to: Industrial Sensing & Process Control IO-Link Master/Device reliability is decided at the port: protect L+ and C/Q against miswire, ESD/EFT/surge, and hot-plug while preserving COM1/2/3 timing margin, then make power-fail and diagnostics deterministic with clear brownout rules and safe ID/parameter storage. A robust design treats each port as a mini “power + comms subsystem” that can always explain failures via reason codes/counters and can be validated with a repeatable lab matrix. H2-1. Page Mission & Scope Guard This page is a port-level, evidence-driven hardware guide for building robust […]
- [Digital Input Design for Dry Contact & Proximity Sensors](https://icnavigator.com/applications/industrial-sensing-process-control/digital-input-dry-contact-proximity/): Digital Input Design for Dry Contact & Proximity Sensors ← Back to: Industrial Sensing & Process Control This section provides answers to common issues related to digital inputs, covering topics such as false triggers, contact chatter, sensor behavior inconsistencies, and diagnostic reliability. Each FAQ offers a quick conclusion, backed by evidence from waveform analysis, diagnostics logs, and suggested first fixes to help resolve the issue efficiently. H2-1. What This Page Solves A digital input becomes valuable only when it is trustworthy under real wiring conditions: long cables, shared conduits, ground potential differences, leakage currents, and burst-like interference. This page defines […]
- [Analog Output (4–20mA and ±10V) Interfaces](https://icnavigator.com/applications/industrial-sensing-process-control/analog-output-4-20ma-10v/): Analog Output (4–20mA and ±10V) Interfaces ← Back to: Industrial Sensing & Process Control Center Idea Analog outputs (4–20mA and ±10V) are the most reliable industrial interfaces for long cables and noisy environments. This page explains how to design a precision DAC with loop/voltage driver stages, wire-break/short detection, isolation, and surge/ESD protection, ensuring accuracy, stability, and EMC control. H2-1 Center Idea: Why 4–20mA and ±10V Still Win in Industrial Control Analog outputs remain trusted in harsh industrial environments because they are measurable (current/voltage can be verified at the terminals), calibratable (offset/gain and drift can be corrected and audited), and fault-detectable […]
- [Analog Input (4–20mA/HART/±10V) Front-End Design](https://icnavigator.com/applications/industrial-sensing-process-control/analog-input-4-20ma-hart-10v/): Analog Input (4–20mA/HART/±10V) Front-End Design ← Back to: Industrial Sensing & Process Control This page provides a comprehensive guide to designing accurate industrial analog input channels for 4–20mA, HART, and ±10V signals using PGA + ΣΔ ADCs, while ensuring precision, protection, and diagnostic capabilities. Learn about key topics such as burden voltage, isolation, calibration, and noise management to optimize performance and reliability in your designs. H2-1. Center Idea Industrial analog input channels must stay accurate under long cables, ground offsets, and fast transients. This subpage defines a repeatable, verification-first channel architecture that supports 4–20mA loops, preserves DC accuracy while extracting […]
- [SiC MOSFET Driver: CMTI, Miller Clamp & <2 µs SC](https://icnavigator.com/technology/gate-driver-ics/sic-mosfet-driver/): SiC MOSFET Driver: CMTI, Miller Clamp &
- [GaN HEMT Gate Driver ICs: 0–6 V Control & Fast Edges](https://icnavigator.com/technology/gate-driver-ics/gan-hemt-gate-driver/): GaN HEMT Gate Driver ICs: 0–6 V Control & Fast Edges ← Back to: Gate Driver ICs A GaN HEMT driver must convert PWM into tightly controlled gate-charge current while staying immune to dv/dt noise, so the switch never false-turns-on or shoot-throughs. This page focuses on measurable knobs and acceptance criteria—gate loop/CSI, edge control, timing/ interlock, rail quality, protection, and CMTI—so the design can be validated and reproduced from lab bring-up to production. H2-1. Definition & Scope: What a “GaN HEMT Driver” Must Guarantee Intent: Freeze the contract for this page—what it guarantees, what it does not cover, and which […]
- [SIS Logic Solver: Voting, Lockstep Safety MCU, Isolated I/O](https://icnavigator.com/applications/industrial-sensing-process-control/sis-logic-solver/): SIS Logic Solver: Voting, Lockstep Safety MCU, Isolated I/O ← Back to: Industrial Sensing & Process Control A SIS Logic Solver is the decision core of a safety loop: it validates input health, applies deterministic 1oo2/2oo3 voting, and drives a defined safe-state sequence. Its credibility comes from isolation-aware signal integrity plus traceable evidence (snapshots, timestamps, cause codes) that makes every trip predictable, reproducible, and auditable. H2-1. Role of the SIS Logic Solver in the Safety Loop Extractable definition (for SEO / AI) A SIS Logic Solver is the decision core of a Safety Instrumented Function (SIF): it validates safety-related inputs, […]
- [Emergency Shutdown & Interlock (Fast Latch + Isolation)](https://icnavigator.com/applications/industrial-sensing-process-control/emergency-shutdown-interlock/): Emergency Shutdown & Interlock (Fast Latch + Isolation) ← Back to: Industrial Sensing & Process Control Emergency Shutdown & Interlock ensures a deterministic, fail-safe stop: when a hazard occurs, the system must cut or derate energy within a defined time budget and latch into a known safe state. It also must leave recoverable, auditable evidence (reason codes, timing proof, and black-box records) so the event can be verified and fixed without guesswork. Emergency Shutdown & Interlock ensures a deterministic, fail-safe stop: when a hazard occurs, the system must cut or derate energy within a defined time budget and latch into […]
- [Functional Safety & Compliance for LED Drivers](https://icnavigator.com/applications/industrial-sensing-process-control/functional-safety-compliance/): Functional Safety & Compliance for LED Drivers ← Back to: Industrial Sensing & Process Control Center Idea: Functional safety and compliance are won by building a deterministic evidence chain—from hazard and safety functions to verified reaction timing, tamper-evident logs, and key/signature governance—so every trip, test, and field action is traceable and non-repudiable. Outcome: The system can prove what happened, why it happened, and that the device entered (and can recover from) a defined safe state under ESD/surge/EMC and real-world service conditions. H2-1. Center Idea Functional safety & compliance for LED drivers should be treated as an evidence system: deterministic safety […]
- [IGBT Gate Driver ICs: -VGOFF, DESAT, Soft/Two-Level Turn-Off](https://icnavigator.com/technology/gate-driver-ics/igbt-gate-driver-ics/): IGBT Gate Driver ICs: -VGOFF, DESAT, Soft/Two-Level Turn-Off ← Back to: Gate Driver ICs This page turns IGBT gate driving for traction/industrial into a verifiable playbook: −VGOFF, DESAT short-circuit detection, and soft/two-level turn-off are treated as measurable knobs with acceptance criteria. The goal is repeatable review/bring-up/production outcomes—prevent false turn-on, react fast to shorts, and control overshoot/EMI using timing budgets and layout-ready rules. A switch-technology deep dive: negative gate bias, DESAT short-circuit detection, and soft/two-level turn-off for traction and industrial power stages. H2-1. Definition & Boundary: What “IGBT Gate Driver” Means Here Scope Lock Intent: Define a strict boundary for this […]
- [Gate-Transformer Driver (GDT): Push-Pull Primary, Sync Secondary](https://icnavigator.com/technology/gate-driver-ics/gate-transformer-driver/): Gate-Transformer Driver (GDT): Push-Pull Primary, Sync Secondary ← Back to: Gate Driver ICs Gate-Transformer Driver is a high-isolation gate-drive approach that delivers strong, fast switching pulses through a transformer, and it wins when dv/dt is harsh and common-mode coupling must be minimized. The core success condition is guaranteed volt-second balance and reset plus matched secondary networks, so Vgs amplitude, droop, skew, and dv/dt immunity remain within acceptance limits. H2-1. Gate-Transformer Driver — Definition & When It Wins A gate-transformer driver (GDT) transfers gate-drive energy across an isolation barrier using magnetic coupling. It excels in high dv/dt and pulsed environments, but […]
- [Multiphase Gate Driver for VR: Interleaving & Share Signals](https://icnavigator.com/technology/gate-driver-ics/multiphase-gate-driver-for-vr/): Multiphase Gate Driver for VR: Interleaving & Share Signals ← Back to: Gate Driver ICs Core Idea Multiphase VR gate driving is about making every phase switch the same way: interleaving, timing match, current-sense scaling, and fault policy must be consistent so ripple cancels, heat spreads, and protection is deterministic. This page turns those knobs into measurable gates (X/Y/N pass criteria) to prevent imbalance, noise, and “works-on-bench” failures in real CPU/GPU VR systems. H2-1. Definition & Scope for Multiphase VR Gate Drivers This chapter locks the page boundary: multiphase VR gate driver content covers phase coordination, share semantics, timing consistency, […]
- [Half-Bridge / Full-Bridge Gate Driver Timing & Interlock Guide](https://icnavigator.com/technology/gate-driver-ics/half-bridge-full-bridge-driver/): Half-Bridge / Full-Bridge Gate Driver Timing & Interlock Guide ← Back to: Gate Driver ICs Core Idea Half-/full-bridge gate drivers succeed or fail on one thing: guaranteeing positive effective deadtime under worst-case delay/skew/jitter while ensuring deterministic interlock and fast, consistent fault shutdown. This page provides a measurable timing budget, verification playbook, and sign-off criteria to prevent shoot-through without sacrificing efficiency. H2-1. Scope, Definitions, and Where HB/FB Drivers Fit Intent Make the page boundary unambiguous This page focuses on timing integrity in half-bridge / full-bridge drivers—preventing cross-conduction by hardware interlock, programmable deadtime, and matched delay, with testable acceptance criteria. HB vs […]
- [I/P Converter & Pneumatic Manifold Design Guide](https://icnavigator.com/applications/industrial-sensing-process-control/ip-converter-pneumatic-manifold/): I/P Converter & Pneumatic Manifold Design Guide ← Back to: Industrial Sensing & Process Control Core idea: An I/P Converter & Pneumatic Manifold turns a loop-current or digital command into stable, controllable pressure/flow, then distributes it across ports with measurable evidence. What “good” looks like: fast, stable closed-loop response and deterministic fail-safe behavior—proven by logged fields (drive effort, pressure response, port ΔP, comm errors, and recovery time) rather than guesses. H2-1. What This Module Is (Definition & System Boundary) Core function: Convert an electrical command (4–20 mA or a digital setpoint) into a controlled pneumatic output (pressure/flow) and distribute it […]
- [Electric Actuator Controller: BLDC/Stepper, Feedback, Protection](https://icnavigator.com/applications/industrial-sensing-process-control/electric-actuator-controller/): Electric Actuator Controller: BLDC/Stepper, Feedback, Protection ← Back to: Industrial Sensing & Process Control Center Idea + What This Page Solves This chapter defines the reliability bar: stable motion control is achieved only when the power stage, feedback I/O, sensing/protection, and isolated comms are engineered as a single evidence-driven system. An electric actuator controller fails in predictable ways when the design treats motion, sensing, and communications as separate “features”. The reality is a coupled system: the power stage injects switching noise; the feedback chain must remain trustworthy; the thermal state changes electrical parameters; and the supply can dip or overshoot […]
- [Smart Valve Positioner: Position AFE, Drives, I/P & Diagnostics](https://icnavigator.com/applications/industrial-sensing-process-control/smart-valve-positioner-electronics/): Smart Valve Positioner: Position AFE, Drives, I/P & Diagnostics ← Back to: Industrial Sensing & Process Control Key idea: A smart valve positioner is a proof-driven closed-loop system that turns commands into precise valve travel by combining position sensing AFEs, drive electronics, and the I/P pneumatic boundary. The most reliable designs prioritize stability, power margin, and evidence logs so accuracy holds across temperature, load, and field noise—not just on the bench. H2-1. Page Mission A smart valve positioner is a closed-loop electromechanical device that turns control commands into precise valve travel using position sensing, drive electronics, and an I/P (current-to-pressure) […]
- [High-Side Gate Driver (Bootstrap & Charge Pump) Guide](https://icnavigator.com/technology/gate-driver-ics/high-side-gate-driver-bootstrap-charge-pump/): High-Side Gate Driver (Bootstrap & Charge Pump) Guide ← Back to: Gate Driver ICs Core Idea A high-side gate driver must keep a floating gate-bias (VBS) stable while enforcing interlock/deadtime and resisting dv/dt-induced false turn-on. The right choice (bootstrap vs charge pump) is the one that passes measurable bring-up gates: VBS_min ≥ X V, tDT_eff ≥ Y ns, skew ≤ N ns, and zero false pulses under worst-case switching. H2-1. Definition & Use Cases of High-Side Gate Drivers Intent Define what a high-side gate driver truly controls and provide clear “must-use” triggers for common power stages. In scope Floating reference […]
- [Low-Side Gate Driver ICs: Selection, Timing, and Design Hooks](https://icnavigator.com/technology/gate-driver-ics/low-side-gate-driver/): Low-Side Gate Driver ICs: Selection, Timing, and Design Hooks ← Back to: Gate Driver ICs Core Idea A low-side gate driver wins when strong, clean turn-on/turn-off is needed with minimal complexity—by controlling the gate loop, Rg(on/off), UVLO, and timing as one measurable system. This page turns those knobs into calculable sizing and pass/fail criteria so edges stay fast without overshoot, EMI, brownout chatter, or production drift. Scope: Low-side gate drivers only (ground-referenced). High-side bootstrap/charge-pump and isolation barriers are intentionally out of scope for this page. H2-1. Definition & Where Low-Side Drivers Win Intent Establish a single, unambiguous definition for low-side […]
- [Medical HMI Isolation: Isolated USB + IEC 60601-1 Power](https://icnavigator.com/technology/digital-isolators-isolated-power/medical-hmi-isolated-usb-iec-60601-1/): Medical HMI Isolation: Isolated USB + IEC 60601-1 Power ← Back to: Digital Isolators & Isolated Power Medical HMI isolation succeeds only when leakage-current targets are translated into wiring, shield-bond ownership, and a testable budget—then USB isolation and power choices are validated without “Y-cap first” shortcuts. This page provides decision-ready topologies, measurable pass criteria (X/Y/N), and a verification plan so EMC/ESD improvements never break 60601-1 leakage compliance. H2-1 · Scope & Decision Tree Scope & Decision Tree (Medical HMI Isolation) This chapter locks the page boundary and turns medical isolation requirements into a 3-minute decision flow: Data-only vs Data+VBUS vs […]
- [Ex Power & Intrinsic-Safety Barriers](https://icnavigator.com/applications/industrial-sensing-process-control/ex-power-intrinsic-safety-barriers/): Ex Power & Intrinsic-Safety Barriers ← Back to: Industrial Sensing & Process Control H2-1 · Center Idea Center Idea Ex power is not “higher power delivery”; it is power that remains energy-limited under any single fault. A barrier, isolated supply, energy-limit monitor, and fault-bypass path together form an energy guardrail with diagnosable failure paths. Practical meaning: compliance depends on controlling not only steady-state V/I/P, but also stored and transient energy that can appear during open/short events, startup/retry cycles, and surge interactions. Steady-state energy: open-circuit voltage, short-circuit current, output power limits. Stored energy: capacitors/inductors (including cable-equivalent C/L) that can release energy […]
- [24V Process Power Front-End (Flyback/LLC, Surge, eFuse)](https://icnavigator.com/applications/industrial-sensing-process-control/24v-process-power-front-end/): 24V Process Power Front-End (Flyback/LLC, Surge, eFuse) ← Back to: Industrial Sensing & Process Control H2-1. What “24V process power front-end” actually means (scope & boundary) Definition (extractable): A 24V process power front-end is the system-level input stage that converts an industrial 24V bus into a controlled, protected, and diagnosable intermediate supply—surviving surges, hot-plug events, and brownouts while providing reliable power-good timing. This page focuses on the front-end boundary: from the field terminal (24V bus) to a stable intermediate rail after protection, hot-swap/eFuse control, and isolation conversion (Flyback or LLC). The goal is not “power conversion at any cost,” but […]
- [Intrinsic Safety Sensor Node (Ex i) Architecture & Certification Hooks](https://icnavigator.com/applications/industrial-sensing-process-control/intrinsic-safety-sensor-node-ex-i/): Intrinsic Safety Sensor Node (Ex i) Architecture & Certification Hooks ← Back to: Industrial Sensing & Process Control This page turns “build an Ex i sensor node” into an engineering checklist: how to constrain available energy, how to demonstrate safety under faults, and how to design self-test + evidence hooks that reduce certification friction. H2-1. Page Mission & What Ex i Really Means for a Sensor Node Intrinsic safety (Ex i) is best treated as an energy envelope that must remain valid during credible faults and be supported by verifiable evidence. A sensor node is not made “Ex i” by […]
- [High-Precision Sampling Across Isolation](https://icnavigator.com/technology/digital-isolators-isolated-power/high-precision-sampling/): High-Precision Sampling Across Isolation ← Back to: Digital Isolators & Isolated Power Precision sampling across an isolation barrier is not “adding one isolator”—it is a closed loop of clock jitter, AFE linearity, isolated power noise, partition/return paths, and measurable validation gates. The winning recipe controls coupling paths (Cbar/Y-cap/shield), budgets jitter+ripple+spurs end-to-end, and proves it with repeatable pass criteria. Scope System Recipe No Cross-Topic Spillover Definition & Scope Boundary High-precision sampling across an isolation barrier is a system problem: accuracy is preserved only when clock jitter, barrier coupling, isolated power noise, and front-end drive errors are budgeted and validated together. What […]
- [BMS/HV Systems: Isolated CAN-FD + isoSPI Daisy Chain](https://icnavigator.com/technology/digital-isolators-isolated-power/bms-hv-isolated-can-fd-isospi/): BMS/HV Systems: Isolated CAN-FD + isoSPI Daisy Chain ← Back to: Digital Isolators & Isolated Power Core Thesis In BMS/HV systems, isolation must be treated as a complete, testable system—partitioning (CAN-FD vs isoSPI), reinforced insulation targets, and isolated power must be co-designed to survive HV dv/dt and to pass production gates with repeatable X/Y/N acceptance criteria. H2-01 · What This Page Solves (Scope & Decision Map) PurposeDefine the system problem and lock the decision inputs This page turns BMS/HV isolation into a measurable system decision: isolation for communication, isolated power, safety/compliance targets, EMC immunity, and production-ready validation. Scope boundary: focuses […]
- [Fault & Black-Box: Event Logging, Latch & Clear](https://icnavigator.com/technology/digital-isolators-isolated-power/fault-black-box-logging/): Fault & Black-Box: Event Logging, Latch & Clear ← Back to: Digital Isolators & Isolated Power A fault black-box in an isolated system standardizes what gets recorded, when it latches, who can clear it, and how recovery is verified—so field disputes become auditable evidence instead of guesswork. With survivable storage and cross-domain time correlation, every UV/OT/SC event is captured with minimum context and pass/fail gates (X/Y/N), enabling consistent diagnose → decide → recover workflows. H2-01 · What is “Fault & Black-Box” in an Isolated System Black-box logging in isolation is not generic logging—it is an audit-ready evidence chain for fault […]
- [Motor / Inverter Isolation Stack: Driver + ΔΣ + Bias](https://icnavigator.com/technology/digital-isolators-isolated-power/motor-inverter-isolation-stack/): Motor / Inverter Isolation Stack: Driver + ΔΣ + Bias ← Back to: Digital Isolators & Isolated Power In motor/inverter systems, isolation only “works” when the gate driver, ΔΣ sensing chain, and isolated bias are co-designed as one deterministic stack under worst-case dv/dt and fault energy. The goal is simple: truthful sensing + predictable protection timing + repeatable production evidence—so field behavior matches lab results. System Context & Boundary (Motor / Inverter Isolation Stack) Context — why this stack is hard Motor inverters combine extreme dv/dt at the switching node with high fault energy; the isolation stack must keep sensing […]


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