Pre-bias startup — compensation caveats?

Prevent discharging the pre-biased output: inhibit synchronous pull-down, bias the EA to track the pre-bias level, and use a gentle soft-start slope. Ensure the current-limit and valley/peak sense offsets won’t force reverse current or false hiccup during the hand-off to regulation.

Loop Compensation & Stability for Buck/Boost

Q: Why must Boost/Buck-Boost keep fc below the RHPZ?

The right-half-plane zero raises gain while adding negative phase, so pushing bandwidth near it erodes phase margin rapidly. Keep fc ≤ fRHPZ/5 as a practical ceiling. Improve transient with feed-forward and load-line shaping instead of forcing more bandwidth into the unstable region.

Q: When is slope compensation mandatory in peak CMC? How is valley CMC different?

Peak current-mode control suffers subharmonic oscillation when duty exceeds roughly 0.5. Add external ramp slope ma comparable to the inductor down-slope to stabilize. Valley CMC samples at the valley, relaxing the condition, but still needs adequate noise margin and proper inner-loop gain at high duty.

Q: Type-II vs Type-III — how do I choose?

Use Type-III in Buck for higher bandwidth and LC double-pole cancellation (Z1≈fo, Z2≈fz,ESR). Start with Type-II for Boost/BB where the RHPZ caps bandwidth; add phase with zeros but keep conservative high-frequency roll-off. Switch up only if margins and noise allow.

Q: How do phase margin targets trade off overshoot and response time?

PM ~55–65° usually balances speed and damping. Lower PM yields faster rise but larger overshoot and ringing; higher PM damps better but slows recovery. If speed is still insufficient, prefer load-line or feed-forward enhancements instead of pushing fc toward plant limits.

Q: PFM at light load prevents open-loop measurement — what can I do?

Force PWM/CCM during Bode testing or use a load to pull the converter out of PFM. If unsupported, inject around the error amplifier and document mode boundaries. Avoid interpreting PFM traces as loop gain; they represent burst logic, not linear small-signal behavior.

Q: Curves look distorted — how to debug a wrong injection point?

Verify TP_INJ and TP_ERR locations, maintain 50-Ω source/termination, and minimize ground loop area. Compare a baseline through-trace versus injected trace to spot loading. If the EA saturates or noise rises sharply, move the probe upstream and reduce injection level.

Q: Does spread-spectrum modulation affect closed-loop measurements?

Yes. Dithering smears the switching harmonic content, blurring gain/phase curves and masking peaking. Disable spread spectrum for loop characterization, then re-enable for EMI validation. If you must keep it on, average longer and accept reduced resolution near fc.

Q: How does ESR drift (temperature/aging) impact compensation?

ESR changes shift the ESR zero and effective damping. With MLCCs, ESR often drops cold, lifting the zero and reducing phase help; electrolytics age upward. Place compensator zeros with margin, validate across temperature, and consider derating fc slightly for worst-case corners.

Q: Multiphase system beats/whines — what’s the mitigation order?

Adjust the phase matrix for better interleaving, then retune fc or fsw to avoid mixing products, finally enable spread spectrum. Check current sharing loop stability and sense routing symmetry before changing compensation topology.

Q: Is deliberate output droop (AVP) acceptable?

Yes, if documented and within system tolerance. AVP trades controlled sag during transients for smaller output capacitors and faster recovery. Specify droop slope, clamp limits, and regulation bands, and verify load-line linearity across temperature and current sharing conditions.

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Peak/Valley current-mode control, slope compensation, feed-forward & load-line (AVP/D-LAV), and practical Bode hooks for stable power stages.

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Introduction & Search Intent Mapping

This page targets engineers who need to set crossover frequency, phase/gain margin, and prepare Bode hooks while accounting for peak/valley CMC behavior, slope compensation, and feed-forward/load-line options. It applies to Buck / Boost / Buck-Boost / SEPIC / Zeta in CCM, with notes for light-load PFM.

One-line answer

Loop compensation shapes the error-amplifier response so the power stage crosses at f_c with ~60° phase margin and >6 dB gain margin; mitigate subharmonic risk in peak-CMC at high duty via slope compensation and keep f_c well below the boost/BB RHPZ.

Quick rules

f_c ≈ f_sw/10 … f_sw/5 PM 55–70° GM > 6 dB Peak-CMC @ high-D → slope comp Boost/BB: f_c ≪ f_RHPZ Use ESR zero to add phase

Key formulas

f_RHPZ(boost) ≈ (R_load · (1−D)²) / (2πL) → ensure f_c ≪ f_RHPZ

f_z,ESR = 1 / (2π · ESR · C_out) → place zeros to lift phase

Peak-CMC subharmonic risk ~ D > 0.5 → add external ramp m_a

Prepare Bode hooks and target crossover with safe phase/gain margins.

Control Modes Overview

Peak CMC vs Valley CMC

Peak CMC: sample at the peak; high-duty subharmonic risk (≈ D>0.5). Add external ramp m_a; sensitive to ripple/noise but excellent transient control.

Valley CMC: sample at the valley; less sensitive to high-duty subharmonics. Watch low ripple / small R_sense noise. Choose per topology and bandwidth targets.

Voltage-mode vs Current-mode vs Digital

Voltage-mode: simple but sensitive to L/C shifts; often needs Type-III for higher bandwidth.

Current-mode (peak/valley): quasi 1st-order plant eases compensation; tie bandwidth/limits directly to inductor current. Peak CMC at high D requires slope compensation.

Digital (discrete PI/Type-III): flexible; account for sampling/compute delay (phase lag). Discretization (ZOH/Tustin) moves effective zeros/poles—verify on hardware.

When slope compensation is mandatory

Required for peak CMC at high duty (Buck at high D; Boost/BB with unfavorable inner slope). Start with a fraction of the inductor down-slope; ensure stability first, then restore bandwidth.

For Boost / Buck-Boost, RHPZ limits bandwidth—keep f_c well below f_RHPZ before fine-tuning the ramp.

Power Stage Poles/Zeros by Topology

Map the dominant poles/zeros per topology and set a safe upper bound for f_c. For light-load PFM/burst, force PWM/CCM during Bode measurement; otherwise the curve is not representative.

Buck — Main Resonance & ESR Zero

f_o ≈ 1 / (2π√(LC)) (double pole). Output-cap ESR creates f_z,ESR = 1 / (2π·ESR·C_out) which can add phase. Ultra-low ESR MLCC shifts f_z,ESR higher; Type-III is often preferred for higher bandwidth.

Start f_c ≈ f_sw/10 … /5 Type-III often needed Watch MLCC ESR shift

Boost / 4-Switch Buck-Boost — RHPZ Limit

Plant includes a right-half-plane zero: f_RHPZ ≈ (R_load·(1−D)²)/(2πL). It raises gain while dropping phase; keep bandwidth well below it.

Hard rule: f_c ≤ f_RHPZ/5 Use AVP/VFF for transient Slope comp for peak-CMC (high D)

SEPIC / Zeta — Coupled Inductors & ESR Double Zeros

Series/coupled inductors and the series capacitor add extra poles; MLCC ESR may create a pair of zeros. Use conservative bandwidth first, then add zeros to recover phase; note coupling factor k shifts pole locations.

Default f_c ≤ f_sw/10 Place zeros vs dominant poles Mind coupling factor k

Relative locations only (not to scale). Use as a placement guide for bandwidth and zero alignment.

PFM/Burst note: lock PWM/CCM when extracting loop gain; record mode boundaries (current-limit valley/peak, burst thresholds) separately.

Compensation Types & Design Recipes

Choose a compensator and place zeros/poles to meet PM ≥ 55–65°, GM > 6–10 dB, and f_c ≤ f_sw/5. With very low ripple or small R_sense, slightly reduce f_c to avoid noise amplification.

Type-I / Type-II / Type-III — Quick Guide

Type-I: low bandwidth, DC accuracy. Type-II: one/two zeros + one HF pole (good start for Boost/BB/SEPIC). Type-III: two zeros + two HF poles (common for high-BW Buck).

Z1 ≈ dominant pole (LC/load) Z2 ≈ ESR zero (phase lift) P1,P2 ≥ 3–5× f_c (roll-off)

Buck (High-BW) — Type-III Recipe

Set f_c → Z1 ≈ f_o → Z2 ≈ f_z,ESR → P1 ≈ 3–5× f_c → P2 near f_sw/2 for roll-off. Verify Bode margins and step response.

Boost / Buck-Boost — Type-II Start

Constrain f_c ≤ f_RHPZ/5 → place Z1 near the lowest dominant pole → optional Z2 to add phase → add HF pole(s) for noise roll-off. Improve transient via AVP/D-LAV or VFF, not by pushing bandwidth.

Digital Compensation (PI/Type-III)

Account for sampling & compute delay (phase lag). ZOH/Tustin discretization shifts zeros/poles. Keep f_c well below Nyquist/10 and validate with hardware Bode.

Place zeros against dominant poles (and ESR zero) to recover phase; push HF poles above 3–5× f_c to roll off noise.

Targets: PM ≥ 55–65°, GM > 6–10 dB, f_c ≤ f_sw/5. With very low ripple, reduce f_c slightly and ensure probing/fixture are shielded and 50-Ω matched.

Slope Compensation (CMC Essentials)

Understand the sub-harmonic instability mechanism when sampling at peak and how to apply slope compensation (`m_a`) to avoid instability at high duty cycles. It involves matching the inductor current descent slope to `m_a` and selecting the optimal slope ratio.

Instability Mechanism: Subharmonic Oscillations

Subharmonic oscillations can occur when sampling at peak duty, especially at high duty cycles where the feedback response fails to compensate for rapid inductor current changes.

Higher D → subharmonic risk Peak sampling becomes unstable Need for slope compensation (m_a)

Design Guideline: Matching Slope `m_a` with Inductor Current Descent

The external slope `m_a` should be matched to the inductor current descent rate. A suggested range for `m_a` is based on the inductor characteristics and the maximum allowable ripple in current-mode control.

Calculate `m_a` ≈ L / R Typical range for `m_a`: 0.25–0.6

Valley CMC vs. Boost Inner Loop Considerations

In valley CMC, the compensation requirements are more relaxed compared to peak CMC. Boost inner loops require a stricter control of slope compensation to ensure stable performance due to the right-half-plane zero (RHPZ) in the topology.

Implementation: Resistor/Capacitor Values & Internal COMP Pin Networks

Common implementations use resistor-capacitor (RC) networks to generate the required slope compensation, which can be applied directly to the COMP pin of the controller IC. Common design approaches are described with recommended component values for different ICs.

Matching the inductor current descent with external slope to avoid instability in peak CMC operation.

Feed-Forward & Load-Line (AVP / D-LAV)

Explore how feed-forward (VFF) and load-line (AVP/D-LAV) techniques enhance transient response, allowing for controlled output voltage sag and reduced output capacitor size.

Input Feed-Forward (VFF): Topology Adaptation & Zero Crossing Phase Advantage

VFF allows the converter to preemptively adjust based on input voltage, improving transient response by making adjustments before the feedback loop reacts. Zero-crossing phase advantages improve the system’s ability to handle input voltage changes.

Load-Line (AVP): Controlled Output Voltage Sag for Smaller Capacitors

Load-line control allows output voltage to sag momentarily under transient conditions, trading this sag for a reduction in required output capacitance. This technique is widely used to manage larger load steps while reducing size and cost of the power supply.

Implementation Path: Error Amplifier Networks & Current Sensing Coupling

Feed-forward and load-line techniques are implemented by coupling error amplifier networks with current sensing. The error amplifier adjusts the control loop to react quickly to changes in the load, minimizing the need for excessive capacitance.

Tuning and Default Values

Default tuning values should be used initially to prevent overcompensating and causing instability. Gradually adjust parameters based on system response and component characteristics, following the recommended procedure for AVP/D-LAV and VFF adjustments.

Feed-Forward and Load-Line control techniques enhance transient response while managing output voltage sag.

Bode Hooks & Measurement Playbook

Learn about injection point selection, impedance shaping, test setup with transformers/dividers, and grounding/shielding for accurate Bode measurements. Ensure correct test workflow from frequency sweep to margin reading.

Injection Point Selection & Impedance Shaping

Choose the correct injection point (error amplifier output or feedback voltage divider node) to achieve stable Bode responses. Use impedance shaping to ensure minimal reflection and maintain signal integrity during measurements.

Test Setup: Transformers, Voltage Dividers, Grounding & Shielding

Proper injection transformer or voltage divider setup is essential for accurate measurement. Ensure 50 Ω impedance matching and shielded grounding loops to reduce noise interference and provide clear data.

Measurement Workflow: Sweep Range, Open-Loop/Closed-Loop, & f_c Margin

Set a frequency sweep from 10 Hz to half the switching frequency (f_sw). Switch between baseline, open-loop, and closed-loop measurements to determine the bandwidth (`f_c`) and gain margins.

Common Measurement Errors: Light Load PFM, Current Limiting, Soft-Start & Protection

Beware of common measurement errors like light-load PFM instability, current-limiting points, and the effects of soft-start or protection circuits that can distort frequency response measurements.

Illustration of the Bode measurement setup: includes injection points, transformers, and impedance shaping.

Multiphase & Beat-Avoidance

Learn how to design phase matrices for multiphase systems and how to avoid beat frequencies by adjusting phase, `f_c`, and `f_sw`. Understand the trade-offs between shared vs. independent compensation in multiphase designs.

Phase Matrix: 2/3/4/6 Phases

A multiphase system’s performance heavily relies on the phase matrix. Optimizing phase differences for 2, 3, 4, and 6 phases can greatly enhance stability and transient response.

Beat-Avoidance Sequence: Change Phase → Change f_c / f_sw → Enable Spread Spectrum

To avoid beat frequencies, adjust phase first, then tweak `f_c` or `f_sw`, and lastly, enable spread spectrum for optimal performance.

Shared vs Independent Compensation: Current Sharing & Error Amplifier Structure

In multiphase designs, decide between shared or independent compensation. Shared compensation improves current-sharing but may require more complex error amplifier structures.

Phase matrix for multiphase systems and beat-avoidance methods in frequency design.

Special Cases & Edge Conditions

Learn how to handle edge cases such as USB-PD PDO switching, pre-bias startup, temperature tolerance, and noise/EMI management. Discover strategies to ensure system stability in varying conditions.

USB-PD Scenario: f_c and Loop Switching with PDO Transitions

In USB-PD scenarios, the transition between PDOs can cause dramatic changes in loop bandwidth (f_c). Learn how to manage loop switching to avoid instability during PDO transitions.

Pre-bias Startup: Avoid Discharge & Soft-Start Slope/Surge

Pre-bias startup can cause unwanted discharge of capacitors. Learn how to avoid this and design soft-start slopes to minimize inrush current and surges during startup.

Temperature/Tolerance: ESR Drift & Core μ Variations on Pole Location

Temperature variations and ESR drift can cause pole locations to shift, affecting stability and performance. Learn how to mitigate these effects using tolerance and temperature compensation techniques.

Noise/EMI: Spread Spectrum Interaction with Measurement & Compensation

Spread Spectrum is effective in reducing EMI but can interact with measurement techniques and compensation strategies. Learn how to optimize the trade-off between reducing EMI and maintaining measurement accuracy.

Illustration of handling special cases like USB-PD transitions, pre-bias startup, and temperature tolerance in power systems.

Quick Recipes (Copy-Paste Cards)

Use these quick recipes to speed up your design process for different topologies. These copy-paste cards offer practical configurations for Buck, Boost, and BB/4-Switch designs.

Buck-HS/High-Speed: Target f_c ≈ f_sw/8, Type-III, Z1 Align f_o, Z2 Near ESR Zero

For high-speed Buck designs, set f_c ≈ f_sw/8, use **Type-III** compensation, align **Z1** with the main resonance frequency **f_o**, and place **Z2** near the ESR zero.

Boost-RHPZ Limited: f_c ≤ f_RHPZ/5, Type-II, Increase Phase, Conservatively Roll-off Gain

For Boost designs with RHPZ limitations, set f_c ≤ f_RHPZ/5, use **Type-II** compensation, increase phase, and ensure a conservative roll-off of gain to maintain stability.

BB/4-Switch: Partitioned Modeling (Buck-like/Boost-like), Set f_c for Worst-Case Region

In BB/4-Switch designs, partition the model into **Buck-like** and **Boost-like** regions. Set f_c according to the worst-case region to optimize performance across all phases.

Quick recipe for Buck, Boost, and BB/4-Switch designs: guidelines for compensation and crossover frequency settings.

Validation & Sign-off Checklist

Run frequency- and time-domain tests, sweep temperature, and account for prototype tolerances. Capture results in a traceable template and use a “Fail → Fix” path (two-step validation + long-term remedy).

Bode: PM/GM/f_c

Measure loop gain from 10 Hz up to ~½ f_sw. Targets: PM 55–70°, GM > 6–10 dB, f_c ≤ f_sw/5 (Boost/BB: f_c ≪ f_RHPZ).

Lock PWM/CCM (avoid PFM) Document TP_INJ / TP_ERR Note mode boundaries

Step: ±50% Load

Apply ±50% I_load steps with realistic di/dt. Record overshoot/undershoot, settling time (2% band), and any burst/limiting artifacts.

< 5% overshoot (goal) < 1–2 ms settle (typ.)

VIN Transient

Sweeps and brown-out dips: verify regulation and margin near minimum VIN and at max duty. Capture droop recovery and any hiccup entry/exit.

Temperature Sweep & Prototype Tolerance

-40 °C → +85 °C (or app range). Track ESR drift and inductor μ change → pole/zero shifts. Compare 3–5 boards to quantify spread.

Recommended validation flow and documentation cadence.

Record Template & “Fail → Fix” Path

Test	Setup / Notes	Result	Pass/Fail	Action (Quick / Long-term)
Bode	TP_INJ=…; TP_ERR=…; PWM lock	PM=…°, GM=…dB, f_c=…	□P / □F	+Z @ … Hz / redesign EA network
Step	ΔI=±50%; di/dt=…A/µs	OS=…%; Ts=…ms	□P / □F	tune AVP / add HF pole
VIN	ΔVIN=…V; slew=…V/µs	droop=…mV	□P / □F	increase slope m_a / widen duty clamp
Temp	-40→85 °C	shift=…%	□P / □F	derate f_c / ESR cornering

Tip: On mobile, swipe sideways to see all columns.

Two-step validation: (1) Quick tune on bench (zeros/poles/AVP/slope). (2) Long-term fix in BOM/layout/IC settings (ESR class, inductor μ, routing, hooks).

IC Selection Hooks (COMP / ISEN / VFF / AVP)

Common hook naming by major vendors and how to spot them in data sheets. Examples include real part numbers to anchor terminology. Always check the latest datasheet before routing.

Brand	Example MPNs (real)	Typical Hook Names	Where to Find in Datasheet
Texas Instruments	TPS54160, TPS40210, TPS40170	COMP, CS/ISNS, VSENSE, SS/TR, VFF/VIN feed (app-dependent)	“Pin Functions”, “Compensation”, “Current Sense”, “Applications”
Analog Devices (incl. LTC)	LTC3780, LTC3892, LT8610	ITH(COMP), SENSE±, FB, TRACK/SS, OV/UV, optional VFF	“Pin Description”, “Applications Information”, “Typical Applications”
STMicroelectronics	L7985A, L296, ST1S10	COMP, CS, FB, SS, optional VFF/Sync	“Pin settings”, “Compensation Network”, “Application hints”
onsemi	NCP1587, NCP3065, FAN6500X	COMP, CS/ISEN, FB, SS, droop/IMON (model-dependent)	“Pin Description”, “Functional Description”, “Design Procedure”
Infineon (IR)	IRU3037, XDPL8221, TLF50211	COMP/EAOUT, CS/SENSE, FB/VS, SS, optional VFF	“Pin configuration”, “Loop compensation”, “Current sensing”
Renesas (Intersil)	ISL81601, ISL85410, ISL8117	COMP, ISEN/CS, FB, SS/TRK, AVP/DROOP/IMON	“Pin descriptions”, “Compensation design”, “Current sharing / AVP”
Monolithic Power Systems (MPS)	MP1584, MP2499, MPQ4571	COMP, CS/ISEN, FB, SS, load-line via LL/IMON (part-dependent)	“Pin Functions”, “Loop Compensation”, “Application Information”
NXP	MC34704, TEA1995 family, PF5020 (PMIC)	COMP/EAOUT (on controllers), CS, FB, SS, system VFF/AVP (platform)	“Pin description”, “Functional description”, “Design notes”

Tip: On mobile, swipe sideways to see all columns.

How to Locate Hooks Fast

Search the PDF for: COMP, ITH, ISEN/CS, FB/VSENSE, SS/TRACK, IMON/DROOP, VFF. Then jump to “Compensation” and “Applications Information” to extract recommended RC ranges.

Matrix Placeholder (to be extended)

For each MPN, record: Hook Pins, Suggested RC ranges, Sense method (resistor/DCR/csamp), AVP/VFF availability, Notes (RHPZ limits, valley/peak mode, ramp).

Typical hooks to locate in controller/regulator datasheets for loop work.

FAQs

Why must Boost/Buck-Boost keep f_c below the RHPZ?

The right-half-plane zero raises gain while adding negative phase, so pushing bandwidth near it erodes phase margin rapidly. Keep f_c ≤ f_RHPZ/5 as a practical ceiling. Improve transient with feed-forward and load-line shaping instead of forcing bandwidth into the unstable region.

When is slope compensation mandatory in peak CMC? How is valley CMC different?

Peak current-mode control suffers subharmonic oscillation once duty > ~0.5. Add external ramp slope m_a comparable to the inductor down-slope to stabilize. Valley CMC samples at the valley, relaxing the condition, but you still need noise margin and adequate inner-loop gain at high duty.

Type-II vs Type-III — how do I choose?

Use Type-III in Buck to cancel the LC double pole and reach higher bandwidth (Z1≈f_o, Z2≈f_z,ESR). Prefer Type-II for Boost/BB where RHPZ caps bandwidth; add phase with zeros but keep conservative HF roll-off. Upsize only if noise and margins allow.

How do phase-margin targets trade off overshoot and response time?

PM ≈55–65° balances speed and damping. Lower PM yields faster rise but larger overshoot/ringing; higher PM damps better but slows recovery. If speed is insufficient, prefer load-line or feed-forward tweaks instead of pushing f_c toward plant limits.

PFM at light load prevents open-loop measurement — what can I do?

Force PWM/CCM during Bode testing or add load to exit PFM. If unsupported, inject around the error amplifier and document mode boundaries. Don’t interpret PFM traces as loop gain; they represent burst logic, not linear small-signal behavior.

Curves look distorted — how to debug a wrong injection point?

Verify TP_INJ/TP_ERR nodes, maintain 50-Ω source/termination, and minimize ground-loop area. Compare through-trace vs injected to spot loading. If the EA saturates or noise rises, move upstream and reduce injection level.

Does spread-spectrum modulation affect closed-loop measurements?

Yes. Dithering smears switching harmonics, blurring gain/phase and masking peaking. Disable spread spectrum for loop characterization, then re-enable for EMI checks. If you must keep it on, average longer and accept reduced resolution near f_c.

How does ESR drift (temperature/aging) impact compensation?

ESR shifts move the ESR zero and damping. MLCC ESR drops cold, lifting the zero and reducing phase boost; electrolytics age upward. Place compensator zeros with margin, validate across temperature, and slightly derate f_c for worst-case corners.

Multiphase system beats/whines — what’s the mitigation order?

First tune the interleaving phase matrix, then adjust f_c or f_sw to avoid mixing products, finally enable spread spectrum. Check current-sharing loop stability and sense-routing symmetry before changing compensation topology.

Is deliberate output droop (AVP) acceptable?

Yes, if specified and within tolerance. AVP trades controlled sag during transients for smaller output capacitors and quicker recovery. Define droop slope, clamps, and regulation bands; verify linearity across temperature and current-sharing conditions.

How to tame loop jitter during USB-PD PDO changes?

Gate loop gain during transitions: ramp soft-start, limit EA slew, and pre-position duty clamps for the new PDO. If supported, switch compensation/AVP profiles with PDO. Validate using scripted VIN/VOUT steps that emulate negotiated states.

Pre-bias startup — any compensation caveats?

Prevent pre-bias discharge: inhibit synchronous pull-down, bias the EA to track pre-bias, and use gentle soft-start. Ensure current-limit and valley/peak sense offsets don’t force reverse current or false hiccup during hand-off.

Digital loops (discrete PI/Type-III) — how to account for sampling delay?

Model ZOH plus compute delay as extra phase lag. Start with f_c ≤ f_s/10. Tustin mapping moves zeros/poles; re-place after discretization. Validate margins on hardware; timing jitter adds additional phase uncertainty.

When should I reduce f_c instead of adding more phase boost?

Lower bandwidth when the plant limits it (RHPZ, parasitics, noise floor) or when extra boost worsens peaking/EMI. A slightly lower f_c with cleaner phase is more robust across temperature and tolerance spread.

EA output is noisy — how can I improve it?

Reduce high-frequency loop gain, move HF poles down modestly, and add an RC snubber on COMP if allowed. Shorten COMP/FB routing with solid ground. Check probe grounding and 50-Ω practices. Excess sense noise may require larger R_sense or DCR-filter tweaks.

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Loop Compensation & Stability (Buck / Boost / Buck-Boost)