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USB-C/PD Power-Path Protection

← Back to: eFuse / Hot-Swap / OR-ing Protection

Scope: connector-side power-path protection only — low-cap ESD on CC/SBU, VBUS OVP/short/reverse, cable-flip with coordinated clamp + fast disconnect.

Out of scope: PD negotiation (PDO/PPS), downstream NVDC/charge–discharge, DC/DC control loop, system BMS. When mentioned, they appear as a one-line boundary note only. PG=True means pass; FAULT=True means constrained/shutdown.

Problem Scenarios & Usage Boundaries

USB-C ports face near-connector risks: hot-plug inrush, VBUS shorts/over-voltage, cable-flip stress, and ESD on CC/SBU. Without close-in protection, systems show PG chatter, ghost resets, and reverse-current damage. This page addresses coordinated clamp and microsecond-level disconnect to keep FETs inside SOA while preserving high-speed integrity.

  • Why must CC/SBU use ultra-low-cap ESD arrays instead of generic TVS?
  • How fast must VBUS disconnect under shorts/OV — at the μs scale?
  • How does reverse current harm the upstream/parallel source?
  • Why are PG chatter and post-ESD ghost resets so common?
Engineering gates: IEC 61000-4-2, TLP clamp curves, FET SOA, and a ns→μs protection chain (TVS → eFuse).
USB-C/PD port power-path protection stack Low-cap ESD for CC/SBU, TVS + eFuse/Hot-Swap on VBUS, and ideal-diode OR-ing for reverse blocking; PG/FAULT semantics shown. USB-C Receptacle CC/SBU Low-Cap ESD C_line ≤ 0.6 pF TVS + eFuse / Hot-Swap OVP · ILIM · Fast short Ideal-Diode OR-ing Low drop · Reverse block System Load / DC Domain • Coordinated clamp → microsecond fast disconnect • PG/FAULT semantics aligned across brands • A→A / A→B substitution within validated thresholds
USB-C port protection stack: low-cap ESD for CC/SBU, TVS + eFuse/Hot-Swap on VBUS, and ideal-diode OR-ing for reverse blocking.

Operating Principle: Coordinated Clamp & Fast Disconnect

Protection timing: TVS clamps first (ns) to limit VVBUS to VCLAMP, then eFuse fast-trip (μs) disconnects before MOSFET SOA is exceeded. CC/SBU ESD arrays preserve high-speed integrity with low Cline. OR-ing controllers provide low-drop reverse blocking and priority switchover.

  • CC/SBU path: differential/common-mode handling; low-cap arrays balance Cline vs clamp level.
  • VBUS protector: OVP, ILIM (steady/fast-short), dV/dt, latch/hiccup; tdetect ≤ 100–200 ns, toff ≤ 1–5 μs.
  • Ideal-Diode: ΔV@I, Irev threshold, trecover, source priority.
Windowed thresholds (for cross-brand substitution): ESD: IEC 61000-4-2 contact ≥ ±8 kV, air ≥ ±15 kV; CC/SBU Cline ≤ 0.6 pF; VBUS OVP (5 V bin 6.0–6.2 V; 9/15/20 V bins by 1.2×–1.4× or 21/24/28 V families); tdetect ≤ 200 ns; toff ≤ 5 μs; ΔV@I and Irev within recorded limits.
Coordinated clamp timing TVS clamps first, then eFuse fast-trip cuts VBUS within microseconds to keep MOSFET inside SOA. Waveforms: I_ESD, V_VBUS, Gate/FAULT. I_ESD V_VBUS V_CLAMP Gate / FAULT TVS clamp (ns) eFuse fast-trip SOA safe region t_detect ≤ 200 ns t_off ≤ 5 μs V_CLAMP window
Coordinated clamp timing — TVS clamps first, then eFuse fast-trip cuts VBUS within microseconds to keep MOSFET inside SOA.
Windowed thresholds (copy to BOM/test plan):
  • ESD (CC/SBU): IEC 61000-4-2 contact ≥ ±8 kV, air ≥ ±15 kV; Cline ≤ 0.6 pF; specify TLP VCLAMP.
  • VBUS protector: OVP 5 V bin 6.0–6.2 V; higher bins by 1.2×–1.4× or 21/24/28 V families; tdetect ≤ 200 ns; toff ≤ 5 μs.
  • OR-ing: ΔV@I within target; Irev peak and trecover within recorded limits during source switchover.

Key Parameters & Windowed Thresholds (Selection Sheet)

All parameters are expressed as windows to enable A→A / A→B cross-brand substitutions without degradation. Copy rows directly into BOM/test plans; keep PG/FAULT semantics consistent across parts.

Window legend: target ranges (✓ = within window, ! = check drift, × = out of window). Use project-specific clamp value for VCLAMP@I_TLP.

ESD/TVS for CC/SBU

Param Window Project Target Notes
IEC 61000-4-2 (Contact/Air) ≥ ±8 kV / ≥ ±15 kV ±8 / ±15 kV Array-type near receptacle; multi-point strike coverage
Cline (per CC/SBU) ≤ 0.6 pF ≤ 0.6 pF Preserve HS/Alt-mode SI margin
VCLAMP@I_TLP ≤ X V @ ITLP ≤ 12 V @ 8 A (example) Define per project; capture TLP curve
Leakage @ Vbias ≤ 50 nA ≤ 30 nA Room & hot spot-check

VBUS Protector (eFuse / Hot-Swap)

VIN Bin OVP Window ILIM (steady/fast) tdetect / toff dV/dt / Soft-start RDS(on) / Vdrop Irev / TSD PG/FAULT/ALERT & IF
5 V 6.0–6.2 V Iset / 1.5–2.5× ≤ 200 ns / ≤ 5 μs Programmable ramp ≤ X mΩ / ≤ Y mV Limited / Yes PG, FAULT, ALERT / I²C or PMBus
9 / 15 / 20 V 1.2×–1.4× nominal Iset / 1.5–2.5× ≤ 200 ns / ≤ 5 μs Slew controlled ≤ X mΩ / ≤ Y mV Limited / Yes PG, FAULT, ALERT / I²C or PMBus
21 / 24 / 28 V family Family bins Iset / fast short ≤ 200 ns / ≤ 5 μs Soft-start options ≤ X mΩ / ≤ Y mV Irev report / TSD PG/FAULT semantics unified

OR-ing (Ideal-Diode)

Param Window Project Target Notes
ΔV @ Iload ≤ target (per I bin) ≤ 40 mV @ 2 A (example) Thermal check at max load
Irev_peak / trecover ≤ target / ≤ 10–50 μs ≤ 0.3 A / ≤ 20 μs No power drop on switch
Priority logic Deterministic Main→Backup Document switchover rule
BOM remark (one-liner): CC/SBU ESD Cline ≤ 0.6 pF, IEC ≥ ±8/±15 kV, VCLAMP@I_TLP within project window; VBUS eFuse OVP per bin, tdetect ≤ 200 ns, toff ≤ 5 μs; OR-ing ΔV@I and Irev/trecover within targets; PG/FAULT semantics aligned.

Tuning & Validation Matrix (Minimal Executable)

Six scenarios, one flow: Inject → Measure → Log → Verdict. Record unified fields to enable safe substitutions before release.

Hot-plug (5/9/15/20 V)

Measure inrush, VBUS shape, PG chatter under repeated inserts.

  • Log: inrush_peak, t_rise, pg_state, fault_code
  • Pass: inrush ≤ window; PG ≤ 1 bounce/insert

VBUS–GND Short

Pulse short near port; capture detect and cutoff.

  • Log: t_detect, t_off, fault_code
  • Pass: t_detect ≤ 200 ns, t_off ≤ 5 μs, SOA safe

Cable Flip / Mis-insert

CC1↔CC2 role swap; SBU coupling; verify recovery.

  • Log: cc_role, pg_state, fault_code
  • Pass: role switch time ≤ target; no persistent FAULT

ESD Strikes

Pins/shield/near-trace hits; compare clamp and reboot.

  • Log: v_clamp, pg_state, reboot_flag
  • Pass: VCLAMP within window; no ghost reset

Reverse / OR-ing

Dual-source switch with load step; check reverse peak.

  • Log: i_rev_peak, t_recover, priority_state
  • Pass: Irev ≤ target; trecover ≤ 10–50 μs; no drop

Thermal Sweep

−20/25/85/105 ℃ quick-run scenarios 1–5.

  • Log: ovp_actual, ilim_set, drift_%, pg_state
  • Pass: drift within window; PG stable
Scenario Inject Measure Log Fields Verdict
Hot-plug Std cable; repeat Inrush, PG inrush_peak, t_rise, pg_state, fault_code ✓ window / ! review / × fail
VBUS-GND Short Pulse near port tdetect, toff, SOA t_detect, t_off, fault_code tdetect ≤ 200 ns; toff ≤ 5 μs; SOA ok
Cable Flip CC1↔CC2 swap Role, recovery cc_role, pg_state, fault_code Switch ≤ target; stable PG
ESD Strikes Pins/shield/traces VCLAMP, reboot v_clamp, pg_state, reboot_flag Clamp ≤ window; no ghost
OR-ing Dual source swap Irev, trecover i_rev_peak, t_recover, priority_state Irev ≤ target; no drop
Thermal Sweep −20/25/85/105 ℃ OVP/ILIM drift ovp_actual, ilim_set, drift_%, pg_state Within window; stable PG
Cable-flip detection & near-port placement CC1↔CC2 role detection arrows, low-cap ESD/TVS placed close to receptacle, VBUS protector location, and probe points. USB-C Receptacle Keep ESD ≤ Y mm CC1 CC2 Flip detect CC/SBU Low-Cap ESD C_line ≤ 0.6 pF VBUS Protector OVP · ILIM · t_detect/t_off VBUS Gate PG/FAULT System Load domain
Cable-flip handling with CC1/CC2 detection and near-port protection placement; probe points for VBUS, Gate, and PG/FAULT.
Release gate (paste into checklist): Complete scenarios 1–6 with logs v_clamp, t_detect, t_off, ilim_fast, i_rev_peak, t_recover, pg_state, fault_code. Map telemetry before A→B rollout. No mapping → no production.

Series-Level Mapping with Concrete Part Numbers

Use three keys — Voltage bin (5 V only / up to 20 V / 21–28 V), Strategy (fast / foldback / latch / hiccup / reverse-blocking), and Interface (GPIO / I²C / PMBus) — to choose equivalents across TI / ST / NXP / Renesas / onsemi / Microchip / Melexis. This page lists connector-side parts only.

CC/SBU — Low-Cap ESD / Port Protectors

Brand Series / PN Notes
TI TPD4S311A USB-C port protector with CC/SBU protection; low capacitance, ESD/transient clamp.
ST TCPP01-M12, USBLC6-4, ESDA25P35-1U1M Type-C port protector + low-cap ESD/TVS combo for CC/SBU/DP lines.
NXP NX48P0407, NX20P3483 High-voltage CC/SBU protection; short-to-VBUS tolerance.
onsemi FUSB251 Dedicated CC/SBU protector for Type-C ports.
Renesas (use low-cap ESD arrays + ISL power-path parts) Combine generic low-C ESD with ISL VBUS/OR-ing devices.
Microchip (pair low-C ESD arrays with load switches) Keep CC/SBU protection close to the receptacle.
Melexis — No dedicated CC/SBU protectors; use brands above for ESD/port protection.

VBUS — eFuse / Hot-Swap / OVP Load Switch

Voltage bin TI ST NXP Renesas onsemi Microchip Melexis
5 V only (downstream) — TCPP01-M12 NX30P6093 ISL6186 NIS5021 (12 V eFuse usable upstream) MIC94161 (reverse-blocking load switch) —
up to 20 V (PD SPR 100 W) — TCPP01-M12 (+ TVS) NX30P6093 — NIS5021 — —
21–28 V (industrial / PD EPR edge) TPS25940 — — — — — —

OR-ing / Reverse-Blocking (Ideal-Diode Controllers)

Brand Series / PN Notes
TI LM74700-Q1 Ideal-diode controller for low-drop OR-ing; automotive-grade.
Renesas ISL6146 OR-ing controller with priority and reverse-current control.
onsemi (use with NIS eFuses + external MOSFETs) Common combo: NIS front-end + MOSFET OR-path.
Microchip MIC94161 (reverse-blocking load switch) Low-drop reverse-blocking for smaller currents.
ST / NXP / Melexis (project-specific: eFuse + MOSFET implementation) For connector-side focus, TI/Renesas are the main OR-ing families.

A→A (Same brand/series)

  • ESD class & line capacitance not downgraded (IEC ≥ ±8/±15 kV; Cline ≤ 0.6 pF)
  • OVP/ILIM/timing within project window (tdetect ≤ 200 ns; toff ≤ 5 µs)
  • PG/FAULT semantics unchanged (logic polarity/text)

A→B (Cross-brand)

  • Update telemetry mapping first: ilim_set, ilim_fast, i_rev, fault_code
  • Run and pass the Chapter-4 test matrix (hot-plug/short/flip/ESD/thermal)
  • OR-ing metrics (ΔV@I, Irev_peak, trecover) within window; no brown-out on switchover
USB-C power-path: CC/SBU ESD + VBUS eFuse + OR-ing Connector-side stack showing CC/SBU low-cap ESD, VBUS TVS+eFuse, and ideal-diode OR-ing path. USB-C Receptacle CC1/CC2 · SBU1/SBU2 · VBUS Low-Cap ESD C_line ≤ 0.6 pF TVS + eFuse OVP · ILIM · fast trip Ideal-Diode OR-ing low ΔV · reverse block System Load PG / FAULT / ALERT
Connector-side stack — CC/SBU low-cap ESD, VBUS TVS+eFuse, and ideal-diode OR-ing.

BOM Remark Templates (This Page Only)

Copy into your BOM. Variables (X, Y, Z, Z1, ΔV_max@I_load) are project windows aligned with test results.

CC/SBU ESD

“Use low-cap ESD arrays on CC/SBU (Cline ≤ 0.6 pF); IEC 61000-4-2 contact ≥ ±8 kV / air ≥ ±15 kV; TLP clamp ≤ X V @ ITLP; trace length to receptacle ≤ Y mm.”

VBUS Protector

“Connector-side eFuse/Hot-Swap: OVP window (5 V: 6.0–6.2 V / 20 V: 24–28 V); short detection ≤ Z ns; turn-off ≤ Z1 µs; PG/FAULT semantics aligned with this page.”

OR-ing Requirement

“Ideal-diode path ≤ ΔV_max@I_load; reverse-current threshold and recovery per test record; no brown-out during dual-source switchover.”

Telemetry Mapping

“Before substitution, update cloud/edge mapping (fault_code, ilim_set, ilim_fast, i_rev). No shipping without mapping.”

Separation of Responsibilities

“Select protection ICs separately from PD controllers; protocol parameters must not replace protection parameters.”

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Fault Injection & Observables

Turn high-risk connector-side issues into executable scripts and measurable windows, so substitutions won’t fail in pilot runs. Use placeholders X/Y/Z/N as project windows aligned with your Chapter-3 selection table.

Intermittent Short (1 µs ON / 100 µs OFF)

  • Purpose: verify tdetect, fast-trip toff, SOA margin, PG stability over thermal cycles.
  • Setup: VBUS bin=5/9/15/20 V; pulse source with 1 µs conduction, 100 µs pause; 104 repetitions.
  • Observe: tdetect ≤ 200 ns; toff ≤ 5 µs; PG glitch count ≤ N/min; ΔTFET ≤ Z °C.
  • Fail if: PG chatter > N/min, SOA excursion, or auto-restart oscillation.

Post-ESD “Ghost Reset”

  • Purpose: ensure PG cleanliness, I²C ALERT frame integrity, and proper latch/hiccup strategy.
  • Setup: ±8 kV contact / ±15 kV air; hits at shell, shield, near-trace; 10 shots per point.
  • Observe: PG pulse width < Y ms, ALERT CRC-OK ≥ 99%, FAULT latch set when required.
  • Fail if: spurious resets, bus corruption, or unlatchable faults.

OR-ing Switchover Reverse Spike

  • Purpose: bound reverse current peak and recovery, check priority retention.
  • Setup: Main↔Backup handover both directions under Iload=rated.
  • Observe: Irev peak ≤ X A; trecover ≤ 20–50 µs; no priority flip; ΔV@I within window.
  • Fail if: brown-out, priority reversal, or Irev overshoot.

Over-VBUS Mis-Supply (24–28 V)

  • Purpose: prove OVP window, back-to-back FET stress, and safe latch/retry.
  • Setup: inject 24–28 V for 10–50 ms at receptacle; monitor Vdownstream, gate, FAULT.
  • Observe: OVP triggers; tlatch/tretry as spec; no downstream over-stress.
  • Fail if: pass-through over-voltage or FET thermal runaway.
Fault-injection observables for USB-C Intermittent short, post-ESD PG chatter, reverse-current spike during OR-ing, and over-VBUS behavior with latch/hiccup; annotated timing and thresholds. Intermittent short t_detect ≤ 200 ns, t_off ≤ 5 µs Post-ESD PG chatter PG pulses < Y ms, ALERT CRC-OK ≥ 99% OR-ing reverse spike I_rev_peak ≤ X A, t_recover ≤ 50 µs Over-VBUS (24–28 V) OVP clamp → latch/retry; no pass-through
Fault-injection observables: intermittent short, post-ESD PG chatter, reverse-current spike, and over-VBUS behavior with latch/hiccup.

Layout & Floorplan Essentials (Connector-Side)

Near-Port Placement

Place ESD/TVS as close as possible to the receptacle; straight traces, minimal stubs, return path defined. Distance to port ≤ Y mm.

Loop Minimization

Shrink hot VBUS loop; separate high-di/dt power loop from CC/SBU signal loop; shield shell-to-ground via fan-out near the TVS.

Thermal vs. Sense Decoupling

For Hot-Swap/eFuse, provide copper for heat; route Kelvin sense away from gate/PG/FAULT; avoid sense vias inside hot copper islands.

Probes & Pads

Add TP_PG, TP_FAULT, TP_I_sense+, TP_I_sense–; place thermal stickers on FET back (center + edge) for ΔT tracking.

Connector-near protection floorplan Near-port ESD/TVS, short return paths, hot-swap copper zoning, and Kelvin sense points; measurement pads for PG/FAULT/I_sense. USB-C Receptacle ESD / TVS near-port ≤ Y mm eFuse / Hot-Swap thermal copper + vias Ideal-Diode OR-ing equal length/width TP_I_sense+ TP_I_sense– TP_PG TP_FAULT
Connector-near protection floorplan: near-port ESD/TVS, short return paths, Hot-Swap copper zoning, Kelvin sense points, and probe pads.

FAQ

Why do CC/SBU lines need ultra-low-capacitance ESD instead of generic TVS?
Ultra-low-C arrays protect without degrading the differential impedance of CC/SBU and sideband channels. Generic TVS often adds several picofarads, detuning Type-C detection and SBU integrity, especially during cable-flip and Alt-mode probing. Keep Cline ≤ 0.6 pF and place devices within a few millimeters of the receptacle.
How fast must the VBUS disconnect be for a hard short at the receptacle?
Treat a hard short as a µs-scale event. Trip detection should occur in hundreds of nanoseconds, and the pass FET must reach a safe off state within a few microseconds. A good working window is tdetect ≤ 200 ns and toff ≤ 5 µs, verified across bins at 5/9/15/20 V and worst-case temperature.
Do I still need ideal-diode OR-ing if my eFuse supports reverse blocking?
Reverse-blocking eFuses protect against back-feed but don’t guarantee low drop or seamless source priority. Ideal-diode controllers minimize ΔV and manage Irev during switchover, avoiding brown-outs and priority flips. Use the eFuse for fast trip and the ideal-diode for continuous OR-path quality and low-loss redundancy.
What OVP window should I set for 5 V-only sinks vs 20 V-capable ports?
Use narrow OVP near the bin: for 5 V, 6.0–6.2 V avoids nuisance trips yet blocks 9–20 V mis-supply. For 20 V ports, 24–28 V blocks EPR edges and transient overshoot. Validate clamp with the same TVS used in hardware so timing remains “TVS clamps first, eFuse disconnects second.”
How to verify coordinated clamp timing between TVS and eFuse fast-trip?
Drive a controlled surge or short; probe VBUS at the receptacle, the TVS node, and the eFuse gate. Pass if the TVS clamps to VCLAMP before the pass FET leaves its SOA and the eFuse turns off within the µs window. Fail if clamp delay or FET heating exceeds the project limits.
Will cable-flip stress SBU lines without DP/ALT-mode enabled?
Yes, probing during flip can couple energy into SBU even when Alt-mode is off. Keep SBU protected with low-C arrays, route SBU away from hot VBUS loops, and validate with ESD hits at shell and near-trace points. A clean layout prevents false detection and avoids post-ESD PG chatter.
How do I prevent PG chatter after an ESD hit on the shell?
Provide a low-impedance shell-to-ground return and place the TVS close to the receptacle. Add PG de-glitch filtering if allowed, and verify ALERT/FAULT latch paths. Your pass criteria are short PG pulse width, intact ALERT frames, and no autonomous restarts across repeated ±8/±15 kV hits at multiple points.
Can I parallel two eFuses for higher current on VBUS?
Paralleling is risky without current-share control. Mismatch in RDS(on) and trip timing can overload one path. Prefer a single higher-rated device or a controller that supports share and foldback coordination. If you must parallel, validate thermal balance and identical ILIM/timing across temperature.
What’s a safe ESD level for CC pins when the board is hand-routed?
Target at least ±8 kV contact, ±15 kV air with low-cap arrays, and keep the distance to the receptacle small. Hand routing increases parasitics and loop area; compensate with straight traces, short stubs, and a defined return. Validate using gun hits on shell and near the CC trace.
How do I log which fault actually triggered the disconnect?
Use a consistent FAULT code map and capture a short trace around the event: PG state, ALERT source, and eFuse status registers. Store the code and timing in a ring buffer so post-ESD or short-cycle tests are attributable. Treat unmapped codes as a failure until telemetry mapping is updated.
When should I use Hot-Swap (external MOSFET) instead of an integrated eFuse?
Choose a Hot-Swap controller when you need higher SOA, tailored dV/dt control, or back-to-back FET sizing unavailable in a single chip. eFuses are compact and fast to trip, but external MOSFETs scale current and thermal design better. Validate timing and OVP exactly as with eFuses.
What must be in the BOM so purchasing won’t pick a slow-response alternative?
Add explicit windows: low-cap ESD Cline ≤ 0.6 pF; OVP = 6.0–6.2 V (5 V) or 24–28 V (20 V); tdetect ≤ 200 ns; toff ≤ 5 µs; ΔV@I and Irev limits; PG/FAULT semantics. Require telemetry mapping updates before any A→B substitution.
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