Medical / Metrology Input Protection

Pre-isolation input protection must reconcile three tensions: surviving high-voltage and ESD energy, preserving accuracy/low noise, and meeting safety compliance. The practical path is layered: limit energy (series R/PTC/fuse or eFuse policy), cascade clamps (GDT/TSS to shed energy → low-R_dyn TVS to reduce residual → low-leak soft clamp to a clean reference), and controlled bleed to chassis using medical-grade C_Y and a bleed resistor. Every clamp/bleed element must enter both the patient-leakage budget and the error budget (bias, bandwidth, CMRR) so the AFE does not saturate and the design passes audits.

Four Parameter Cards

Compliance Checklist (copy to BOM/review)

• Pre-isolation clamps selected by residual-band; patient-leakage model covers N/SFC with temp/tolerance worst-case.
• CAT __ / Uimp __ kV validated per IEC 61010; divider network derated; creepage/clearance verified with slots where needed.
• ESD/EFT/Surge injection paths defined (port/chassis, CM/DM); pass criteria: residual to AFE < limit and functional recovery < __ ms.
• C_{in_total} budget documented per channel; anti-alias filter and CMRR targets maintained.
• Any element open/short (SFC) keeps leakage and thermal rise within limits; mitigation recorded.

Patient-contact channels must survive surges while keeping instrumentation stages out of saturation and meeting BF/CF leakage limits. The practical stack is: input limit energy (R/PTC/micro-fuse), cascade clamps (spark gap/GDT→TVS→low-leak reference clamp), and controlled bleed (R_bleed + medical-grade C_Y to chassis). All clamp/bleed elements enter the I_patient budget and the error budget (bias, bandwidth, CMRR). Single-fault (SFC) open/short must still hold leakage and thermal limits.

Single Fault Condition (SFC) Table

Low-Leakage Parts Shortlist

For CAT-rated instruments, the HV divider, surge cascade, and range switching must tolerate the working voltage and Uimp while preserving accuracy and bandwidth. Divider failure must fall into a controlled path (limit energy → disconnect), relays/SSR need spark-gap or RC snubbers and dv/dt control, and CAT/Uimp define creepage/clearance, power, and package ratings.

Divider Power & Temperature Card

Range Switching Protection Card

Build a layered path from energy shedding to residual clamping and finally low-C/low-leak finishing. Choose components by goals → layers → device families → key parameters → layout rules. Priority rules: shed energy first (GDT/TSS/MOV), then minimize residual with low-Rdyn TVS and soft clamps; on the measurement side, favor low capacitance and low leakage over nominal VRWM. Electronic disconnect (eFuse) governs the energy integral.

Engineering Matrix (HTML, copy-ready)

Engineering Matrix (CSV, copy-ready)

goal,layer,device_family,key_params,layout_notes,path
Leakage limit,Return-Path,CY+R_bleed,"Iac=ωCY*Vmains; Idc=Vref/R_bleed; Ileak_sum","shortest-to-chassis, single-point-bond, diff-symmetry",Medical
Saturation avoidance,Residual-Clamp,TVS+low-leak soft clamp,"Rdyn, Ceq, Ileak, tclamp","near-AFE-ref, star-return, minimal-loop",Both
Surge survival,Energy-Shed,GDT/TSS/MOV,"Vhold/Vbr, ITLP, tarc, life","upstream-of-TVS, chassis-first, short-&-wide",Both
Energy policing,Limit-Energy/Disconnect,eFuse/PTC/Fuse,"Ilim, int(I^2)dt, Pdiss, foldback/hiccup","thermal-path, stable-sense, route-to-shed",Both
Bandwidth integrity,Low-C ESD,ESD array (low C),"Ceq@100MHz, Vbr, Ileak","closest-to-pins, diff-pair-symmetry",Both
Range safety,Range-Switch,Relay/SSR/Analog-SW,"ton/toff, leakage, dv/dt, Ron, snubber","open-before-close, deadtime, clamp-assist",Metrology

Use conservative quick formulas to size leakage, residual, bandwidth and energy budgets; validate later with transient tests. Evaluate N and SFC states separately. For repeated surges, combine eFuse foldback/hiccup with the upstream energy-shed stage and verify the equivalent power.

Computation Card (copy-ready)

Examples (ECG channel & CAT III/600 V)

Translate protection intent into board practice: route high-energy paths to chassis first, keep return loops tiny, enforce creepage/clearance with slots and mask keepouts, apply guard rings and driven shields around precision inputs, and manage thermal spacing for dividers, relays, SSRs, and eFuses.

Layout Checklist — 15 Hard Rules

1. Place CY + R_bleed at the connector boundary; bond shortest to chassis/PE.
2. Put TVS upstream of measurement nodes; minimize loop area to its return.
3. Close ESD loops locally to the same reference plane; avoid long meanders.
4. Use mask keepouts and milled slots to enforce creepage/clearance targets.
5. Route high-energy returns to chassis first; keep analog reference isolated.
6. Add HV silkscreen markers near critical gaps and arc paths.
7. Implement guard ring around IA/TIA inputs tied to a low-impedance reference.
8. Use driven shield for sensor leads; maintain symmetry for differential pairs.
9. Keep eFuse/PTC away from precision AFE; provide copper for heat spreading.
10. Distribute divider power; estimate ΔT from Vi²/Ri and θJA,eq.
11. Reserve spacing for relays/SSRs; include snubbers across arcing contacts.
12. Star-return sensitive nodes; avoid stitching that creates unintended loops.
13. Place surge shed (GDT/TSS/MOV) closest to the entry and chassis bond.
14. Keep anti-alias networks compact; account for their contribution to Cin,total.
15. Document measured creepage/clearance and slot dimensions on the fab notes.

Layout Check Card (Print to A4)

Execute a repeatable port-level validation plan covering ESD, EFT, Surge, CAT working voltage with Uimp, and medical leakage. For each family, define setup, injection path, probe bandwidth/window, pass criteria, and screenshot naming so results are comparable and auditable.

Validation Matrix — CSV Template (copy-ready)

TestID,Family,Subtype,Port/Node,Setup,Level,Reps,ProbeBW,Window,PassCriteria,Observed,Verdict,Screenshot,Notes
ESD-01,ESD,Contact,+/- Port Pin,"Gun direct, 8kV",8kV,10,200MHz,10ms,"Vres ≤ V_AFE,max & recovery ≤ 20ms",,<PASS/FAIL>,, 
ESD-02,ESD,Air,Enclosure,"10cm, 15kV",15kV,10,200MHz,10ms,"No latchup; recovery ≤ 20ms",,<PASS/FAIL>,, 
EFT-01,EFT,Clamp,Port Bundle,"Coupling clamp",2kV,1k bursts,100MHz,5ms,"No false trigger; jitter ≤ spec",,<PASS/FAIL>,, 
SUR-01,Surge,CM,L-G,"1.2/50 μs",2kV,5,100MHz,5ms,"eFuse foldback OK; no damage",,<PASS/FAIL>,, 
SUR-02,Surge,DM,L-L,"1.2/50 μs",1kV,5,100MHz,5ms,"Vres window within limit",,<PASS/FAIL>,, 
CAT-01,CAT,Uimp,Input,"As per CAT rating",3kV,3,100MHz,5ms,"Divider ΔT within limit; integrity OK",,<PASS/FAIL>,, 
LEK-01,Leakage,Patient,N/SFC,"BF/CF config",--,--,--,--,"Ipatient ≤ limit (N/SFC)",,<PASS/FAIL>,, 
      

Buckets focus on pre-isolation protection for Medical/Metrology front-ends. Selection favors low leakage, low equivalent capacitance, controlled residual window (low R_dyn), and energy-safe eFuse/Hot-Swap policies. Notes specify what makes each part pass guardrails (leakage, Cin,total, Vres bandwidth, ∫I²dt).

Representative Parts by Brand & Function (with reasons)

Cautions per Domain

• Medical (BF/CF): include diode/TVS I_leak in patient-leakage budget; count C_eq into input bandwidth and offset; verify N/SFC.
• Metrology (CAT/Uimp): match divider power/creepage to CAT class; verify surge path (CM/DM) and residual bandwidth fits V_AFE,max.

Preserve leakage, equivalent capacitance, residual voltage bandwidth, and energy trajectory when swapping brands. Unify eFuse policy semantics (I_lim, timers, foldback/hiccup) to keep ∫I²dt under SOA. For TVS, match R_dyn and V_res(t,f); for divider stacks, keep value/tolerance/power/voltage and distribution thermal management consistent.

Migration Checklist — 10 Hard Checks

1. Sum I_leak (clamp + ESD arrays) into Medical patient-leakage budget (N/SFC).
2. Verify C_eq@100 MHz ≤ signal-path limit; measure bandwidth shift vs. target.
3. Match TVS R_dyn and residual-voltage bandwidth to keep V_res(t,f) ≤ V_AFE,max.
4. Re-tune eFuse I_lim, timer, foldback/hiccup so ∫I²dt ≤ SOA of TVS/divider.
5. Unify PG/FAULT semantics and recovery time (e.g., ≤ 20 ms) across brands.
6. Keep divider value/tolerance/power/voltage ratings and ΔT distribution unchanged.
7. Preserve creepage/clearance and slot strategy; re-mark HV silkscreen if package changes.
8. Confirm Uimp/CAT class with the new BOM (datasheet + test evidence).
9. Re-run ESD/EFT/Surge with the new parts; capture residual and recovery screenshots.
10. Update validation CSV and BOM notes; freeze versions for traceability.

BOM Remark Template (copy-ready)

[BOM Remark — Pre-Isolation Protection]
1) Clamp path: total leakage (diode/TVS/ESD) ≤ patient-leakage budget (N & SFC). List measured I_leak@25/50 °C.
2) Data-side ESD arrays: C_eq@100 MHz ≤ ____ pF per lane; confirm eye/bandwidth OK.
3) TVS residual: R_dyn matched; V_res(t,f) ≤ V_AFE,max with scope evidence.
4) eFuse policy: I_lim=___ A, t_lim=___ ms, mode=[foldback/hiccup]; ∫I²dt ≤ TVS/divider SOA.
5) Divider stack: values/tolerances/power/voltage unchanged; ΔT verified ≤ ___ °C at worst case.
6) CAT/Uimp: class=___, Uimp=___ kV; creepage/clearance and slot geometry documented.
7) PG/FAULT semantics: compatible; recovery ≤ ___ ms; no latch after ESD/EFT/Surge.
8) Re-validation: ESD/EFT/Surge levels per plan; attach screenshots (filename convention).
[Brands allowed: TI / ST / NXP / Renesas / onsemi / Microchip / Melexis. Cross-brand changes must re-run validation matrix before release.]