Index of memory topics: NOR/NAND, eMMC/UFS, EEPROM/FRAM/MRAM, DRAM/LPDDR/PSRAM/SRAM/eDRAM, controllers & management (FTL/ECC/training/crypto), key specs, use-case mapping, design hooks and quick pairings.
Non-Volatile Memories
Parallel NOR Flash
XIP, fast random reads, slower program/erase; async parallel bus with page buffers for code/boot storage.
SPI/QSPI/OSPI NOR Flash
1/4/8-line interfaces, Octal/HyperBus with DTR; code plus small data, optional XIP.
Raw NAND (SLC/MLC/TLC/QLC)
High capacity, page/block ops; requires FTL/ECC/bad-block handling (ONFI/Toggle) for logs & bulk data.
eMMC / UFS (Managed NAND)
Controller with ECC & wear leveling built-in; HS400/UFS gears; ideal for system/rootfs and cameras.
EEPROM (I²C/SPI/Microwire)
Byte-write granularity, 10⁵–10⁶ endurance; great for parameters, calibration and small logs.
FRAM / FeRAM
Near-SRAM speed with 10¹²+ endurance and retention; frequent parameter writes, metering.
MRAM / ReRAM
Non-volatile with high endurance and low write power; store critical state for power-loss recovery.
NVRAM Solutions (NVSRAM + Supercap/Battery)
On power-fail, mirror to non-volatile storage for transient protection and quick recovery.
Volatile Memories
DRAM (SDR/DDR2/3/4/5)
High bandwidth/low cost; tRCD/tRP/tCL timing and refresh; main memory, frame buffers, caches.
LPDDR (LPDDR2/3/4/5)
Mobile low-power DRAM with deep power states; for handhelds, embedded graphics and edge AI.
PSRAM / HyperRAM
DRAM core with SRAM-like interface; HyperBus/Octal ease of use for displays and mid-size caches.
SRAM (Async/Sync/Tag)
Ultra-low latency, smaller capacity; use for caches, high-speed tables and small dual-port needs.
Embedded DRAM / TCM
On-chip high bandwidth memory for accelerators, imaging pipelines and networking.
Controllers & Management
NAND Controller / FTL
ECC strength (BCH/LDPC), wear leveling, bad-block tables and static data refresh strategies.
eMMC/UFS Features
Boot partitions, RPMB secure area, health metrics and power-loss protection options.
DDR Controller / PHY
Write/read training, clock/jitter tolerance and temperature-aware refresh (T-REFI).
Security & Crypto
XIP authentication, storage encryption (AES/XTS) and anti-rollback/version counters.
Key Specs & Metrics
NOR/EEPROM/FRAM Metrics
Read latency, program/erase time, endurance, retention, sector/page size and temperature grades.
NAND/eMMC/UFS Metrics
Capacity, page/block sizes, interface rates, ECC needs, write amplification/TBW and robustness.
DRAM/LPDDR Metrics
Data rate (MT/s), bus width, timings, power states; Bandwidth = rate × width / 8.
PSRAM/HyperRAM Metrics
Read/write latency, burst depth, I/O level (1.8/3.0V) and hidden refresh behavior.
General & Qualification
ESD/temperature grades (industrial/automotive), service life/EOL and second-source availability.
Use-Case Mapping
Boot / XIP
Parallel NOR or Octal-NOR/HyperFlash (DTR) for execute-in-place boot paths.
Parameters / Frequent Small Writes
Prefer FRAM; alternatives: I²C/SPI EEPROM for light updates.
High-Capacity Data
Raw NAND + controller for maximum capacity, or eMMC/UFS for easier integration.
High-Bandwidth Cache / Imaging
LPDDR4/5 or DDR4/5 depending on platform requirements.
Mid-size Cache / Simple Bus
PSRAM/HyperRAM for moderate capacity with easy interfacing.
Power-Loss Data Integrity
FRAM/MRAM or eMMC with cache-protection plus supercap hold-up.
Design Hooks & Pitfalls
Boot Chain & Security
XIP image signature/rollback, dual-image fallback and using eMMC boot partitions safely.
ECC & Bad-Block Strategy
BCH/LDPC requirements vary by node; size for margin and validate at qualification.
Wear-Leveling & Filesystem
SPI-NOR: littlefs/FAT; NAND: YAFFS2 or UBI+UBIFS; eMMC/UFS use internal FTL.
Refresh & Power-Loss
DRAM refresh vs. temperature; refresh NAND/MLC/TLC data at high temp to avoid disturb/retention loss.
SI/PI & Layout
DDR length-match/impedance/continuous reference; OSPI/HyperBus lane matching & clock symmetry; tight decoupling.
Power Sequencing
Define rail order and back-feed protection; obey tPU/tR/tINIT before first access.
Temperature & Lifetime
High temp reduces retention/cycle life; check AEC-Q100 grades and retention curves.
Mass Production & Compatibility
Vendors differ in IDs/commands; abstract drivers and maintain a qualified second-source table.
Performance Tuning
OSPI/HyperBus with DTR + XIP cache; eMMC HS400 & deeper queues; DDR bursts/prefetch.
Secure Regions
Use eMMC RPMB/secure partitions and NOR protected sectors; isolate keys/certificates.
Quick Pairings
Boot + System Drive
Octal NOR XIP for boot + eMMC/UFS for root filesystem.
Metering / Industrial
FRAM params + SPI-NOR firmware + Raw NAND log (strong ECC).
Vision / Edge AI
LPDDR4/5 bandwidth + OSPI NOR boot + eMMC for datasets.
Automotive Gateway
A53/A55 + LPDDR4-ECC + eMMC health monitoring + secure boot + ring logs.
Wearables
QSPI NOR + FRAM params + PSRAM cache; deep sleep and fast wake.
