Intro
Power over Ethernet (PoE) lets a single cable carry power and data, simplifying wiring and deployment. Robust designs hinge on detection/classification compliance, reliable MPS keeping, the PD side’s hot-swap and isolated power stage, plus the PSE’s multi-port power budgeting and scheduling.
This page outlines architecture, timing, and practical rules to avoid mis-classification, dropouts, and thermal issues in IEEE 802.3af/at/bt systems.
Back to hub: Power Management ICs (PMIC)
Architecture
PD Path
RJ45 and magnetics feed a rectifier (optionally an ideal-diode bridge) into the PD controller that handles detection, classification, MPS, and hot-swap FET control. Power then enters an isolated Flyback/ACF to generate 3.3/5/12 V rails for the load.
PSE Multi-Port
A PSE controller/manager supervises per-port detection, inrush and current limit, applies 2-pair / 4-pair delivery, and coordinates LLDP power budgeting and priority across multiple ports.
Working Principle
PoE sequencing covers detection of the 25 kΩ signature, classification (2-event/4-event), controlled power-up/inrush, and continuous MPS (Maintain Power Signature). IEEE 802.3bt adds 4-pair delivery, LLDP negotiation, and PSE port-level budgeting.
Detection & Signature
The PSE verifies a ~25 kΩ PD signature and screens Capacitance/Open/Short conditions before power is granted. Moisture, contamination, or magnetics coupling may skew the apparent resistance—validate with a source-measure sweep and scope the port voltage.
Classification
IEEE 802.3af/at uses 2-event classification; 802.3bt uses 4-event to signal higher power. Physical class sets limits, while Autoclass/LLDP refine allocation dynamically. Keep class resistor accuracy and timing within tolerance to avoid mis-class.
Maintain Power Signature (MPS)
The PD must present periodic current draw within the MPS window (current threshold plus on/off duty). Light-load designs often need a small bleed or pulsed load to prevent dropouts; beware LED/relay loads that unintentionally fall outside the window.
Power-Up & Inrush
The PD’s hot-swap FET controls dV/dt and limits inrush; verify SOA against the worst-case input capacitance and cable conditions. Capture peak inrush, slope, and device temperature rise; watch transformer magnetizing current during the soft-start interval.
4-Pair Delivery
802.3bt can deliver power over four pairs. Keep pair currents balanced via symmetric magnetics and layout; unequal resistance or routing can overheat a pair or trigger early port fold-back. Design for equal length and comparable DC resistance across pairs.
Design Rules
Front-End & Protection
Place RJ45 TVS close to the connector; meet IEC 61000-4-2/-4-5 as required. Implement a correct Bob Smith termination network and pick a CM choke that avoids saturation over the PoE DC component. Consider an ideal-diode bridge to lower loss and case temperature versus Schottky.
PD Controller Essentials
Keep detection/classification resistor accuracy tight and include tolerance stacking. Set MPS timing to fit the real load profile. Check current limit and the hot-swap FET SOA. For APD (Adapter Priority Detect), implement proper ORing/ideal diode control to prevent back-feed to Ethernet power.
Isolated DC/DC
Choose Flyback or ACF by power range and efficiency targets; size synchronous rectification and gate drive margin. Optocoupler feedback is simple but adds aging/linearity drift; secondary-side sampling improves dynamics. Route the Y-capacitor with short returns to control leakage and EMI.
PSE-Side Strategy
Configure per-port inrush/current-limit, LLDP, and power budget; define port priority and graceful de-rate policies under overload. Watch thermal limits on compact packages and keep alarms/telemetry visible to system software.
Layout & EMI
Minimize high-di/dt loop area from bridge → hot-swap → bulk cap → transformer. Keep RJ45→PD controller routing symmetric; use split grounds across isolation and a clean slot under the transformer. Place TVS/bridge/bulk by proximity priority to tame surge and ringing.
Sizing & Quick Calcs
Bulk capacitance: Cbulk ≈ Istep·Δt / ΔV | Inrush slope: dV/dt ≈ Ilimit / Cbulk | Bridge loss (approx): P ≈ 2·Iavg·Vf (Schottky) or P ≈ Irms2·RDS(on) (ideal-diode) | SR gate margin: Vgate ≥ Vth + Δ with enough di/dt immunity.
Validation & Debug
Validate PoE designs with a repeatable scope checklist, stress them under corner conditions, confirm immunity and emissions, and use a compact fault tree to converge quickly on root causes.
Scope Checklist
Probe with ≥200 MHz bandwidth and short ground springs. Capture single-shot events and annotate limits. Verify the following traces on each new build:
- Detection & classification waveforms — stable 25 kΩ signature; correct 2/4-event levels and timing.
- Power-up inrush peak and dV/dt — within PD hot-swap FET SOA; no excessive ringing.
- MPS duty window — current pulses meet threshold and on/off window under all loads.
- Flyback primary/secondary waveforms — no saturation, controlled demag; SR timing correct.
- Startup overshoot/undershoot — rails settle within tolerance; no UV/OV latch.
Corner Cases
- Long cable: emulate worst-case drop; watch classification levels and inrush ringing; verify MPS at end-of-line.
- Cold start (low temp): bulk ESR↑ → higher inrush; confirm FET SOA and start-up time.
- Full/under-load: validate regulation, SR transitions, and MPS stability; check thermal rise.
- Short / intermittent shorts: confirm protection thresholds and recovery, including short-on / short-off cycling.
Compliance & Immunity
- IEC 61000-4-2 ESD: place RJ45 TVS close; verify contact/air levels; keep return as short as possible.
- IEC 61000-4-5 Surge: coordinate TVS + bridge + bulk placement; check clamp voltages and wave tail heating.
- IEC 61000-4-6 RF immunity: control Y-cap path; minimize common-mode loop; observe control loop perturbations.
- CISPR 32 emissions: shrink high-di/dt loops; snub ringing; review transformer shielding/grounds.
Fault Tree
Start from the symptom and follow one-step checks to either fix or exonerate each branch.
Applications
Typical PoE targets map naturally to af/at/bt power classes. Use the cards below to align rails and decide whether APD (Adapter Priority) is required.
IP Camera
Power class: at/bt | Rails: 5 V, 12 V | APD: Optional (local backup to avoid remote dropout).
Note: Watch cable drop on IR LED load; confirm MPS during night mode.
VoIP Phone
Power class: af/at | Rails: 3.3 V, 5 V | APD: No.
Note: MPS friendly; check acoustic load pulses from hands-free amplifier.
Wi-Fi Access Point
Power class: at/bt (4-pair recommended) | Rails: 3.3 V, 5 V, 12 V | APD: Optional.
Note: Ensure pair-current symmetry; verify LLDP budget during peak throughput.
Industrial Sensor / IO-Link Gateway
Power class: af/at | Rails: 5 V, 12 V | APD: Optional.
Note: Validate surge and EFT; confirm MPS with bursty field I/O.
Thin Client / Small Panel PC
Power class: bt (4-pair) | Rails: 12 V, 5 V | APD: Recommended.
Note: Check thermal headroom and steady MPS at idle/boost transitions.
LED PoE Luminaire
Power class: at/bt | Rails: LED constant-current + 5 V control | APD: No.
Note: Ensure dimming scheme preserves MPS; verify EMI with long ceiling runs.
IC Selection
Choose PoE controllers by power class (af/at/bt) or by integration (PD all-in-one, PD + PWM, or multi-port PSE). Cards below are indicative—always verify with the latest datasheet.
Quick Filter
By Power Class
Class 0–4 (af/at, ~15–30 W)
Fit: af/at | Role: PD+primary PWM combo.
Highlights: integrated hot-swap, current limit, flyback-friendly; supports Autoclass via system logic.
Notes: good for IP cameras/APs; check SR gate drive headroom.
Datasheet: refer to vendor documentation.
Fit: af/at | Role: PD+PWM integration.
Highlights: robust detection/classification, hot-swap FET drive, EMI-aware references.
Notes: place TVS and bridge close; observe layout keep-ins for primary loops.
Datasheet: refer to vendor documentation.
Fit: af/at | Role: PD only (external PWM).
Highlights: MPS control, inrush limiting, adapter ORing support via external FET/ideal diode.
Notes: verify APD priority and back-feed protection.
Datasheet: refer to vendor documentation.
Type 3/4 (bt/PoE++, up to ~60–90 W, 4-pair)
Fit: bt, 4-pair capable | Role: PD only (pairs with ACF/Flyback).
Highlights: 4-pair current sharing, hot-swap FET gate shaping, Autoclass/LLDP ready via system MCU.
Notes: match magnetics/trace symmetry to balance pair currents.
Datasheet: refer to vendor documentation.
Fit: at/bt options | Role: PD only; pairs well with external PWM/ACF.
Highlights: proven PowerDsine lineage, robust detection/classification, system-level reference designs.
Notes: confirm MPS with bursty loads; plan for Autoclass/LLDP if needed.
Datasheet: refer to vendor documentation.
By Function (Integration)
PD + PWM (All-in-One on Primary)
Power: af/at | Use: compact IP cam/AP supplies.
Highlights: hot-swap FET control, current limit, clean start-up for flyback.
Datasheet: refer to vendor documentation.
Power: af/at | Use: compact designs with low BOM count.
Highlights: solid classification timing, EMI-aware app notes.
Datasheet: refer to vendor documentation.
PD Only (External PWM/ACF)
Power: at/bt | Use: higher-power rails with ACF/SR.
Highlights: 4-pair aware; hot-swap dV/dt shaping; Autoclass/LLDP ready via host.
Datasheet: refer to vendor documentation.
Power: af/at/bt options | Use: flexible PD with external power stage.
Highlights: mature ecosystem; reference designs for cameras and APs.
Datasheet: refer to vendor documentation.
Power: af/at | Use: cost-effective PD with external flyback/ACF.
Highlights: configurable MPS; APD/ORing support with external FETs.
Datasheet: refer to vendor documentation.
PSE Multi-Port (Managers / Controllers)
Fit: multi-port bt PSE | Role: per-port current limit, power budget, LLDP interface.
Highlights: telemetry/alerts for switch integration; port priority/de-rate policies.
Datasheet: refer to vendor documentation.
Fit: managed PSE ports | Role: current limit, detection/class, budget control.
Highlights: scalable port counts; reference designs for enterprise switches.
Datasheet: refer to vendor documentation.
Fit: multi-port switches | Role: detection/classification, power budget, LLDP hooks.
Highlights: widely deployed in enterprise gear; rich diagnostics and firmware tools.
Datasheet: refer to vendor documentation.
Ecosystem & Peripherals
Complements PD parts with primary controllers and isolation devices; pair with PD-only chips for tailored efficiency and transient control.
Ideal-diode/active bridge and surge protection options to cut bridge loss and improve thermal headroom in higher-power PoE designs.
Peripheral sensing and support components for PoE end-equipment; pair with PD/PSE solutions as needed.
Selections are indicative. Always verify against the latest datasheet.
Still unsure which PoE PD/PSE fits your class and LLDP budget? Submit your BOM for a 48h cross-brand recommendation.
FAQs
What are af/at/bt power limits and how do 2-event vs 4-event classes map to real designs?
af targets ~13 W at PD input; at ~25.5 W; bt scales to 60–90 W with 4-pair delivery. af/at use 2-event classification while bt uses 4-event to communicate higher power. Physically classify for limits, then refine with LLDP or Autoclass. Validate timing windows and resistor tolerances on every build.
Ideal-diode bridge vs Schottky bridge — efficiency and thermal trade-offs?
Estimate Schottky loss as 2·Iavg·Vf; active bridges approximate Irms2·RDS(on). Above ~10–15 W, ideal bridges often cut several hundred milliwatts, reducing hotspot temperature and improving margin for EMI snubbers. Ensure controller reverse blocking and fast switchover to avoid brown-outs during transients.
How should I set the MPS duty window and avoid dropouts under light load?
Keep PD load pulses above the MPS current floor and within the allowed on/off ratio. Periodic or dimming loads (LED, relays) can slip outside the window. Add a small bleed or schedule short current bursts synchronized to system activity, then confirm with a long capture across temperature and cable length.
How does APD (adapter priority) prevent back-feed into Ethernet power?
Use ORing with an ideal-diode controller or FETs to isolate the adapter path from the PoE path. Sense adapter presence, switch priority with debounce, and guarantee reverse blocking to the RJ45. On failover, maintain rails with adequate holdup capacitance to avoid misclassification or MPS loss.
Flyback or ACF for the isolated stage — where is the boundary for efficiency and EMI?
Up to ~25–30 W, a well-designed flyback (with SR) is compact and efficient. Above that, ACF improves switching losses, winding stress, and EMI headroom, especially for 4-pair bt. Budget gate-drive margin for SR, and model transformer leakage to place snubbers precisely.
How do LLDP and physical classification work together, and when is Autoclass helpful?
Physical class caps maximum power; LLDP negotiates operating power more precisely at runtime. Autoclass measures actual consumption to tighten budgets on dense PSEs. Use LLDP/Autoclass in bursty or temperature-dependent loads, but test boundary cases so ports never drop below MPS thresholds.
How do I check hot-swap FET SOA and verify inrush safely?
Estimate peak and duration from Cbulk, dV/dt, and current limit; ensure the FET’s SOA curve covers worst case at low temperature. Capture peak current with a fast shunt and observe junction heating. Verify magnetizing current of the transformer does not add to the inrush stress window.
Any rules for Bob Smith termination and TVS part choice and placement?
Use recommended RC values per magnetics vendor; keep returns short and symmetrical. Place the RJ45 TVS as close as possible to the connector, meeting IEC 61000-4-2/-4-5 levels. Ensure current paths to ground avoid crossing the isolation slot and do not enlarge common-mode loops.
What matters for 4-pair PoE symmetry — routing and magnetics?
Keep pair lengths and copper resistance closely matched. Choose magnetics supporting 4-pair current without saturation, and route pairs symmetrically to share current. Any imbalance overheats a pair and reduces system margin, especially under bt high-power peaks and long cables.
How does the Y-capacitor path affect leakage and EMI in isolated PoE?
Y-cap improves common-mode EMI but adds leakage current and potential touch-current perception. Place it with the shortest return to minimize loop area and verify compliance against safety requirements. Tune value to pass CISPR while staying within leakage limits for your product category.
How do long cables and cold starts influence power-up timing?
Long runs increase drop and reflections; cold temperatures raise ESR, inflating inrush and delaying regulation. Validate detection/classification at end-of-line, then check inrush dV/dt and loop stability at low temperature. Ensure MPS still holds when rails settle more slowly than room-temperature baselines.
How should multi-port PSEs allocate power and set priority?
Define a global budget, allocate per-port caps, then apply port priorities. Under overload, de-rate gracefully—shed lowest priority or reduce negotiated power via LLDP. Telemetry is essential: log events so the switch can throttle peaks without flapping ports or misclassifying connected PDs.
Why do LED drivers sometimes lose MPS, and how do I fix it?
PWM dimming can average below the MPS threshold or violate the duty window. Add a bleed path or synchronize a maintenance pulse with the dimming frame. Confirm across brightness extremes, temperature, and cable length so MPS never drops during transitions or low-light stand-by.
Minimum parts to pass IEC 61000-4-5 surge on PoE lines?
A PoE-rated TVS near RJ45, a low-loss bridge or active bridge, tight primary loop, and proper common-mode choke selection handle most cases. Add RC snubbers across the transformer or rectifier as needed. Layout distances and return paths often determine success more than raw TVS ratings.
Field debug path for mis-classification, no-power, or random dropouts?
Start with signature accuracy and clean detection; confirm class timing and resistor stack. Next, validate MPS under the true load profile and check hot-swap inrush slopes. Finally, inspect PSE budgeting and LLDP logs for throttling events. Each step removes a frequent root-cause category quickly.
Resources & CTA
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