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Intro — What This Page Solves
PoE ports must balance three tensions: IEEE detection/classification integrity, surge robustness (including cross-pair), and low residual / low capacitance so differential signaling and MPS remain intact. A layered route works: shed energy with GDT/TSS, reduce residual with low-Rdyn TVS, then finish with a low-C ESD array near the RJ-45. Current limiting, soft-start, and metering must stay MPS-safe.
Standards Snapshot
This chapter aligns IEEE 802.3 (af/at/bt) rules for detection, classification, and MPS with the EMC trio IEC 61000-4-2 / -4-4 / -4-5. We translate clauses into design hard constraints: leakage and capacitance on detect/class paths, residual-voltage bandwidth for surge cascades, and MPS-safe filtering for metering/limits. Use the four quantified parameters below to keep ports compliant and robust.
IEEE 802.3 essentials (af / at / bt)
Keep the 25 kΩ signature intact. Clamp networks on the detect path must not add bias via leakage or biasing dividers.
Ensure classification accuracy; avoid series impedance or shunts that skew the current window.
RC filters and comparators for metering/limits must not mask DC or pulse-type MPS.
IEC test set (port application)
Contact/air to pins/shield. Observe residual to PHY; array capacitance must stay within differential budget.
Burst coupling can jitter power rules. Debounce policy thresholds and verify PG/FAULT semantics.
Handle CM energy via GDT/TSS then limit DM residual with low-Rdyn TVS; ESD array finalizes the window.
Carrier/industry specs (e.g., GR-1089) can require tougher cross-pair conditions—treat them as high-tier targets.
Four numbers you must quantify
Array + trace + magnetics must ≤ differential budget to preserve eye/MPS.
Total leakage must not bias signature or classification windows.
Time–frequency residual after cascade; choose TVS by residual band, not only VRWM.
RC/ADC bandwidth must keep DC/pulse MPS visible while rejecting bursts.
BOM remarks (copy & paste)
- PoE clamps must meet the residual-band spec without biasing IEEE detection/classification.
- Use low-cap ESD arrays; verify C_eq@100 MHz ≤ differential budget.
- Metering filter and eFuse/HS thresholds must be MPS-safe per this page.
Architecture — PSE-Side Port Protection
PSE ports should route common-mode energy to chassis at a single point, keep the detect/class path unbiased, and use a GDT/TSS → low-Rdyn TVS cascade ahead of the power-path eFuse/Hot-Swap. Metering must be MPS-safe whether you sense by shunt or magnetic pickup. This section provides placement order, distance guidance, and current-limit policy aligned to PoE budgets.
Placement & distance guidance
- Shield to chassis: single-point near the RJ-45; avoid multi-point straps on signal ground.
- Clamp cascade close to magnetics/RJ-45 with short, symmetric routes; minimize loop inductance.
- Low-C ESD arrays on data pairs at the connector exit; keep C_eq@100 MHz within differential budget.
- Metering before/after eFuse: ensure detect/class/MPS path remains unbiased; validate I_leak and filter corner.
Shield-to-Chassis options
Best CM energy drain; watch ESD return paths and avoid DC ground loops.
Blocks LF/DC, passes HF surges; tune R/C or L to your chassis impedance.
Keep short and wide; avoid multi-point ties that raise uncertainty.
eFuse/Hot-Swap limit policy vs PoE class
Ilim sized to budget + margin; short Timer with hiccup for large Cin.
Coordinate foldback with precharge; dV/dt to prevent PHY brown-out.
Check SOA at cold-start; allow thermal derate; ensure MPS not masked by filters.
Architecture — PD-Side Front-End
The PD front-end chooses between a bridge and an ideal-diode controller, then applies the same GDT/TSS → low-Rdyn TVS → low-C ESD cascade before a soft-start eFuse/Hot-Swap. MPS-friendly metering and filtering must keep DC/pulse MPS visible. Long cable plus large Cin needs staged precharge and slope control.
Bridge vs Ideal-Diode (selection notes)
Robust, simple; higher forward loss; no active I_rev control; slower switchover.
Low drop; fast priority switchover; specify ΔV_trip and I_rev; watch stability with large cables.
MPS-friendly filter templates
RC corner ≥ ~3/τ_pulse; comparator window centered on pulse amplitude; sample rate ≥ 5× pulse rate.
Keep static load above minimum hold; low-pass only to reject EFT; avoid excessive averaging that hides drops.
Startup script — long cable + large Cin
- Precharge via limited Ilim to a safe threshold; monitor rail droop and temperature.
- Enable slope control (dV/dt) to full voltage; verify no PG chatter, no repeated retries.
- Confirm MPS visibility under EFT/EMI; log PG/FAULT/INT for post-test analysis.
Clamp Cascade Design (CM/DM Surge Paths)
Use a layered cascade so the common-mode (CM) energy is shed by GDT/TSS, the differential-mode (DM) residual is narrowed by a low-Rdyn TVS, and the low-cap ESD array near the RJ-45 preserves the eye and protects the PHY. Design with quantified limits: Rdyn, Vresidual(t,f) band, Ceq@1/100 MHz, Ileak, and surge shot count.
Key bounds & quick estimates
- Allowed residual window: VPHY_safe < Vresidual(t,f) < VTVS,soft-knee
- Low-C array budget: Ceq,sum ≤ Cbudget (array + traces + magnetics)
- Cascade residual (rule-of-thumb): Vcm,port ≈ VGDT + Isurge·Rdyn,TVS
Clamps Matrix — structure
GDT/TSS / TVS / ESD-Array
V_trigger/V_hold or V_RWM, R_dyn, C_eq@1/100 MHz, I_leak, P_pp, N_shots
SMD series, pin symmetry, thermal
Distance to RJ-45, return path, relative to magnetics
Long stubs, cross-domain returns, ESD before TVS, biasing detect/class
CM/DM fit, temperature drift, aging
MPS-Safe Filtering & Power Rules
Preserve the Maintain Power Signature (MPS) for both DC and pulse modes. Filters, ADC bandwidth, comparators, and averaging must not hide MPS. Power policing must align with PoE class budgets and be de-coupled from hiccup/averaging to avoid false under-power trips.
Key bounds & policies
- Pulse MPS bandwidth: if pulse width is Tp, choose fc ≥ α / Tp (empirical α ≈ 3)
- Policing consistency: Ilimit · Vport ≥ Pclass + ΔPmargin
- De-couple hiccup and averaging; never let averaging hide pulse MPS edges
RC/ADC quick reference (af / at / bt)
MPS: DC or slow pulse
fc ≳ 3/Tp (if pulse)
Sample ≥ 5× pulse rate
Comparator with small hysteresis (avoid chatter)
Pulsed MPS common
fc target mid-band; avoid heavy averaging
Hold-off for EFT bursts; log PG/FAULT edges
Higher power → verify SOA with dV/dt
Ensure hiccup window decoupled from averaging
Maintain MPS visibility during startup ramps
“Metering ⟷ MPS non-interference” checklist
- Filters/ADC never reduce MPS visibility (DC or pulse).
- Detect/class path is not biased by metering leakage.
- fc and sample rate satisfy Tp bounds; set explicit hysteresis.
- Power policing averaging is de-coupled from hiccup logic.
- eFuse dV/dt does not mask pulse-MPS; verify during ramps.
- PG/FAULT semantics and logs are consistent and timestamped.
- MPS survives EFT/EMI; define minimum pulse-width qualifier.
- Long-cable + large Cin cases include MPS visibility tests.
- Record Vport, Ilimit, MPS_event_count, Fault_code.
- Production test includes MPS visibility, self-protection recovery, and false-trip avoidance.
eFuse/Hot-Swap Policy & SOA
Parameters & modes
Tune Ilim, Itrip, Timer, gate dV/dt, and verify against device SOA under the expected repetition rate. Choose fault policy: Hiccup, Foldback, or Latch. Define PG/FAULT semantics and debounce to avoid spurious resets.
Align with PoE class power budget
- Ilim · Vport ≥ Pclass + ΔPmargin (allow for cable drop, startup inrush, temperature derating).
- Coordinate Timer vs. inrush (Cin, cable length) so that PG does not chatter; add post-fault hold-off.
- Use dV/dt to avoid PHY brown-out and preserve MPS visibility during ramps.
SOA verification at repetition rate
Validate the current pulse (I, ton) and its repetition (1/Trep) against the MOSFET/eFuse SOA surface. Use a simple thermal estimate (ΔT ≈ P · Rθ,eq) and ensure accumulated heating stays below limits across environmental corners.
Extreme startup: long cable / large Cin
- Precharge to a threshold with limited Ipre; monitor Vport droop and device temperature.
- Apply slope-controlled ramp (dV/dt) to full voltage; verify PG stability and no repeated retries.
- At low temperature (high ESR), extend Timer and set a bounded number of hiccup attempts.
PG/FAULT ↔ Power policing interlock
On fault, freeze metering window, log snapshot (Vport, Iport, Tj, codes), then apply policing rules. Separate the average window used by policing from the hiccup decision to avoid ping-pong cycling.
Strategy matrix (load / cable / thermal → dV/dt, Ilim, Timer)
dV/dt: medium; Ilim: Pclass/Vport + small margin; Timer: short; Mode: foldback.
dV/dt: slow; Ilim: higher with precharge; Timer: extended; Mode: hiccup with bounded retries.
dV/dt: gentle; Ilim: derated; Timer: thermal-aware; Mode: foldback + telemetry latch.
PG/FAULT mapping template
PG_OK / UVLO / OCP / OTP / Surge_trip
eFuse / TVS / Meter / ADC comparator
Vport, Iport, Tj, MPS_state, counters
Hold-off / Retry / Latch & Log / Notify host
Metering Hooks & Placement
Placement overview
PSE: meter before or after eFuse; PD: before/after bridge or ideal diode. Do not bias detect/class/MPS paths; control Ileak.
Shunt vs magnetic sensing
High accuracy/bandwidth; power loss = I²·Rshunt; needs Kelvin sense & low-drift amplifier.
Low loss & isolation; medium-high bandwidth; handle offset drift and external magnetic fields.
Bandwidth & algorithms
- Pulsed MPS: if pulse width is Tp, choose fc ≥ 3/Tp; sample ≥ 5× pulse frequency.
- Use sliding average for power, peak detector for OCP; add EFT suppression and a minimum pulse-width qualifier.
- Log Vport, Iport, Tj, event counts with timestamps for traceability.
Power & thermal trade-offs
Estimate shunt dissipation P = Irms² · Rshunt and local temperature rise ΔT ≈ P · Rθ,local. Magnetic sensors reduce loss but require offset/temperature compensation and keep-out from magnetics.
Metering parameter card
mΩ range; Kelvin routing; tolerance & TCR
kHz target; fc ≥ 3/Tp (pulse MPS)
µVrms/√Hz; amp input bias & offset
ksps; ≥ 5× pulse rate; synchronized logging
No bias to detect/class/MPS paths
Shunt power estimate (quick)
P ≈ 0.2²·Rshunt
P ≈ 0.6²·Rshunt
P ≈ 1.0²·Rshunt
≈ P · Rθ,local (layout dependent)
PCB Layout & Grounding
Shortest discharge paths & small loops
Place the low-C ESD array adjacent to RJ-45; return to ground before any routing fan-out. Keep the loop area from RJ-45 → ESD → return via as small as possible and avoid plane breaks under differential pairs near the connector.
Shield to chassis strategies
Best CM discharge; risk of LF ground loop.
Moderates LF loop; limited CM surge current.
Filters HF noise, preserves surge path; size L for peak current.
HF tie with DC isolation; good for ESD/EFT, check power-freq leakage.
Separate energy domain from signal domain
Form a clear clamp/chassis domain for GDT/TSS/TVS returns; keep PHY/MCU on a signal domain. Cross-domain currents must pass through controlled components or via fences—never through random copper.
Cross-pair coupling & differential residual control
- Local reference “mini-shelves” under pairs near the connector to stabilize return.
- Keep ESD array within a few millimeters of RJ-45 pins; use paired vias when layer changes are unavoidable.
- Bound parallelism between pairs; use via fences to break capacitive coupling.
Creepage/clearance & via/loop geometry
Respect target level creepage/clearance in the RJ-45 zone; use two ground vias right off the ESD ground pins; prefer short-wide copper to ground over thin traces; avoid U-shaped returns.
Layout hard rules (15-point checklist)
- Place ESD array within a few millimeters of RJ-45; minimize stubs.
- ESD grounds via immediately (prefer dual vias under pins).
- TVS returns into chassis/energy domain—never into signal ground.
- RJ-45 → ESD path has no forks; paired vias when layer change is required.
- Keep pair symmetry (length/coupling) around the ESD location.
- Do not leave shield floating; choose one of Direct/R/L/RC.
- Maintain cascade order: ESD (RJ-45 side) → Magnetics → TVS.
- Isolate energy domain from signal domain with uninterrupted ground fences.
- Limit pair-to-pair parallelism; via fences break capacitive coupling.
- Use ground via walls near dense routing to block coupling.
- Meet creepage/clearance targets with margin in the port zone.
- Use short-wide copper from protector ground pins; avoid thin serpentine lines.
- Prefer “ground first, then route” for return paths.
- Avoid U-shaped or large return loops in the port area.
- Perform a manual loop-area review in addition to DRC.
Validation Matrix & Scripts
Overview & level planning
Build a port-level plan covering ESD, EFT, Surge (CM/DM, L-G/L-L), cross-pair injection, MPS integrity, and thermal/SOA@repetition. Step levels from low to high; switch modes methodically.
Unified acceptance criteria
- Link alive (or auto-recovers within allowed window; no abnormal logs).
- MPS preserved (DC or pulsed signature clearly visible).
- PG/FAULT semantics correct (codes, timing, debounce, hysteresis).
Residual measurement & logging
Use sufficient probe bandwidth; keep ground leads short. Trigger at surge leading edge; capture rise-decay-settle. Log Vpeak, V10–90%, tsettle, event count, MPS state, and PG/FAULT codes.
Test matrix header (copy & fill)
Residual logging (quick table)
Seven-Brand IC Shortlist
Scope: PoE port protection and power-path only. Buck/LLC and downstream converters are intentionally excluded to avoid overlap with sibling pages. Each card explains why the part fits PoE (Detect/Class/MPS safety), followed by concise watch-outs (Ceq, Ileak, Rdyn, PG/FAULT semantics).
Texas Instruments (TI)
High-power PD interface; Class/MPS friendly. Coordinate soft-start with downstream and ensure detection window leakage is within spec.
Multi-port PSE manager enabling per-port power policing consistent with eFuse limits.
48-V eFuse with programmable Ilim/timer/soft-start; handles long-cable + large Cin bring-up.
Reverse current blocking and low drop; set priority path ΔV precisely.
Ultra-low C for Ethernet pairs; preserves eye while clipping residuals.
High-side current + bus voltage; tuning of averaging window to remain MPS-safe.
STMicroelectronics (ST)
802.3bt PD with active bridge & hot-swap MOSFET; robust start-up for large Cin.
Works with PM8805 to implement controlled power stage.
Adjustable current limiting and controlled ramp; suitable as port or sub-rail protector (check V rating).
Low-cap Ethernet-grade arrays; select by Ceq/channels/package & placement.
NXP
Compact PD interface for lower-power PDs; good for legacy/compatible designs (re-validate MPS).
Ultra-low capacitance arrays tailored for Ethernet pairs and automotive Ethernet.
Renesas
Precision voltage/current/power monitor for port policing with stable averaging; I²C control.
Use IntelliTrip/programmable fault timers for surge-rich environments.
onsemi
PD interface portfolio from af to bt; rugged front-end for line transients (re-test MPS integrity).
Very small packages for tight placement near RJ-45; choose by Ceq & residual window.
Microchip
Multi-port PSE controllers with integrated management for power budgeting & policing.
Active rectification lowers drop/heat; re-verify PG/FAULT and inrush consistency.
Melexis
Programmable Hall current sensing with low insertion loss—ideal when shunt heat is a concern.
Cross-Brand Alternatives & Migration
Goal: swap across brands without breaking Detect/Class/MPS or port power budget. Validate with full IEC-4-2/-4/-5 + cross-pair scripts after any change of protector, eFuse/HS, ideal-bridge, or metering.
Low-C ESD Array Migration
Match by Ceq@100 MHz and residual bandwidth rather than nominal standoff voltage. Typical A→B paths: Nexperia PESD2ETH-D/-AX/-100-T ↔ TI TPD4Exx ↔ onsemi ESD9M/ESD9B. Re-verify eye/GbE return loss and preserve MPS (DC & pulsed) visibility.
eFuse / Hot-Swap / Ideal-Diode Migration
First validate SOA @ repetition with surge scripts; then align Ilim/Timer/dVdt and hiccup vs foldback policy. Sequence: ideal bridge priority path ΔV → eFuse power window → metering average. Example: TI TPS2663 ↔ ST STEF12 ↔ Renesas Hotswap families.
PSE/PD & Ideal-Bridge Migration
Keep Detect/Class windows and MPS strategy (DC vs pulsed) consistent. Moving from passive to active bridge requires re-mapping PG/FAULT and re-tuning inrush. Example: TI TPS2373 ↔ ST PM8805 ↔ onsemi NCP109x ↔ Microchip PD70224/PD70288.
Metering (Shunt ↔ Magnetic) Migration
Size bandwidth with fc ≥ 3/Tp where Tp is MPS pulse width; separate peak-hold from average window. Example: Renesas ISL28023 ↔ Melexis MLX91208. Re-scale ADC rate and repeat MPS integrity scripts.
Migration checklist (10 hard checks)
- Ceq@100 MHz within budget; pair symmetry preserved.
- Ileak within detect/classification windows.
- Residual bandwidth not compressing PHY-safe range.
- SOA @ repetition verified (IEC-4-5 stepped levels).
- Ilim/Timer/dVdt aligned to port budget & cable/Cin.
- PG/FAULT semantics and interlocks do not conflict.
- MPS integrity in both DC and pulsed modes.
- Cross-pair injection does not cause link loss.
- Thermal headroom validated (Tj estimate / IR frames).
- 1-for-1 regression when protector/bridge is replaced.
BOM remarks (paste-ready)
- Data-side ESD arrays shall be selected by Ceq@100 MHz and residual bandwidth, not nominal voltage. PESD2ETH / TPD4E / ESD9 families may substitute only if MPS integrity is re-verified.
- Port eFuse/HS shall pass SOA @ repetition; align Ilim/Timer/dVdt with port budget and long-cable + large-Cin start-up scripts.
- Any PD/PSE/ideal-bridge change requires full IEC-4-2/-4/-5 + cross-pair regression and PG/FAULT semantics mapping review.
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FAQ
Only PoE port scope: protectors, eFuse/Hot-Swap, metering, PSE/PD behavior. Each answer keeps Detect/Class/MPS intact and is written for direct engineering use. The text below is exactly mirrored in the JSON-LD.
How do I add surge clamps without breaking IEEE detection/classification on a PD?
Use a cascade: GDT/TSS for energy shedding, then low-Rdyn TVS to reduce residuals, and a low-capacitance ESD array at the data pairs. Keep Ileak inside the detect window and keep Ceq@100 MHz within budget so MPS is not swallowed. Route to ground first, then outward, and re-verify classification with the full port regression suite.
Where should I place the ESD array—RJ-45 side or PHY side—to minimize residuals?
Prefer the RJ-45 side for the shortest discharge loop and symmetric placement per differential pair. Use PHY-side parts only for secondary clamping or internal coupling fixes. Size by Ceq@100 MHz and maintain pair symmetry and length matching. Confirm with eye/return-loss measurements and check that MPS remains visible in both DC and pulsed modes.
What’s the safest way to handle cross-pair lightning events on 4-pair PoE?
Drive common-mode energy into GDT/TSS first, then let low-Rdyn TVS and low-cap ESD handle the remaining differential-mode residuals. Tie shield to chassis at a single point to avoid raising the signal reference. Validate with cross-pair injection using long-cable emulation, confirming link stability, residual limits at the PHY, and the preservation of MPS signatures.
How do eFuse/Hot-Swap current limits interact with PoE power policing?
Define the system power window with PSE or port policing first, then set eFuse Ilim, timer, and dV/dt so Ilim·Vport ≥ Pclass plus margin. Verify SOA at expected repetition, and interlock PG/FAULT with the policing logic to prevent ping-pong. Establish ideal-bridge priority delta-V before finalizing the eFuse window and averaging strategy.
Can a single low-C TVS protect both data and power paths on a PoE port?
Generally no. Data pairs require ultra-low Ceq and controlled residual bandwidth to protect signal integrity and MPS visibility, while the power path needs higher energy handling and broader clamping. Keep roles separate: data-side low-cap ESD arrays plus low-Rdyn TVS for DM residuals, and higher-energy surge parts on the port power rails or ideal-bridge input.
How do I keep MPS intact when I add RC filters for metering?
Choose bandwidth with fc ≥ 3/Tp, where Tp is the MPS pulse width. Separate peak-hold from the averaging window so pulses remain visible while noise is reduced. Place the metering point so it does not bias detect/class channels. Validate both DC and pulsed MPS modes and confirm no false policing events during dynamic loading.
Should the shield go straight to chassis ground or through a component?
Default to a single-point direct tie to chassis to dump common-mode energy quickly. Where front-end sensitivity demands, you can insert an RC, a small inductor, or a resistor, but you must re-measure surge residuals and EMI. Never route large surge currents into signal ground, and keep the return path short and well defined.
What metering bandwidth is “enough” for power budgeting but safe for MPS?
Start with fc ≥ 3/Tp to preserve MPS edges while capturing load dynamics. Add hysteresis and debounce around policing thresholds to avoid chatter. Do not over-widen bandwidth or EFT bursts may trigger false events. Characterize with step loads, confirm pulse detect statistics, and log average versus peak to tune the final measurement windows.
How do I verify that classification is not biased by my protection network?
Measure classification with the full protection stack installed, logging Ileak, equivalent resistance, and Ceq. Then repeat across temperature and replacement candidates. Passing parametrics alone is insufficient; run a complete port regression: IEC-61000-4-2/-4/-5, cross-pair injection, MPS integrity, and link stability under long cables. Record residual waveforms and decision boundaries for traceability.
What’s the right order for GDT/TSS and TVS to reduce residual voltage?
Place GDT/TSS first to shed the bulk of the surge energy, then a low-Rdyn TVS to narrow the residual band, and finally a low-cap ESD array at the data pairs. Keep devices very close to the RJ-45 or magnetics, minimize loop area, and confirm the step-down of residuals with time-aligned port measurements.
How do I stop repeated hiccup trips under long cable or capacitive loads?
Increase soft-start time and control gate slew so the inrush profile fits the port budget. Align Ilim and timer with the power class and consider pre-charge for very large Cin. Add debounce and hysteresis around PG/FAULT. Validate with worst-case cold start, long cable emulation, and thermal monitoring during repeated attempts.
What are common routing mistakes that inflate surge residuals at the PHY?
Locating protectors far from the RJ-45, creating large loops, breaking pair symmetry, routing first then returning to ground, and using discontinuous return paths all raise residuals. Always connect to ground first, minimize loop area, preserve symmetry and length matching, and keep discharge paths short. Verify with residual measurements and eye diagrams.
