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POR / Brown-Out Detector

← Back to: Supervisors & Reset

Focus on accurate POR/BOD thresholds and clean reset timing under fast/slow ramps and pre-bias—deliver a 48-hour loop from limits → timing → validation → BOM; no hot-swap/ideal-diode/watchdog topics here.

What It Solves

Trip accuracy on real boards
Use worst-case synthesis V_trip_wc = V_nom ± (T_ic ⊕ T_div ⊕ T_temp ⊕ ΔV_wiring) so brown-out neither fires early nor late.

Chatter on slow/noisy rails
Guarantee a clean, single reset with Vhys ≥ 3×Vnoise,rms + ΔVripple,max and tRESET,min ≥ 40 ms (raise under slow ramps).

Pre-bias safety
Hold RESET valid with half-powered rails (USB/peripheral back-feed, residual charge). Add RC pre-filter only if required.

Cross-domain fan-out
Prefer open-drain to share RESET across 1.8/3.3/5 V. Use push-pull only when every sink’s VIH level matches.

Design rules (copy-ready)

  • Hysteresis: Vhys ≥ 3×Vnoise,rms + ΔVripple,max (practical floor ≈ 50 mV).
  • Reset minimum width: tRESET,min ≥ 40 ms; increase to 60–80 ms for ≤0.5 V/ms ramps or pre-bias cases.
  • Open-drain rise time target: set trise ≤ tspec ⇒ Rpullup ≤ (tspec/Cload)·k with k≈0.8.
  • Level rule: VOH,OD ≈ VPULLUP ≥ VIH(min) of all sinks; for fan-out > 3, segment pull-ups or buffer.

Quantified example

3.3 V rail; measured Vnoise,rms=10 mV, ΔVripple,max=15 mV ⇒ Vhys ≥ 45 mV (choose 60 mV).
RESET drives three loads (≈ Cload=60 pF), require trise ≤ 1.0 µs ⇒ Rpullup ≤ (1.0e−6 / 60e−12)·0.8 ≈ 13.3 kΩ (select 10 kΩ).
With slow ramp ≤0.5 V/ms, set tRESET,min=60 ms to guarantee a clean boot.

POR overview: accurate thresholds, hysteresis, ramp immunity, pre-bias safety Four capability tiles: Accurate Trip, Hysteresis, Ramp Immunity, Pre-bias Safe with minimalist icons. Accurate Trip Trip stays correct with real-board tolerances Hysteresis Prevents chatter during brown-outs Ramp Immunity Fast or slow ramps still yield clean reset Pre-bias Safe Valid reset with residual charge/back-feed

Architecture & Signal Levels

Comparator + bandgap defines VIT−/VIT+ and Vhys. Choose open-drain (OD) when RESET must fan out across multiple logic domains; use push-pull (PP) only if all sinks share one rail and back-feed risk is zero. Pull-up domain for OD sets VOH; rise time is dominated by Rpullup × Cload.

Level integrity

  • OD level rule: VOH,OD ≈ VPULLUP ≥ max(VIH(min)) of all sinks.
  • PP constraint: VOH,PP fixed to supervisor’s VDD; do not mix 1.8/3.3/5 V sinks.
  • Back-feed guard: add series isolation (47–100 Ω) or use buffer with I/O clamps for cross-domain trees.

Rise time & timing

  • Target trise ≤ tspec (e.g., 1.0 µs) → Rpullup ≤ (tspec/Cload)·k, k≈0.8.
  • Total propagation to sinks ≈ tDelay (IC) + tbuf + twire + trise.
  • For fan-out ≥ 4 or Cload > 80 pF: segment tree or insert a dedicated reset buffer.

Dividers & hysteresis plumbing

  • External sense divider → account for bias/leakage; use Rtop||Rbot ≤ 200 kΩ to limit drift.
  • Hysteresis via feedback/DAC → effective Vhys ≈ Ihys·Rdiv (if external).
  • Keep sense node ≤ 2–5 cm, shield with ground guard to reduce coupled noise.
Aspect Open-Drain (OD) Push-Pull (PP)
Level compatibility Pull-up to any rail (1.8/3.3/5 V) → easy cross-domain Locked to IC VDD; single domain only
Speed / edge Limited by Rpullup·Cload (slower rise) Fast rise/fall; low Cload sensitivity
Fan-out Good with segmentation/buffer; avoid huge Cload Limited by PP driver current and clamps
Back-feed risk Lower (if pull-up domain well chosen) Higher; can source into unpowered sinks
Recommended use Default for reset trees with mixed domains Single-domain, latency-critical paths only

Worked example

Tree with 3 sinks (1.8 V, 3.3 V, 5.0 V). Choose OD pulled to 3.3 V. Estimated total Cload= 20 pF × 3 + 20 pF (trace) ≈ 80 pF.
Requirement: trise ≤ 1.0 µs → R_pullup ≤ (1.0e−6 / 80e−12)·0.8 ≈ 10 kΩ (pick 10 kΩ).
Supervisor tDelay= 12 µs; buffer adds 25 µs; wiring 5 µs → total ≈ 42 µs << tRESET,min (60 ms) ⇒ safe.

Validation script (OD reset tree)

  1. Measure VIH(min) for all sinks at −40/25/85 °C; set pull-up rail so VOH,OD ≥ max(VIH(min)) + 0.2 V margin.
  2. Estimate Cload (pin caps + trace + input clamps). Compute initial Rpullup from target trise.
  3. Scope RESET at each sink: verify trise, overshoot/undershoot < 10% VPULLUP, and no cross-domain back-feed (unpowered sink).
  4. If fan-out ≥ 4 or failure at 85 °C: insert reset buffer (schmitt, OD output) or segment pull-ups per branch.
  5. Re-run with noise injection (20–60 mVpp) and slow ramp (≤0.5 V/ms); confirm no false release.

Common failure signatures & fixes

  • Slow rising RESET (missed boot window) → lower Rpullup, add buffer, or split branches.
  • Back-feed into 1.8 V domain when 3.3 V active → move pull-up to 1.8 V or add level shifter/series isolation.
  • Chatter at receivers → ensure sinks have Schmitt inputs or add RC at receiver; bump Vhys.

BOM remarks (paste as-is)

  • RESET output type: Open-Drain; pull-up rail = system I/O domain (default 3.3 V).
  • Initial Rpullup=10 kΩ for Cload≈80 pF (target trise ≤ 1.0 µs); update after lab.
  • Provide footprint for optional reset buffer (Schmitt, OD output) on branch to 5 V sink.
  • No PP supervisors allowed unless all sinks share same logic rail and back-feed analysis is attached.
Architecture with bandgap reference and open-drain vs push-pull RESET paths Comparator+reference drives OD and PP branches; OD pulled to 3.3 V fans out to 1.8/3.3/5 V (with a level shifter for 5 V); labels show V_PULLUP, R_pullup, C_load, and VIH(min). Comparator with Bandgap Ref defines V_IT− / V_IT+ & V_hys Open-Drain path R_pullup → 3.3 V 1.8 V sink 3.3 V sink 5.0 V sink Level Shifter VIH(min) lines Push-Pull path Single 3.3 V sink Rules: V_OH(OD) ≈ V_PULLUP ≥ max(V_IH(min)). Rise-time ≈ R_pullup × C_load. Segment or buffer for fan-out ≥ 4.

Thresholds & Timing

Definitions

  • VIT−: falling trip (assert RESET).
  • VIT+: rising release (de-assert RESET).
  • Vhys=VIT+−VIT−: hysteresis.
  • tRESET,min: guaranteed minimum reset pulse width.
  • tDelay: threshold crossing → valid RESET edge.
  • tGLITCH: minimum input pulse width not filtered out.

Tolerance synthesis (worst case)

Combine device tolerance (±Tic), divider tolerance (±Tdiv), temperature drift (±Ttemp), and wiring/IR-drop (ΔV). Use conservative linear sum for guards:

V_trip_wc = V_nom ± (T_ic + T_div + T_temp + ΔV_wiring)

RSS can be used for statistical designs, but small-batch/low-risk builds should prefer linear addition.

Copy-ready design rules

  • Hysteresis floor: Vhys ≥ 3·Vnoise,rms + ΔVripple,max (practical floor ≈ 50–80 mV for 3.3 V rails).
  • RESET width: tRESET,min ≥ 40 ms (raise to 60–80 ms with ≤0.5 V/ms ramps or pre-bias).
  • OD rise time: target trise ≤ tspec ⇒ Rpullup ≤ (tspec/Cload)·k (k≈0.8).
  • Level check: VOH,OD ≈ VPULLUP ≥ VIH(min) of all sinks; if fan-out > 3 or Cload>80 pF, segment pull-ups or buffer.

Quantified example (drop-in)

3.3 V rail; measured Vnoise,rms=10 mV, ΔVripple,max=15 mV ⇒ Vhys ≥ 45 mV → choose 60 mV.
RESET drives 3 sinks; estimated Cload=60 pF; require trise ≤ 1.0 µs ⇒ Rpullup ≤ (1.0e−6/60e−12)·0.8 ≈ 13.3 kΩ → select 10 kΩ.
Slow ramp present (0.3–0.5 V/ms) ⇒ set tRESET,min=60 ms; verify at −40/25/85 °C.

Thresholds with hysteresis, guaranteed reset width, and glitch immunity window U(t) curve crossing V_IT− and V_IT+, hysteresis bracket, t_RESET light window, and a rejected glitch shorter than t_GLITCH. V_IT+ V_IT− V_hys t_RESET(min) glitch < t_GLITCH t_Delay →

BOM remarks (paste as-is)

  • POR/BOD hysteresis: ≥ 60 mV (or ≥ 3×V_noise,rms + ΔV_ripple,max, whichever is higher).
  • tRESET,min: ≥ 60 ms with slow-ramp or pre-bias; otherwise ≥ 40 ms.
  • RESET type: Open-drain, pull-up to system I/O domain; initial Rpullup=10 kΩ for Cload≈60 pF (adjust by trise test).
  • Glitch immunity tGLITCH: ≥ 0.5 µs (rejects EMI-like spikes on monitored rail).

Pre-bias & Ramp Immunity

Pre-bias sources & risks

  • Back-feed from peripherals/USB, cable leakage, residual charge on bulk caps.
  • Rail hovering near VIT−/VIT+ causes missed or too-short RESET pulses.
  • Symptoms: intermittent boot, inconsistent bootloader entry, random lockups.

Mitigation strategy (apply in order)

  1. Increase tRESET,min by +20–40 ms when slow ramps or V_pre are present.
  2. RC pre-filter on sense path or RESET (start R=22 kΩ, C=47 nF; tune via t=R·C and threshold margin).
  3. Increase Vhys if 1) and 2) are insufficient; re-check noise/ripple budget.
  4. Keep RESET low until rail is above VIT+ and stable for Δt (≥ tDelay + oscillator/PLL lock).

Validation matrix (ramp & pre-bias)

Ramp (V/ms) Noise (mVpp) V_pre (×V_nom) Temp (°C) Criteria Result Notes
0.05 20 0.5 −40 / 25 / 85 No chatter; t_RESET ≥ spec; no missed reset □ Pass □ Fail If fail → +20–40 ms t_RESET, then add RC
0.5 40 0.3 −40 / 25 / 85 Same as above □ Pass □ Fail Check V_hys margin
5 60 0.8 −40 / 25 / 85 Same as above □ Pass □ Fail Fast slew + large pre-bias corner
Pre-bias and ramp-rate immunity: ensuring valid reset under slow ramps and residual voltage Two clean ramps (fast/slow) and one pre-biased ramp with a step; RESET trajectory aligned with a minimum t_RESET window and release after V_IT+ stability. V_IT+ Fast ramp Slow ramp V_pre t_RESET(min) Hold RESET until stable above V_IT+

Actionable notes

  • If failure at V_pre=0.5×V_nom with 0.05 V/ms: first increase tRESET,min by +20–40 ms, then add RC pre-filter.
  • Re-measure Vnoise,rms and ΔVripple,max after layout/PSU changes—update Vhys budget.
  • Document the worst-case passing corner; attach plots to ECO for any cross-brand supervisor swap.

BOM remarks (paste as-is)

  • tRESET,min = ≥ 60 ms (pre-bias/ramp-tested); threshold hysteresis per noise/ripple rule.
  • Include RC pre-filter option footprint (e.g., R 0603, C 0603) populated as required by validation.
  • Any alternative supervisor must pass the ramp & pre-bias matrix at −40/25/85 °C; attach results to DMR.

Integration & Fan-out

Design intent

  • Open-drain (OD) first when RESET must cross 1.8/3.3/5 V domains; pull up to the common I/O rail.
  • For fan-out > 3 or Cload > 80 pF use segmented pull-ups and/or a reset buffer.
  • Topology: star or short tree; avoid long daisy-chains and shared-impedance traps.
  • Power-good/clock order: power stable → release RESET → oscillator/PLL lock.

Quantitative rules

  • Rpullup seed: 4.7–22 kΩ (start 10 kΩ), refine by trise and Cload.
  • Rise-time target: trise ≤ tspec (typ. 0.5–1.0 µs) ⇒ Rpullup ≤ (tspec/Cload)·k, k≈0.8.
  • Level rule: VOH,OD ≈ VPULLUP ≥ max(VIH(min)) + 0.2 V margin; otherwise use a level shifter.
  • Delay budget: tprop,total = tDelay(IC) + tbuf + twire + trise ⟂ tRESET,min.

Reset storm prevention

  • Add debounce/blanking so consecutive triggers are spaced by at least tDelay + trise + clock-stability margin.
  • For PP outputs in mixed rails, add series isolation (47–100 Ω) or use OD-buffer to prevent back-feed.

Worked fan-out example

Three domains (1.8/3.3/5.0 V). Choose OD pulled to 3.3 V. Estimated Cload= 20 pF×3 + 20 pF(trace)= 80 pF.
Target trise ≤ 1.0 µs ⇒ Rpullup ≤ (1.0e−6 / 80e−12)·0.8 ≈ 10 kΩ → select 10 kΩ on the trunk.
Branch to 5 V uses a Schmitt buffer/level shifter; each branch keeps Cseg ≤ 40–60 pF to maintain edges.

Open-drain RESET fan-out across 1.8/3.3/5 V domains with segmented pull-ups One OD source drives three domains; 5 V branch via level shifter. Labels show segmented pull-ups, equivalent C_load and per-branch t_prop. POR / BOD OD output R_pullup → 3.3 V 1.8 V sinks (seg. pull-up) 3.3 V sinks Level Shifter 5.0 V sinks C_seg ≤ 40–60 pF t_prop = t_Delay + t_buf + t_wire + t_rise Rule of thumb: choose OD, segment when fan-out ≥ 4 or C_load ≥ 80–100 pF, and shift levels to any higher-V domain.

BOM remarks (paste as-is)

  • RESET output: Open-Drain; pull-up rail = common I/O domain (default 3.3 V).
  • Initial Rpullup=10 kΩ for Cload≈80 pF (target trise ≤ 1.0 µs); segment branches as needed.
  • 5 V path requires level shifter or Schmitt buffer; PP is prohibited across mixed rails.
  • Add debounce/blanking to prevent reset storms under noisy or bouncing rails.

Validation

Ramp sweep

  • Programmable supply at 0.05 / 0.5 / 5 V/ms. Record VIT−/VIT+, tRESET, chatter flag.
  • Pass: no chatter at ≤0.5 V/ms; tRESET ≥ spec (60 ms recommended for slow ramps).

Glitch injection

  • Add 50–200 mV pulses, width 0.2–5 µs, on the monitored rail.
  • Measure tGLITCH threshold (shortest non-trigger). Pass target: ≥ 1 µs.

Pre-bias scenarios

  • Pre-charge Cload to Vpre=0.3/0.5/0.8×Vnom. Power up/down and verify valid RESET.
  • Pass: no missed/short reset; tRESET ≥ tRESET,min (≥ 60 ms recommended).

Temperature drift

  • −40 / 25 / 85 °C. Track VIT±, tDelay, tRESET variation.
  • Pass: VIT± stay within error budget; no early/late trip across corners.

Fan-out & cross-domain

  • n = 1/3/6 branches. At each sink measure trise/tfall, VIH compliance, false-trigger risk.
  • Cross-domain: ensure unpowered domains are not back-fed; PP only in single-rail paths.

Pass/fail thresholds (revise per device limits)

Item Target Notes
t_RESET ≥ 40 ms (≥ 60 ms for slow ramps/pre-bias) Covers worst-case propagation and clock start-up
V_hys ≥ 50 mV or ≥ 3×V_noise,rms + ΔV_ripple,max Choose higher of the two
t_GLITCH ≥ 1 µs Rejects EMI-like spikes
Slow-ramp chatter None at ≤ 0.5 V/ms Scope across temperature corners
Fan-out All sinks meet VIH and t_rise ≤ spec Segment branches if C_load ≥ 80–100 pF

Result logging template (fields)

scenario, params, T(°C), V_IT−(V), V_IT+(V), t_RESET(ms), t_GLITCH(µs), t_rise(µs), fanout(n), pass/fail, notes

Validation matrix for POR: ramp, glitch, pre-bias, temperature, fan-out Five-column matrix of validation cards: Ramp, Glitch, Pre-bias, Temp, Fan-out with pass (✓) and attention (!) icons and key criteria. Ramp Glitch Pre-bias Temp Fan-out 0.05 V/ms No chatter; t_RESET ≥ 60 ms ✓ 0.5 V/ms No chatter; thresholds repeatable ✓ 5 V/ms Watch overshoot/undershoot ! t_GLITCH ≥ 1 µs Shortest non-trigger pulse ✓ 0.2–0.5 µs Should be rejected ! V_pre = 0.3× Valid reset; no miss ✓ V_pre = 0.5× t_RESET ≥ 60 ms ✓ V_pre = 0.8× Hold RESET until stable ! −40 °C No early trip ✓ +85 °C No missed trip ✓ n = 3 t_rise ≤ spec at all sinks ✓ n = 6 Segment/Buffer required !

Corrective action order

  1. Slow ramp or pre-bias fails → increase tRESET,min by +20–40 ms.
  2. Still failing → add RC pre-filter (start R=22 kΩ, C=47 nF) on sense/RESET as appropriate.
  3. Noise-induced chatter → increase Vhys per 3×V_noise,rms + ΔV_ripple,max.
  4. Fan-out/edge failure → segment pull-ups or add Schmitt reset buffer; keep Cseg ≤ 40–60 pF.

BOM remarks (paste as-is)

  • Validation required on Ramp/Glitch/Pre-bias/Temp/Fan-out matrix; archive all PASS plots in DMR.
  • Targets: t_GLITCH ≥ 1 µs; t_RESET,min ≥ 60 ms for slow/pre-bias cases.
  • Fan-out ≥ 4 or Cload ≥ 80 pF: segmented pull-ups or reset buffer must be populated.
  • Cross-domain: no back-feed into unpowered rails; PP allowed only in single-rail branches.

Cross-Brand IC Mapping (Seven Vendors)

Scope

  • Only PURPOSE: POR/Brown-Out/µP Supervisors (single-rail, windowed, multi-rail, watchdog-combo when reset role).
  • Exclude hot-swap/eFuse/ideal-diode/PMICs unless the device is explicitly the reset source (e.g., NXP SBC).

Non-negotiable guardrails

  • Output type must remain OD unless the reset tree is re-designed; PP across mixed rails is disallowed.
  • Keep delay tier (e.g., 40–80 ms) and hysteresis class (≥ 3×Vnoise,rms + ΔVripple,max or ≥ 50–60 mV) consistent.
  • Automotive builds: AEC-Q100 only (TI “-Q1”, onsemi “NCV”, Renesas A-grade, NXP SBC automotive lines).

Texas Instruments

Best coverage for precision thresholds, low-Iq, and multi-rail sequencing. Abundant OD variants and automotive “-Q1”.

STMicroelectronics

Mature µP reset families (STM70x/80x/100x) with tiny packages, broad thresholds and polarity/delay options.

NXP

Automotive SBCs (MC3390x/MC3391x/MC33905/7/8/10) provide built-in POR + diagnostics via SPI; use when the platform already adopts an NXP SBC power tree.

Renesas

Precision supervisors (ISL880xx/8801x/8803x/8806x) with stable temp drift, clean delay classes, and OD outputs.

onsemi

Commodity to automotive (NCV) lines (NCP30x/31x/303–306) with many thresholds; robust, cost-effective second-source angle.

Microchip

Wide legacy and new families (MCP809/810/811, MCP1316/18/132x) ideal for drop-in and low-Iq battery rails.

Melexis

Use internal POR/BOD of Melexis host (e.g., MLX8111x/MLX8xxx). External system supervisor must come from the other six brands.

Supervisor families and why/when to choose

Brand Family / Example PNs Why choose (engineering reasons) Output / Delay Automotive
TI TPS3890/3895(-Q1); TPS3808; TPS3702/3703; TPS386000/1; TPS3851(-Q1) Tight trip (±1% typ), low Iq for battery rails; windowed OV/UV immunity (TPS3702/3) for slow/dirty ramps; 4-rail sequencing (TPS386000/1) for FPGA/SoC; watchdog combo (TPS3851). OD first; broad delay SKUs (ms–s) “-Q1” options
ST STM706/708; STM809/810/811/812; STM1001/100x; STM6719/6830 Proven µP reset lines with many thresholds/polarities; tiny SOT-23/SC70; watchdog or dual-rail options without moving to PMIC. OD/PP variants; fixed/programmable delays Selected AEC parts
NXP MC33905/MC33907/MC33908/MC33910 (SBC with POR/WDT) When the platform already uses an NXP automotive SBC: integrated POR source, SPI diagnostics, fault logging; simplifies homologation. RESET from SBC; delay via config AEC-Q100 SBC
Renesas ISL88002/003/011/012/031; ISL88063/067 Precision thresholds with low temp drift; flexible delay/polarity; stable over corners for industrial/automotive rails. OD focus; clean ms-class delays A-grade selections
onsemi NCP300/301/302; NCP303–306; NCV300/301/302 (auto) Robust, cost-effective second source; many fixed thresholds; NCV line for automotive; PP variants available when single-rail. OD/PP; fixed delays NCV series
Microchip MCP809/810/811; MCP101/102/103; MCP1316/1318/1320/1321 Drop-in legacy coverage and low-Iq options; newer MCP131x offer longer guaranteed reset and better noise immunity; tiny packages. OD focus; fixed/long delay SKUs Selected AEC parts
Melexis Internal POR/BOD within MLX8111x, MLX8xxx lighting/LIN MCUs (use as local reset only) When the host is a Melexis controller: rely on integrated POR/BOD locally; use an external system supervisor from the other six brands. Device-integrated AEC-Q100 devices

Tip: keep OD output, delay tier, and hysteresis class consistent when substituting.

Closest-fit cross-brand substitutions

From To (alt) Keep identical Re-validate
TI TPS3890-Q1 / TPS3895-Q1 onsemi NCV301 / NCV302 (matching threshold/delay) OD polarity; threshold code; delay tier (40–80 ms) t_GLITCH ≥ 1 µs; V_hys vs noise; slow-ramp & pre-bias
TI TPS3702 (windowed) Renesas ISL88031 (windowed variant) Window width; output type R_pullup vs C_load; fan-out timing
ST STM809/810 Microchip MCP809/810 Polarity; delay code; threshold selection Release timing with oscillator/PLL lock
TI TPS386000 (4-rail supervisor) NXP MC33908 SBC (systemic swap) PG/RESET semantics mapped to system SPI fault logging; full sequencing matrix

BOM remarks (paste as-is)

  • Supervisor brand limited to TI / ST / NXP / Renesas / onsemi / Microchip / Melexis. If Melexis host is used, local reset = internal POR/BOD; external system supervisor from the other six brands.
  • Output type = OD; pull-up to I/O domain; t_RESET ≥ 60 ms for slow-ramp / pre-bias scenarios; hysteresis per noise rule.
  • Automotive: AEC-Q100 only (TI -Q1 / onsemi NCV / Renesas A-grade / NXP SBC lines). Attach the Validation Matrix plots to DMR.
  • Cross-brand substitutions must keep threshold code, polarity, delay tier, and OD output; otherwise re-run the full validation set.

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BOM Remarks & Procurement Hooks

  • RESET must be open-drain with ≥10 kΩ pull-up to the host I/O rail; push-pull only if all sinks are level-compatible.
  • t_RESET ≥ 40 ms, t_GLITCH ≥ 1 µs, V_hys ≥ 50 mV (unless validation proves lower values safe).
  • Validate slow-ramp (≤0.5 V/ms) and pre-bias conditions; document worst-case trip and keep ≥20% margin.
  • For fan-out >3, add a buffer or segmented pull-ups; avoid cross-domain back-feed.
  • Alternatives limited to TI / ST / NXP / Renesas / onsemi / Microchip / Melexis; update the test report before release.

Engineering checks: confirm VOH ≥ VIH(min) at the farthest sink; scope rise time vs. Cload; re-run Ramp/Glitch/Pre-bias/Temp/Fan-out when swapping brands or output types.

BOM checklist for POR thresholds and reset timing Two-column checklist: left shows timing/threshold requirements; right shows substitution boundaries and validation gates. POR BOM Checklist Timing & Thresholds t_RESET ≥ 40 ms (slow ramps safe) t_GLITCH ≥ 1 µs (injection-tested) V_hys ≥ 50 mV or ≥ 3×V_noise,rms + ΔV_ripple Open-drain + ≥10 kΩ pull-up to I/O rail Validate ≤0.5 V/ms ramps & pre-bias Keep ≥20% margin to worst-case trip Fan-out >3 → buffer or segmented pull-ups Substitution Boundaries Seven Brands TI · ST · NXP · Renesas onsemi · Microchip · Melexis Keep Output=OD, Delay tier, Hysteresis class Automotive builds: AEC-Q100 only Re-run Ramp / Glitch / Pre-bias / Temp / Fan-out Update the validation report before release

Frequently Asked Questions

Why do measured trip points differ from datasheet values on my board?

Board-level trip shifts come from stacked tolerances and losses: supervisor threshold tolerance, divider tolerance, bandgap drift, trace drops, and temperature. Measure at the supervisor pin, not the regulator output. Budget the composite worst case and keep at least 20% margin between the measured trip and the minimum operating rail.

How long should t_RESET be to guarantee a clean boot under slow ramps?

Use ≥40 ms as a conservative baseline, then tune from ramp testing. With ramps ≤0.5 V/ms, longer resets ensure digital domains and clocks settle before release. If PLL lock or PMIC sequencing is slow, pick the next delay tier and confirm no chatter across the entire temperature range.

What hysteresis is enough to stop chatter on brown-outs?

Size hysteresis so it exceeds noise and ripple by design: V_hys ≥ 3×V_noise,rms + ΔV_ripple,max. For typical 3.3 V rails, 50–80 mV works well. Verify with injected ripple and narrow ramps. If your rail is particularly noisy, increase hysteresis or add front-end RC filtering.

How do I test glitch immunity without over-stressing the rail?

Inject controlled perturbations near the supervisor pin: 50–200 mV pulses with 0.2–5 µs width through a coupling network that limits current. Start at the lowest energy, increase gradually, and scope both rail and RESET. Pass criteria: no false release and t_RESET meets the guaranteed minimum.

Why does pre-bias make the POR miss or shorten the reset pulse?

Residual charge from peripherals, USB sources, or large capacitors can sit the rail between V_IT− and V_IT+. The supervisor may never see a true crossing or may release early. Increase guaranteed t_RESET, add hysteresis or RC pre-filter, and hold RESET low until the rail is demonstrably stable.

Open-drain or push-pull RESET—when should I use which?

Prefer open-drain when fan-out spans multiple logic domains or unknown sinks. It avoids back-feed and lets you pull up to a neutral I/O rail. Use push-pull only when every sink is level-compatible and the reset tree is strictly single-domain. Re-validate rise/fall timing when switching types.

How many loads can I fan-out before I must add a buffer?

Sum input capacitances and routing to estimate C_load. If the required R_pullup to meet t_rise kills noise margin, or if fan-out exceeds three sinks, add a small buffer or segment the pull-ups by domain. Always scope the farthest sink to confirm rise time and logic-high level.

Will temperature drift break my brown-out margin?

Yes, drift stacks with divider tolerance and trace drop. Characterize V_IT± over −40…+85 °C and compute worst-case trip against the minimum system operating voltage. Keep ≥20% margin after adding thermal drift, noise, and ripple. If margin is thin, raise hysteresis or shift the threshold.

Can I pull up RESET to a domain different from the monitored rail?

Yes—this is a key benefit of open-drain. Pull up to the host I/O domain as long as V_OH meets the sinks’ V_IH(min) and there is no back-feed path into the monitored rail. Avoid push-pull in mixed-domain trees unless you add proper level shifting and isolation.

What’s a safe minimal hysteresis for battery-powered designs?

Start with 50 mV on 3.3 V and scale with measured noise: V_hys ≥ 3×V_noise,rms + ΔV_ripple,max. Battery rails with DCDC ripple or long harnesses may need 60–100 mV. Validate with worst-case load transients and low-temperature conditions where ESR rises and ripple increases.

How do I avoid repeated resets during power-down?

Either extend the guaranteed reset width so the system stays held low until power is truly gone, or add a small pre-filter/hysteresis to prevent multiple crossings. Coordinate with clock/PMIC sequencing: release RESET only after the rail and reference domains pass stability criteria.

Which parameters must match when swapping brands in small batches?

Keep the threshold code, hysteresis class, t_RESET tier, output type (OD), and—if applicable—AEC-Q100 grade unchanged. Compare temperature drift and Iq to ensure your margin holds. Any deviation requires re-running ramp, glitch, pre-bias, temperature, and fan-out tests before release.

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