Force a negative Vout→Vin with a source and series resistor, then sweep current to the device’s limit. Pass if Irev stays below the spec and the back-to-back FET body diode never conducts. Add blanking and hysteresis on the reverse comparator. See #reverse-block.

ORing excels at seamless sharing and back-feed immunity with minimal control overhead. Power-mux ICs add policy (priority, brownout rules) and timing control for cleaner handoffs. Choose mux when sources change priority or have PDO events; choose ORing for always-on dual feeds. See #priority.

Start with 1–5 µs measured at the FET gates. Confirm no simultaneous conduction on scope current probes. Lengthen if cabling is long or gate charge is large; shorten if ΔVout dips. Always mask PG/RESET around the handoff. Validate at temperature and load extremes. See #switchover.

Use C ≈ 2·P·t / (Vhi² − Vlo²). Verify ESR ripple I_rms·ESR and transient ΔV = I·ESL/dt. If ΔVout margin is tight, add a small post-path polymer and place the bulk near the load. Log actual hold-time on bench. See #holdup.

Enforce non-overlap, ensure ideal-diode direction is correct, and add a small output series R or active ideal diode toward the load if needed. Disable synchronous rectification briefly on downstream bucks. Confirm zero negative current at Vout during the transition. See #switchover.

Industrial 24 V often needs 20–50 ms dips at 18–20 V; automotive cranking can sag to 6–7 V for tens of milliseconds. Hold up post-path rails, not just VBAT/VBUS. Validate with scripted profiles, not DC steps. Thermal-check the holdup path. See #holdup.

Start with 10–50 ms debounce on slow sources, 2–5 ms on regulated supplies. Dwell of 100–200 ms after a switch avoids ping-pong. Set hysteresis ≥ 3× observed ripple at the sense node. Log event counts to verify stability over hours. See #priority.

Limit current at the path that charges the largest downstream bulk (usually post-path). For sensitive upstream sources, add a gentle soft-charge there as well. Keep the sense resistor Kelvin-routed. Confirm peak and average inrush against connector and fuse limits. See #protect.

Comparators should trip the gate path first; ADC/PMBus records the event ID, timestamp, and channels. Use a pre-trigger circular buffer (≥ 5× dead-time) and spike rejection to avoid false latches. Export CSV for A/B comparisons. See #protect.

Add an RC at the sense amp output sized above switching edge energy, use digital median/decimation on telemetry, and keep sense pairs far from the SW polygon. Place a via-fence around noisy copper. Check with near-field probe and before/after logs. See #layout, #protect.

Route differential sense traces directly from the shunt pads, tightly coupled, away from SW edges and returns. Do not share ground between sense and power returns. Land at the ADC/amp with symmetric entry and guard copper if space allows. See #layout.

Place both at the ringing node with the shortest possible loop—lead length comparable to the device pad spacing. Start with C that halves the overshoot and R that critically damps. Measure dissipation at max duty and ambient. See #layout.

On PDO change, reevaluate the voltage-qualified rule with a small dwell before switching. Mask PG until Vout is inside the safe band. Verify non-overlap and ΔVout across fast and slow PDO transitions. Log event IDs per change. See #priority.

Light-load PFM, long cables, cold/hot extremes, adapter yank, forced reverse, and downstream buck ringing with spread-spectrum on/off. Require three consecutive passes per scenario and correlate events to waveforms. Track drift over soak time. See #validation.

ΔVout within downstream UVLO margin, no shoot-through, I_rev below limit, t_dead inside window, and correct event logging. Each scenario must pass three consecutive runs at temperature corners. Archive scope captures and CSV with configuration hashes. See #validation.