Precision Current/Power Sense

Precision sensing in the power path means wide common-mode range, high rejection (CMRR/PSRR + PWM immunity), true bidirectionality (incl. back-charge), low drift, and energy metrics wired to PG/FAULT/ALERT. Implementation flow: Rsense selection → front-end (INA/CSA or ΣΔ) → bandwidth & filtering → bidirectional thresholds → calibration & temperature mapping → layout (Kelvin/guard) & validation.

High-side INA/CSA: wide V_CM, high CMRR/PSRR, input clamps; avoid reverse-current saturation — best partner to eFuse/Hot-Swap. Low-side: lowest cost but ground noise sensitive; use only when return integrity is guaranteed. Isolated (ISO-amp / isolated ΣΔ): bandwidth/linearity vs latency/CMTI & isolated bias constraints. ΣΔ path: place PWM base into Sinc^N notches; choose OSR for ENOB vs delay. Magnetic: zero burden, larger drift/non-linearity; great for protection adjunct or coarse metering.

Target a full-scale burden of 10–50 mV. Pick R_s=V_FS/I_FS, then verify P=I²R_s for continuous thermals and E_pulse=∫I²R_sdt for surge windows. Control drift via low-TCR alloy shunts and symmetric copper for isothermal behavior. Kelvin pads are mandatory; keep dual-polarity headroom for bidirectional range.

1. Define I_FS, I_pk(t), efficiency and min resolution → select V_FS in 10–50 mV band.
2. Compute R_s, check P_cont vs package rating and θ_JA.
3. Integrate I²R_s over pulse window → verify E_pulse with derating.
4. Pick TCR & tolerance to meet total error; set symmetric copper for isothermal flow.
5. Route true Kelvin sense traces; keep current path separate from sense path.

• Chasing resolution with high R → poor efficiency/overheat.
• Ignoring pulse rating & derating curves.
• Wrong Kelvin routing; mixing sense and current pads.
• Confusing tolerance with stability; TCU not characterized.

Set G from V_FS and ADC range, then ensure BW ≥ 5–10× signal content. Suppress PWM ripple via front-RC, phase-aligned sampling, or ΣΔ Sinc^N notches. Verify V_CM, input clamps, output swing, and reverse-current behavior. Budget error: Err_Vos≈Vos/(G·V_FS).

• Kelvin to shunt; short, symmetric diff routing; single-point return.
• Keep PWM switch loops orthogonal to sense; minimize input capacitance mismatch.
• Place input clamps close; verify recovery time under overload.

1. Bode/step under various loads; measure phase margin.
2. PWM injection (duty sweep) → V_ripple in mVpp & dB.
3. Negative current step; overload & recovery time; clamp behavior.
4. ADC S/H kickback with target sampling phase; aliasing check.

Choose between isolated amplifier and isolated ΣΔ by trading linearity, bandwidth, latency, CMTI, and isolated power noise. Align group delay with eFuse/hot-swap timing so metering and protection remain stable under high common-mode and long return loops.

• ISO-amp → ADC: check swing, output drive, S/H kickback, anti-alias RC.
• ΣΔ Bitstream → MCU/PMBus: clock integrity, jitter, DRDY timing, metastability protection.

Pitfalls: isolated supply ripple injection; insufficient CMTI; mistaking analog BW for effective digital BW; delay not budgeted for loop stability.

1. CMTI step tests; isolated PSRR sweep.
2. Group delay vs PG/FAULT timing alignment.
3. Temperature drift & post-surge zero shift checks.

Use OSR and Sinc^N to notch the PWM base/harmonics while keeping an effective bandwidth that supports power policing. Budget ENOB, RMS noise, and overload recovery so alerts remain stable and timely.

• Pick Sinc order for notch depth vs group delay; window/EMA for stable power averaging.
• Time constants must match PG/FAULT semantics; avoid late alerts or chatter.

Pitfalls: notch misaligned to PWM; assuming nominal OSR equals true BW; slow overload recovery; clock coupling into power stage.

Standardize semantics: PG=operable, ALERT=recoverable, FAULT=protective action. Define I⁺/I⁻ and P_avg/P_peak thresholds with hysteresis and deglitch windows; integrate energy E=Σ(P·Δt) to support time/energy policing. Lock thresholds to eFuse I_trip/timers and ideal-diode ΔV_trip to avoid ping-pong.

Achieve 1–2%FS across temp with one/two-point production calibration, NVM-stored coefficients (with CRC), and online temperature compensation combining shunt TCR and AFE drift. Minimize thermal EMF by symmetric copper and true Kelvin routing.

{
  "cal_version": "v1",
  "timestamp": "UTC-ISO8601",
  "offset_code": 0,
  "gain_code": 1.0000,
  "tcr_shunt_ppm": 25,
  "drift_afe_uV_per_C": 0.5,
  "temp_model": "linear|piecewise",
  "temp_breakpoints_C": [-20, 25, 85],
  "gain_table": [0.998, 1.000, 1.004],
  "offset_table_uV": [-8, 0, 10],
  "crc32": "0x--------"
}

• Two-point at production; verify residuals and across-temp drift.
• Write NVM with CRC & version; log timestamp and station ID.
• Online compensation with board/IC temperature; clamp extrapolation.
• Thermal EMF audit (IR camera, isothermal layout) and Kelvin routing.

Guarantee electrical accuracy with geometry: enforce true Kelvin (+K/−K straight to AFE), short parallel differential, guard/“moat” ground to split power return, distance from switching nodes, symmetric copper for low thermal-EMF, and disciplined analog/digital partitioning.

• Kelvin leads: +K/−K run independently to the AFE pins; do not share power copper; avoid vias unless paired and symmetric.
• Short, parallel, same layer: differential pair with matched length and environment; minimize stubs; place anti-alias RC at the AFE end.
• Connector mapping: pinout aligns with reference plane and return stitching to prevent cross-zone currents.

• Moat/guard ground: separate power return loop from measurement/AFE island; use a single controlled bridge for reference continuity.
• Three-zone rule: power / analog / digital; crossings only through defined bridges or CM filters; no uncontrolled return across the sense pair.
• ESD/TVS returns: shortest loop to chassis/return without traversing sensitive nodes.

• Symmetric copper & isothermal islands: equalize temperature around Rsense; keep heat sources away from +K/−K routes.
• Via fields: balanced pairs near shunt pads for heat spreading without skewing Kelvin impedance.
• SW node clearance: maintain keep-out around switching edges; add “quiet” reference strip above/below the sense pair if needed.

Execute end-to-end validation covering DC linearity, steps/saturation/recovery, PWM injection suppression, negative current/regen, energy integration error, across-temp/aging, and EMI/common-mode injection with explicit acceptance criteria and reproducible scripts.

• DC linearity/gain/offset at −40/25/85/105°C and 1/10/50/100% FS.
• Step/pulse tests: saturation entry & recovery, overshoot limits.
• PWM injection sweep: residual vs frequency to form suppression curve.
• Negative current/regen sign stability and false-trigger rate.
• Energy integration error vs reference under steady & dynamic load.
• EMI/CMTI robustness and event logging; aging drift delta.

uuid,temp_C,vin_V,load_A,waveform,duty,freq_Hz,sample_rate_sps,window_ms,osr,sinc_order,notch_align,gain,offset_uV,linearity_pctFS,enob_bits,residual_uV,recovery_ms,energy_meas_J,energy_ref_J,energy_err_pct,cmti_flag,emi_flag,alert_count,fault_count,pass_fail,notes

Shortlist focuses on production-proven parts for precision current/power sensing. Each pick states why it’s favored (CMRR, drift, PWM rejection, bandwidth, isolation, or metering features) and key caveats (V_CM, latency, layout/Kelvin, thermal).

Priority order: architecture/common-mode scope → accuracy & drift → bandwidth & PWM suppression → interface/pin-map. For ΣΔ↔analog front-ends, recompute OSR/Sinc and re-align notch vs PWM base; adjust ALERT deglitch to match new latency. For Rsense, preserve R·I_max (10–50 mV V_FS) and pulse power.

• Architecture/Common-Mode: V_CM min/max, bidirectional range, isolation & CMTI; ΔV_trip and ideal-diode interactions.
• Accuracy/Drift: Vos, Vos/°C, GainErr, INL/ENOB (ΣΔ), calibration method and NVM format.
• Dynamics: −3 dB BW, step recovery, PWM suppression depth at target frequency; ΣΔ latency budget.
• Semantics: ALERT/FAULT/PG levels, deglitch & latch behavior; energy registers scaling.
• Mechanicals/Thermal: Pin-map, package θ_JA, Rsense footprint & TCR, Kelvin pad compatibility.

BOM Remark — Precision Sense Chain
1) Architecture & VCM: Replacement must support VCM ≥ __ V, bidirectional current range ≥ __ A, CMTI ≥ __ kV/μs (if isolated).
2) Accuracy: Vos ≤ __ μV, Vos/°C ≤ __ μV/°C, GainErr ≤ __ %, ENOB ≥ __ bits (ΣΔ).
3) Dynamics: BW ≥ __ kHz, PWM suppression ≥ __ dB @ __ kHz; ΣΔ OSR/Sinc = __ / __; latency ≤ __ μs.
4) Semantics: ALERT deglitch = __ samples, latch = __ ms; energy registers scaling = __.
5) Shunt: R = __ mΩ, I_max = __ A (V_FS ~ 10–50 mV), pulse power ≥ __ W; TCR ≤ __ ppm/°C; footprint & Kelvin pads compatible.

Keep Rsense burden near 10–50 mV, align bandwidth and filtering to your PWM spectrum, and map ALERT semantics to PG/FAULT without ambiguity.