Protection Set for Buck / Boost / Buck-Boost Regulators

Cycle-by-cycle trips at the next PWM decision, catching sub-millisecond surges to protect FETs and magnetics—best for spiky or fault-prone loads. Average limit filters ripple to preserve throughput and reduce nuisance trips—good for motors/LEDs. Many controllers combine both: set average near thermal safe current, cycle limit above ripple crest.

Validate at VIN_max/hot with square-wave steps; log t_trip, duty loss.

Peak sensing reacts earlier but is vulnerable to leading-edge spikes; blanking and RC filtering are mandatory. Valley sensing inherently ignores that spike but reacts one half-ripple later, so thresholds must include ripple amplitude. On noisy boards, start with valley plus modest slope compensation; migrate to peak only after measuring spike width.

Tune t_blank ≈ 3–5× spike width; verify across temp.

A fast-short path bypasses the slow error amp: comparator → strong gate pull-down → SW clamp. Keep the blanking window short enough not to mask the first catastrophic edge, yet long enough to ignore switch spikes. For MHz bucks, start ~100–150 ns and confirm turn-off within ~1–3 µs.

Measure detect-to-gate-off delay and overshoot at VIN_max/hot.

Clamp limits overshoot with a bleed or clamp FET and keeps the rail alive—ideal for analog rails, but it dissipates heat and can modulate ripple. Full shutdown removes drive and is safest for digital/logic rails; it causes service interruption but avoids thermal stress during faults.

Set clamp only for small overshoot; otherwise prefer shutdown.

Ride-through holds regulation through brief sags using output capacitance and deglitching—good for UX continuity. Restart drops the rail and re-ramps, clearing latched faults but resetting downstream devices. Choose ride-through for digital loads with hold-up; use restart when safety or sequencing requires a clean power-on.

Size deglitch for worst sag; confirm PG behavior.

Start from V_out=V_ref(1+R_top/R_bot). Propagate E96 tolerances, reference accuracy, and FB bias/leakage to the threshold. Keep the FB node impedance ≤100 kΩ to limit leakage error. Target ±1–2% at the output, and verify across temperature and PCB contamination scenarios.

Guardband with worst-case V_ref, bias, and temp drift.

Set t_HICCUP about 4–8× t_SS to limit average power in a hard short and allow input caps to recharge. Verify thermal duty by measuring hotspot temperature over repeated cycles. If temperature creeps upward, extend off-time or back-off retries to keep silicon and magnetics within limits.

Log duty vs temperature; cap worst-case retries.

Latch keeps the rail off until a manual clear via EN/RESET or power cycle—preferred for safety-critical paths. Document the minimum EN low pulse and any timing needed for supervisors. Expose FAULT/PG pins and log the cause to aid field service and certification audits.

Provide onsite clear path and visible FAULT indication.

When Vout is pre-charged, prevent reverse discharge through body diodes. Use an ideal-diode ORing FET or controller, and disable active discharge during faults. Verify startup with pre-bias at various levels and ensure SW/node current never flows into the load on enable.

Probe SW/body-diode current; confirm no undershoot.

Fold-back reduces current with temperature, preserving partial service but lowering capability; good for fan failures or transient heat. Hard trips shut down quickly to protect hardware and may require manual recovery. In sealed boxes, prefer fold-back with adequate hysteresis; log T_trip and recovery time distributions.

Set ΔT_hyst ≥ ramp×latency; run soak tests.

Hiccup toggles PG with each attempt; auto-retry keeps PG low until stable; latch holds PG low until manual clear. FAULT is usually open-drain and can be wire-ORed. Debounce PG and respect minimum EN pulses to avoid reset storms in chained VRMs or MCU domains.

Document clear conditions and PG masks.

Rsense with Kelvin routing gives best accuracy and repeatability at the cost of power loss and area. RDS(on) saves BOM but drifts +60–90% hot and varies by lot; guardband aggressively or calibrate. For higher currents, DCR sense plus NTC compensation is a low-loss middle ground.

Recheck limits at hot VIN and hot board.

Start with a small RC at the sense node, tight Kelvin routing, and leading-edge blanking around 80–200 ns. Add comparator deglitch 0.5–2 µs for inductive loads, shorter for digital rails. Validate with conducted/radiated immunity bursts and count nuisance trips against thresholds.

Correlate spike width to t_blank before increasing thresholds.

Gate downstream EN from upstream PG to avoid starting into a collapsing bus. Mask downstream PG during upstream faults and enforce minimum EN pulses. On brownouts, allow ride-through at the front end while holding downstream rails off until the boost recovers and PG is stable.

Scope PG/EN edges; add debounce to shared lines.

Log VIN, Iload, board temperature, t_trip, t_clear, PG state, and a compact fault code (OCP/OVP/UVP/OTP/retry count). Include pre-bias flag and firmware revision. Store rolling windows in non-volatile memory and export CSV during service to accelerate root-cause analysis.

Add timestamps and board serials for traceability.