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Push-Button / Manual Reset Debounce

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What It Solves

False/Repeated Resets

Mechanical bounce (0.1–2 ms packets) and EMI glitches (<1–10 µs) cause spurious triggers before software can stabilize inputs.

Cross-Level Mismatch

Push-pull RESET across 1.8/3.3/5 V risks VIH/VIL margin loss and pulse width “compression” after level shifting; power ramp edges add uncertainty.

Non-repeatable Long-Press

Time-base drift vs temperature/voltage shifts long-press timing, breaking UX and reliability expectations across builds.

Programmable Timing

Debounce 10–50 ms · Long-press 1–10 s (2/5/8 s bins) · Fixed reset pulse 20–200 ms.

Open-Drain First

Pull up to the host I/O domain per rail; push-pull allowed only with verified VIH/VIL and pulse-width retention.

Glitch Immunity

t_GLITCH_min ≥ 3–10 µs using RC pre-filter + digital filter; startup inhibit avoids power-ramp artifacts.

Capability strip: bounce immunity, cross-level safety, repeatable timing Three cards summarizing pain→countermeasure→verifiable metrics for push-button debounce and reset timing. Bounce → Immunity EMI glitches <10 µs t_GLITCH ≥ 5 µs Debounce 25 ms Cross-Level Safety OD + per-domain pull-ups No pulse shrink VIH/VIL verified Repeatable Timing Long-press & reset pulse t_LONG = 5 s ±10% t_RST = 100 ms ±10%

Acceptance Targets

  • False resets: 0 in 105 presses under bounce+EFT profiles.
  • t_DEBOUNCE ±20%, t_LONG ±10%, t_RST ±10% across –40~+105 °C, VDD ±10%.
  • Multi-domain OD fanout within I_sink pin rating.

BOM Remarks (Copy-ready)

Debounce 25 ms ±20%; Long-press 5 s ±10%; Reset pulse 100 ms ±10%. RESET = Open-Drain, per-domain pull-ups 10–47 kΩ. MR glitch immunity ≥5 µs with RC pre-filter (220 Ω/47 nF).

Architecture & Signal Levels

Output Type: Open-Drain First

Pull up to the host I/O domain per rail (10–47 kΩ). For push-pull, validate VIH/VIL at corners and ensure reset pulse width is preserved after level shifting.

  • Fanout current: I_sink_total = Σ(Vi/Ri) < pin rating.
  • Rise time: tr ≈ 2.2·Rpullup·Cline (verify last edge of t_RST).

MR Input: RC + Digital Filter

Use 100–330 Ω + 10–100 nF at MR to attenuate sub-µs/µs glitches; set digital t_GLITCH ≥ 3–10 µs. Add startup inhibit ≥ 200 ms to ignore power-ramp chatter.

  • RC cutoff: fc ≈ 1/(2πRC) (e.g., 220 Ω×47 nF → ~15.4 kHz).
  • Keep UX: let digital logic enforce t_DEBOUNCE; avoid excessive C.

Finite State Machine

Idle → Debounce → Pressed → LongPress → ResetPulse → ReleaseWait → Idle. ReleaseWait suppresses post-long-press re-triggers on key release.

  • Short press → IRQ/soft reset; Long press → hard reset/shutdown.
  • t_RST ≥ 8–12 cycles of the slowest clock domain.

Cross-Level & EMI/ESD Notes

  • Prefer OD + per-domain pull-ups for 1.8/3.3/5 V islands.
  • For long RESET wires, add near-end pull-up + 22–100 Ω series.
  • Route away from high dV/dt power edges; guard with GND where needed.
Architecture overview: MR filter, debounce FSM, reset pulse, level match, multi-domain fanout Block diagram with labeled open-drain/push-pull, pull-up resistors, VIH/VIL, t_GLITCH and t_RST across host domains. Button MR Input RC Filter R=100–330 Ω · C=10–100 nF t_GLITCH ≥ 3–10 µs Debounce FSM Idle→Debounce→Pressed →LongPress→ResetPulse →ReleaseWait Reset Pulse t_RST = 20–200 ms Level Match OD / PP VIH/VIL verified Host Domains A / B / C RC attenuates sub-µs/µs glitches OD preferred Per-domain pull-ups t_RST preserved

Fanout check: I_sink_total = Σ(Vi/Rpullup,i) < I_sink_pin_max. Rise time: tr ≈ 2.2·Rpullup·Cline; verify the final edge does not violate t_RST perception at the slowest domain.

Thresholds & Timing

Parameter Dictionary (Canonical)

  • t_DEBOUNCE: 10–50 ms (typ. 25 ms)
  • t_LONG: 1–10 s (bins: 2/5/8 s)
  • t_RST (reset pulse): 20–200 ms (typ. ≥100 ms)
  • t_GLITCH_min: ≥3–10 µs (digital) or RC-equivalent
  • V_IL / V_IH: MR input thresholds (corner-verified)
  • R_PULLUP: 10–47 kΩ per domain (by Cline/noise/fanout)

Design Rules & Formulas

  • Slowest-domain coverage: t_RST ≥ N / f_clk_min (N = 8–12).
  • Rise time check: tr ≈ 2.2 · R_PULLUP · Cline (verify final edge recognition).
  • RC glitch attenuation: for a negative pulse of width τg, Vout/Vin ≈ 1 − e−τg/(R·C); combine with t_GLITCH_min.
  • No-in / No-out: before stability → no trigger; after ≥ t_DEBOUNCE → must trigger.

Copy-Ready BOM Notes

t_DEBOUNCE = 25 ms ±20%; t_LONG = 5 s ±10%; t_RST = 100 ms ±10%.
t_GLITCH_min ≥ 5 µs; MR RC pre-filter 220 Ω / 47 nF (or equivalent).
RESET = Open-Drain; per-domain pull-ups 10–47 kΩ; submit corner validation for any cross-brand swap.

Worked Example

Slowest clock domain = 32 kHz ⇒ t_RST ≥ 8/32k ≈ 250 ms. If UX targets 100 ms, use split resets: main domain 100 ms; slow domain gated so it still observes ≥8 cycles logically.

For Cline = 60 pF and R_PULLUP = 22 kΩ, tr ≈ 2.2·22k·60p ≈ 2.9 µs — safely below typical t_RST.

Edge Conditions

  • Very slow ramps (50–500 ms): confirm “no-in/no-out”.
  • Level-shifted push-pull: re-measure t_RST at the far side.
  • Long cable: near-end pull-up + 22–100 Ω series to tame ringing.
Timing windows for debounce, long-press and reset pulse Waveform panel showing bounce, accepted debounce window, long-press threshold (dashed) and fixed reset pulse bar. Time → Debounce window Long-press threshold Reset pulse
  • False resets: 0 in 105 presses with bounce + 1/3/10 µs glitch injection.
  • t_DEBOUNCE ±20%, t_LONG ±10%, t_RST ±10% across −40~+105 °C and VDD ±10%.
  • Verified “no-in/no-out” under 50–500 ms power ramps.

Integration & Sequencing

Interlocks & Dependencies

  • Prefer OD + per-domain pull-ups for 1.8/3.3/5 V islands, or use level-translation + buffers.
  • Closed loop: Reset → stable PG (aggregate) → Run.
  • Chained deps: Reset(A) → PG(A) → Reset(B) → PG(B) …

MCU Roles & Inhibit Windows

  • Short press → IRQ/soft reset/menu; long press → hard reset/shutdown.
  • Startup Inhibit ≥ 200 ms after power-up or reset.
  • ReleaseWait suppresses post-long-press re-triggers.

Fail-Safe Patterns

  • RESET open/short detection; dual-path OR or active-gate backup.
  • Stuck/abnormal bounce → timeout fuse (avoid repeated hard resets).
  • Unstable PG must block downstream reset release.
Reset tree with MR→FSM→Reset Pulse→Fan-Out and PG aggregation Block-level reset topology showing per-domain pull-ups across 1.8/3.3/5 V, with PG aggregation and sequencing arrows. MR Button / RC Debounce FSM Startup Inhibit Reset Pulse t_RST Fan-Out Buffer OD / Level Match Domain A · 1.8 V Domain B · 3.3 V Domain C · 5 V Per-domain pull-ups OD preferred PG Aggregator System OK Reset → PG (aggregate) → Run Startup Inhibit t_RST preserved

RESET = Open-Drain; per-domain pull-ups 10–47 kΩ or level-matched fan-out buffer. Enforce sequencing: Reset → PG (Aggregate) → Run. Startup Inhibit ≥ 200 ms; ReleaseWait after long-press.

Validation

Stimulus Profiles

  • Bounce: random/periodic; packet length 0.1–2 ms; duty 10–90%; repetitions 104–105.
  • Slow ramps: 50–500 ms up/down; add ±2–5% micro-jitter around plateau.
  • Ultra-short glitches: <1 µs / 3 µs / 10 µs; edges <50 ns; amplitude 0→VIO ±10%.

Corner Conditions

  • Temperature: −40 to +85/+105 °C; VDD: nominal ±10%.
  • I/O islands: 1.8 / 3.3 / 5 V tested independently.
  • EMI: EFT/Burst adjacency; near-field RF 80–1000 MHz (3–10 V/m equivalent); long-trace coupling.

Tolerance Sweeps

  • t_DEBOUNCE ±20%, t_LONG ±10%, t_RST ±10% (three-axis combinations).
  • R_PULLUP = 10/22/47 kΩ × Cline = 20/60/120 pF × line length = 5/20/50 cm.
  • Forced combo example: 300 ms ramp × 3 µs glitch every 10 ms × VDD −10% × 85 °C × R_PULLUP 47 kΩ + Cline 120 pF.

Fixtures & Instrumentation

  • Arbitrary waveform generator: bounce envelope + glitch injection; slope sweeps.
  • Digital oscilloscope ≥200 MHz: pulse-width stats (t_RST), threshold excursions, trigger tagging.
  • Thermal chamber −40~+105 °C; programmable supplies (±10% scan); independent I/O rails.
  • Injection nodes: Generator→MR; DUT RESET→Scope; observe PG/FAULT in parallel.

Data Schema (Logging)

Conditions: Temp, VDD, IO_Level, LineLen, R_PULLUP, C_line, GlitchProfile, Slew.
Results: Pass/Fail, t_RST_meas, t_DEBOUNCE_meas, FalseResetCount, t_GLITCH_max_pass, Notes (waveform refs).
Conclusion: Acceptable Window (t_DEBOUNCE_min/max_pass, t_RST_min_pass, t_GLITCH_max_pass).

Pass / Fail Criteria

  • False reset rate: 0 in 105 presses (or ≤1e−5) under full matrix.
  • t_RST preservation: far-end domain measurement within ±10% of spec.
  • No-in / No-out: no trigger before stability; must trigger after ≥ t_DEBOUNCE.
  • EMI robustness: no early release / double-trigger under EFT/Burst & RF tests.
Validation rig for MR→FSM→RESET with pass/fail criteria Generator→MR→DUT(FSM)→RESET→Scope; right column shows pass/fail blocks; bottom strip lists temperature and supply corners. Generator Bounce/Glitch/Ramp MR Input Node DUT (FSM) Debounce / Long-press Scope t_RST / Events Pass Criteria False reset ≤ 1e−5 t_RST within ±10% No-in / Must-out EMI robust Corners: Temp −40~+105 °C · VDD ±10% · IO 1.8/3.3/5 V

Cross-Brand IC Mapping

Cards show Function, Brand/PN, Output Type, Timing (t_RST / debounce support), and Notes. Prefer Open-Drain for cross-voltage domains; verify push-pull VIH/VIL and pulse preservation at the far side. Align timing to the slowest domain: t_RST ≥ 8–12 / f_clk_min. Debounce/long-press is guaranteed by the FSM; supervisors provide thresholds/timers.

Supervisor / Reset Timer

TI · TPS3836 / TPS3837

Output: OD/PP options · Timing: fixed delays · Notes: simple MR path; broad availability; good baseline for multi-domain pull-ups.

Programmable Delay + MR

TI · TPS3895

Output: OD · Timing: programmable delay · Notes: flexible Reset→PG sequencing; aligns well with fixed t_RST from FSM.

Watchdog + MR Path

TI · TPS3430

Output: OD · Timing: WDT windowing · Notes: ties MCU short-press logic to supervised hard-reset policies.

MR / Reset Supervisor

ST · STM6717 / STM6718

Output: OD · Timing: fixed · Notes: lightweight integration; suited for multi-level islands via per-domain pull-ups.

Supervisor + MR

ST · STM811 / STM706

Output: OD · Timing: thresholds + delay · Notes: common pairing with MCU/PMIC reset paths.

RTC Reference for MR Strategy

NXP · PCF8523 / PCF8563

Output: IRQ/OD · Timing: time base · Notes: provides schedule/wake references; combine with FSM for debounce/long-press.

System Basis (Supervision)

NXP · MC33910

Output: OD · Timing: integrated power supervision · Notes: multi-domain PM features; requires system-level regression for PG/EN chains.

Voltage Supervisor + MR

Renesas · ISL88002 / ISL8810

Output: OD · Timing: thresholds + delay · Notes: good threshold accuracy; low power.

RTC + Switchover

Renesas · ISL1208 / ISL1209

Output: IRQ/OD · Timing: time base + backup · Notes: aligns long-press UX with cold-start windows; pair with FSM timing.

Threshold + Reset Family

onsemi · NCP300 / NCP301 / NCP308

Output: OD · Timing: fixed delays · Notes: cross-voltage friendly; stable sourcing for procurement.

Supervision Series

onsemi · NCP31x Family

Output: OD · Timing: thresholds + delay · Notes: broad variants; fits OD-first strategy.

Supervisor / Reset Timer

Microchip · MCP1316 / MCP1321

Output: OD · Timing: multiple delay bins · Notes: small packages; easy drop-in for MR paths.

Low-Power Reset

Microchip · MCP111 / MCP112

Output: OD · Timing: fixed · Notes: minimal BOM impact; entry-level MR companions.

Automotive-Grade MR/Supervision

Melexis · MLX-series (representative)

Output: OD (typ.) · Timing: thresholds + delay · Notes: robust across temperature and noise; check AEC-Q variants for compliance.

Copy-Ready Procurement Hooks

  • RESET = Open-Drain; per-domain pull-ups 10–47 kΩ (or level-matched buffer on push-pull).
  • Timing alignment: t_RST ≥ 8–12 / f_clk_min; debounce/long-press via FSM, not the supervisor.
  • Automotive: use only AEC-Q lines within the seven brands; re-run Chapter 5 matrix post-swap.
  • BOM note (paste-ready): “RESET=OD; per-domain pull-ups 10–47 kΩ; t_DEBOUNCE=25 ms±20%; t_LONG=5 s±10%; t_RST=100 ms±10%. Brand swap requires corner validation.”

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BOM Remarks & Procurement Hooks

Hard Requirements

  • RESET output shall be Open-Drain with ≥10 kΩ pull-up to the host I/O rail. Push-pull not accepted unless VIH/VIL and far-end pulse width are validated across PVT corners.
  • Timing: t_DEBOUNCE=25 ms ±20%; t_LONG=5 s ±10%; t_RST=100 ms ±10%.
  • Glitch immunity: t_GLITCH_min ≥5 µs at MR input; provide RC pre-filter (R=220 Ω, C=47 nF or equivalent).
  • Fan-out: for multi-domain RESET, use OD + per-domain pull-ups or a level-safe fan-out buffer; keep wiring length <10 cm or add buffering.
  • Startup Inhibit ≥200 ms after power-good to avoid boot-phase false presses.

Brand Swap Policy

Cross-brand alternatives are limited to TI / ST / NXP / Renesas / onsemi / Microchip / Melexis. Before release, update internal mapping and re-run the Chapter-5 validation matrix under temperature, supply, and EMI corners. For AEC-Q programs, swap only within automotive lines and keep output type (OD preferred) and delay bins equivalent.

Acceptance & Evidence

  • False reset rate ≤1e−5 over ≥105 press events under full matrix stimulation.
  • t_RST at the slowest domain within ±10%; debounce and long-press thresholds met.
  • “No-in / Must-out” holds from −40~+105 °C, VDD ±10%, with EFT/RF exposure.
  • Provide waveforms/CSV for t_GLITCH_max_pass, t_DEBOUNCE_min_pass, t_RST_min_pass.

Paste-ready BOM Note

RESET output shall be Open-Drain with ≥10 kΩ pull-up to the host I/O rail. Push-pull is not accepted unless VIH/VIL and far-end pulse width are validated across PVT corners. Timing: t_DEBOUNCE=25 ms ±20%; t_LONG=5 s ±10%; t_RST=100 ms ±10%. Glitch immunity: t_GLITCH_min ≥5 µs at MR; RC pre-filter (R=220 Ω, C=47 nF or equivalent). Fan-out: OD + per-domain pull-ups (or level-safe buffer), wiring <10 cm or add buffering. Brand swap: TI/ST/NXP/Renesas/onsemi/Microchip/Melexis only; update mapping and re-run Chapter-5 validation. Startup Inhibit ≥200 ms after power-good.

Frequently Asked Questions

Why prefer open-drain RESET for cross-voltage domains?

Open-drain lets each domain pull up to its own rail, giving safe fan-out and clean voltage compatibility. It avoids push-pull contention and level-mismatch that can shorten pulses at the far side. If push-pull is used, you must verify VIH/VIL and the received pulse width across PVT corners and EMI conditions.

How long should debounce be for tactile switches?

Typical tactile bounce sits in the 10–50 ms range. Choose about 25 ms, then confirm under temperature extremes, supply variation, and injected EMI. Too short increases false triggers; too long hurts user experience for short actions. Validate the acceptable window with randomized bounce packets and record minimum stable press duration.

What is a safe long-press threshold for hard reset or shutdown?

Most systems adopt 2–8 s depending on safety and regulation. Five seconds is a balanced default that reduces accidental activation while staying acceptable for usability. Separate soft-reset actions to short presses and reserve long-press for irreversible operations. Confirm timing at temperature and with clock tolerances to keep user experience consistent.

How do I guarantee minimum reset pulse width across corners?

Use a fixed t_RST from the FSM or supervisor and size it to the slowest clock domain: at least 8–12 cycles at the minimum frequency. When crossing levels, re-measure pulse width at the far side, especially with push-pull or translators. Add fan-out buffering if rise times or loading threaten pulse preservation.

How to filter EMI/EFT bursts on the MR pin without hurting UX?

Combine a small RC pre-filter with a digital t_GLITCH threshold so EFT-like spikes are rejected while short presses remain responsive. Budget the RC delay so it does not consume the allowed 25 ms debounce window. Validate with burst sequences and near-field RF while measuring the minimum stable press that still triggers reliably.

How to avoid double-trigger when the user releases after a long-press?

Add a ReleaseWait state to swallow edges immediately after the long-press event is latched. Emit a single, fixed-width pulse, then enforce a short inhibit window so residual bounce cannot retrigger. Clear debounce counters only after the button is stable again. Validate with slow ramps and random release bounce patterns.

Can I share RESET across multi-voltage domains safely?

Yes—prefer open-drain with per-domain pull-ups so each island tracks its rail. Keep traces short and check combined leakage and input capacitance. For long harnesses or heavy fan-out, use a level-safe buffer to preserve pulse width and edges. Always re-measure at the far end before sign-off in corner conditions.

How to validate debounce and long-press under temperature drift?

Sweep −40 to +105 °C and VDD ±10% while applying randomized bounce packets and slow ramps. Record minimum stable press duration and the long-press decision point, then compare against targets: 25 ms debounce and 5 s long-press. Use acceptance windows rather than single values, and include EFT/RF exposure for realistic worst-case behavior.

What startup inhibit time avoids power-on false presses?

Use at least 200 ms after power-good before accepting MR input. This masks slow supply ramps, digital initialization noise, and relay chatter that resemble valid presses. Gate the FSM with the PG aggregate, then enable debounce logic. Verify with 50–500 ms ramps, brief brown-outs, and injected bounce during early boot phases.

How to spec glitch immunity for procurement?

State a numeric threshold such as t_GLITCH_min ≥5 µs at the MR pin, plus an RC pre-filter target. Define the test using an arbitrary waveform generator with sub-microsecond pulses and specified edge rates. Include pass/fail windows and require waveform evidence under temperature and supply corners before approving brand substitutions.

When is push-pull RESET acceptable?

Prefer push-pull only within a single, shared I/O rail where VIH/VIL and edge rates are guaranteed. Measure the pulse at the far end after any translators, and confirm EMI resilience so overshoot or undershoot does not truncate width. For multi-voltage fan-out, open-drain with per-domain pull-ups is the safer default.

What are the top risks when swapping brands late in the cycle?

Timing bins and default polarities may differ, and push-pull versus open-drain can change far-end pulse width. Long-press policies vary across product lines. Update the internal mapping, then re-run the Chapter-5 matrix at temperature, supply, and EMI corners. Require waveform evidence and revise the BOM note before release approval.

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