Reference oscillators, synthesis & jitter cleaning, clock distribution, interface-focused clocks, timing & synchronization, converter/RF clocks, RTC, monitoring & health, key specs, and design hooks.
Reference Oscillators
XO (Crystal Oscillator)
Fixed frequency, low PN, cost-effective; general reference/MCU clock.
TCXO (Temperature-Compensated XO)
ppm-class stability & fast thermal recovery for comms/measurement.
OCXO (Oven-Controlled XO)
Ultra-low drift & PN; best short/mid-term stability for timing/microwave.
VCXO
Fine tuning range for PLL tracking; video/audio sync.
VCTCXO
Adjustable TCXO—lock & calibrate friendly for cellular/GNSS.
MEMS Oscillator
Shock/vibration tolerant; programmable frequencies; moderate PN.
Programmable XO
I²C/SPI set-frequency for platform builds & flexible SKUs.
Synthesis & Jitter Cleaning
Fractional-N / Integer-N PLL
Wide ratios & fine step; PN/spur trade-offs for LO/system clocks.
Jitter Attenuators / Clock Cleaners
Tunable loop BW, external refs, jitter profiles for converters/SerDes.
CDR (Clock & Data Recovery)
Recover clock from data with EQ & jitter tolerance for high-speed links.
DDS (Direct Digital Synthesis)
Fine steps & fast hops; manage spurs for waveform/scans/radar.
Spread-Spectrum Clocking (SSC)
Peak EMI reduction with down-spread; board/PSU/storage friendly.
Distribution & Fanout
Zero-Delay Buffers (ZDB)
Feedback-aligned low skew for multi-domain FPGA/SoC.
LVDS/HCSL/LVPECL Fanout Buffers
Multi-output, low jitter/skew; selectable levels for PCIe/SerDes.
Programmable Delay / Phase
ps–ns steps for phase alignment & multi-card sync.
Clock Crosspoint Switch
Dynamic routing with bypass/guard paths for redundancy/testing.
Glitch-Free Clock Mux
Hitless main/backup switching and failover.
Interface-Focused Clocks
JESD204 Ref Clock & SYSREF
Subclass-1 alignment & low random jitter for high-speed ADC/DAC.
PCIe Reference Clocks (SRNS/SRIS)
HCSL/LVPECL with optional SSC for CPUs/switches.
Ethernet/SyncE PHY Clocks
25/125/156.25 MHz; EEC/SEC classes for carrier backhaul.
USB3/SDI/Video Clocks
27/74.25/148.5 MHz & genlock options for broadcast/cameras.
Audio Master Clocks
Low PN MCLK/BCLK/LRCK with ASRC/PLL cooperation.
Timing & Synchronization
IEEE 1588/PTP Hardware Timestamping
One/two-step stamping, delay correction & clock recovery.
Synchronous Ethernet (SyncE)
EEC/SEC, jitter filtering for carrier/5G backhaul.
GNSS-Disciplined Oscillators (GPSDO)
OCXO/TCXO disciplining & holdover strategies.
White-Rabbit-Style Timing
ps-level alignment with bidirectional link calibration.
Timing Cards & Modules
PLL + cleaner + fanout in one; disciplining & alarms.
Converters & RF
ADC Sampling Clocks
Ultra-low random jitter; short, differential routing for RF/DC sampling.
DAC / RF Synth Clocks
Low spurs & SYSREF cooperation for direct RF conversion.
RF LO Synthesizers
Frac-N + external VCO for low PN/low spurs TRx.
Low-Speed Timebase & RTC
RTC (Real-Time Clock)
32.768 kHz crystal/XO, calendar/alarms, timestamping.
RTC Backup & Switchover
Ultra-low leakage with supercap/coin-cell holdover.
TCXO-Based RTC
Lower drift via TCXO disciplining; I²C timekeeping.
Secure RTC / Time-Stamping
Tamper detection, signed time, power-fail events.
Monitoring & Health
Clock Monitor / Missing-Pulse
Freq offset & loss-of-lock alarms; automatic switchover.
Phase/Frequency Monitors
Phase measurement/TDC hooks for channel alignment.
Aging/Thermal Compensation
Digital calibration & drift estimation for long-life systems.
Key Specs & Selection
Phase Noise & Jitter
Offset PN curve, RMS jitter window, converter SNR budgeting.
Skew & Alignment
Inter-channel skew/drift with ZDB/phase trims.
Stability
ppm/°C, daily/yearly aging—timing/comm critical.
Spurs & Masks
Frac-N spurs & DDS images—purity for RF/wideband.
Output Standards
LVCMOS/LVDS/HCSL/LVPECL—swing, terminations, common-mode.
Supply & EMI
PSRR, isolation/filters, SSC strategy & compliance.
Loop Bandwidth
Cleaner vs tracker trade-offs; PLL stability & lock time.
Design Hooks & Pitfalls
Reference & Isolation
Clean refs/low-noise LDOs; analog/digital isolation; length-matched diff pairs.
Clock-Tree Planning
Source→cleaner→fanout→endpoints; hierarchy, fanout budget & redundancy.
PCB Layout & Routing
Straight/short paths, impedance & terminations, controlled returns & slots.
JESD204 SYSREF/LMFC
Subclass-1 alignment, delay match, jitter/skew windows.
EMI & SSC
Choose spread depth/rate; disable SSC on sensitive chains.
Thermal & Mechanical
OCXO/MEMS placement & airflow; minimize thermal gradients.
Production Test & Cal
PN/jitter measurement, EEPROM params & field trim hooks.
