Reset Polarity & Levels: Push-Pull vs Open-Drain

Q: How do I pick the pull-up value for an open-drain reset shared by multiple devices?

Choose RPU so the bus meets t_r ≈ 2.2·RPU·CBUS ≤ 0.1·TFEED. Estimate CBUS=ΣCTRACE+ΣCPIN, then back-solve RPU. For long traces or large fan-in, prefer the lower end of the range. Validate at the worst node by measuring 10–90% rise-time and archiving a bus-C audit table.

Q: When is push-pull safer than open-drain on mixed-voltage boards?

Use push-pull for same-domain, low-jitter, high-speed reset where a crisp edge is required. Use open-drain for cross-domain and wire-OR cases. If a PP driver must cross down-level, add 100–330 Ω series and a Schottky clamp to the target VDD; never wire-OR PP with other active drivers.

Q: How do I avoid back-power when a 5 V push-pull drives a 1.8 V RESET?

Clamp the down-level input by adding a 100–330 Ω series resistor at the PP source and a Schottky diode to 1.8 V. Alternatively, convert to OD output and pull up to 1.8 V. Acceptance: with the 1.8 V rail off, ΔVVDD<100 mV and Ibp below 50% of the clamp spec.

Q: What active polarity should I choose if the MCU exposes both RESET and RESET#?

Prefer active-low (RESET#) with OD outputs for wire-OR and cross-domain flexibility. For same-domain, low-noise paths, active-high + PP is acceptable. Lock the choice across schematic symbols, BOM fields, and firmware comments to prevent semantic mismatches during layout or procurement.

Q: Can I wire-OR two supervisors to one reset line without chatter?

Yes—use OD outputs, implement a single pull-up point near the load, and add a small far-end RC (1–4.7 nF) for release damping. Validate by toggling each source independently; acceptance is a release glitch < 20 µs and no ping-pong behavior across temperature and supply corners.

Q: How do rise-time and pre-bias interact to create false “release” events?

A slow t_r can linger around thresholds while pre-biased nodes appear “high”. Keep t_r ≤ 0.1·TFEED, reduce RPU, or add a far-end RC to sharpen crossing. Under brown-in/out slopes, ensure the dV/dt × window overlap stays short; target an effective overlap < ~50 µs for robust immunity.

Q: What sink-current target is safe for OD outputs across −40~+125 °C?

Compute Isink ≥ (VPU − VOL,max)/RPU, then add 20–30% margin for temperature and lot variation. Verify at the hottest corner where VOL,max typically rises. If fan-in or trace length increases, reassess RPU and re-measure worst-node 10–90% rise-time to confirm timing headroom.

Q: Do I need a series resistor on a push-pull reset into a lower-voltage domain?

Yes in most cases. Insert 100–330 Ω in series to limit contention and pair with a Schottky clamp to the lower VDD. Exceptions are rare and require identical domain levels and no back-power path. Always re-test during power-down to ensure ΔVVDD remains below acceptance.

Q: How do I validate polarity through brown-in/brown-out ramps and fast glitches?

Test with three ramp rates (fast/typical/slow). Probe RESET vs VDD/CLK using matched bandwidth limits. The assert/release windows must not invert under any slope or injected glitch. Record timing at −40/25/85/125 °C; acceptance is no polarity inversion and no false releases during fault-injection pulses.

Q: What’s an acceptance criterion for shared pull-ups on long traces?

Measure CBUS and worst-node t_r. Accept if t_r ≤ 0.1·TFEED, or ≤ 1 µs whichever is stricter. Add a small far-end RC to tame rebounds. Keep a trace-of-record: topology, probe points, cable model, and before/after waveforms for ECO tracking and audits.

What It Solves

This page focuses on output type (push-pull vs open-drain), active polarity (high/low), and cross-domain pull-ups. It addresses back-power during partial power, slow release edges on shared lines, and polarity mismatches across 1.2/1.8/3.3/5 V domains. Window thresholds, delays/debounce, reset tree fanout, and watchdog topics are handled on sibling pages.

Mixed Voltage Domains

MCU/PMIC/FPGA run at different I/O levels (1.2/1.8/3.3/5 V); RESET must cross domains safely.

Action: Prefer OD + pull-up to the target domain for cross-domain reset.

Polarity Mismatch

Devices expose RESET (AH) and RESET#/RST_N (AL). Miswiring causes always-reset or never-reset.

Action: Unify polarity via OD + target pull-up; otherwise use a small inverter/gate.

Pre-bias & Back-power

PP across domains can feed target rails via ESD/clamp diodes during partial power or power-down.

Action: For PP cross-domain, add 100–330 Ω series + Schottky to target VDD and verify no self-bootstrap.

Shared Wire-OR Lines

Mismatched pull-up vs bus capacitance yields slow release and chatter on multi-source resets.

Action: Use single-point pull-up near the load and size R_PU for rise-time.

Deliverable: Recipes A/B/C

Three wiring recipes mapped to domains and polarity: OD + target pull-up; PP same-domain; multi-source Wire-OR with RC.

Deliverable: Acceptance

Rise-time, sink current, power-down self-bootstrap ΔV, and cross-domain glitch window are explicitly verified.

Deliverable: Cross-Brand Map

Quick filtering by PP/OD and AH/AL families across the seven brands (datasheets linked with rel="nofollow" in the full page).

Problems → Risks → Paths. Alt: Key reset pitfalls and mitigation routes across domains and polarities.

Sizing rules: rise-time t_r ≈ 2.2·R_PU·C_LINE, target t_r ≤ 0.1·T_FEED (or ≤1 µs whichever is stricter). For PP cross-domain, verify power-down self-bootstrap ΔV_VDD<100 mV and leakage below clamp limits.

Polarity Basics: Active-High vs Active-Low

Definitions & Notation

AH (active-high) means high level asserts reset; AL (active-low) means low level asserts reset (typical pins: RESET#/RST_N). Datasheets vary in “assert/release” wording—lock BOM polarity, schematic symbol, and firmware comments together.

Selection Logic

Prefer AL for flexibility: easy wire-OR and cross-domain with OD outputs.
Use AH + PP for same-domain, low-jitter fast edges; add protection when crossing into lower domains.
When control and target polarities differ, first try OD + pull-up to the target polarity; otherwise add a small inverter/gate.

Acceptance Points

Across cold/hot start and brown-in/out, the assert/release windows remain correct (no polarity inversion glitch).
Documentation consistency: schematic, BOM Polarity(AH/AL), firmware comments 1:1 matched; ECO recorded for changes.

Four-quadrant matrix for polarity and output choices. Alt: Typical wiring, pros/cons, pitfalls, and corner hints.

Engineering takeaway: Default to OD + AL with the pull-up tied to the target rail to unify polarity and avoid back-power. If low jitter is paramount in a single domain, choose PP + AH but add a series resistor and Schottky clamp when any level crossing is possible. Always validate rise-time vs the feed window and re-check under −40~+125 °C and ±10% supply variation.

Output Stage: Push-Pull vs Open-Drain

Push-Pull (PP)

Active pull-up and pull-down (low output impedance) → fast edges, no pull-up needed. Risks: cross-domain VOH > V_target, back-power via input clamps, short-circuit current when fighting other drivers.

Open-Drain (OD)

Sinks only; requires external pull-up to the target domain. Benefits: wire-OR, cross-domain friendly. Tradeoff: rise-time set by R_PU·C_LINE → too slow causes chatter/late release.

Quick sizing: rise-time t_r ≈ 2.2 · R_PU · C_LINE ; bus capacitance C_BUS = ΣC_TRACE + ΣC_PIN ; sink current I_sink ≥ (V_PU − V_OL,max) / R_PU ; temperature domain (−40~+125 °C): t_r ≤ 0.1 · T_FEED (or ≤ 1 µs, whichever stricter).

PP in Same vs Cross Domains

Same-domain: low jitter, fast edges — ideal for AH direct drives.
Cross-domain: add 100–330 Ω series + Schottky to target VDD to prevent clamp-diode back-power.
Don’t wire-OR PP with other sources; avoid direct PP → low-voltage domains without guards.

OD for Wire-OR & Large Fan-In

Single-point pull-up at the load; consider small far-end RC (e.g., 100 Ω / 1–4.7 nF) to tame rebounds.
R_PU range: 4.7–47 kΩ (use lower values for long traces / large fan-in). Check t_r and I_sink concurrently.
MCU internal pull-ups are not a substitute for external ones (tolerance/temperature/fan-in uncertainty).

PP: low Rout, fast; OD: flexible with R_PU·C_LINE limits. Alt: Equivalent circuits and rise-time comparison.

Design Gates & Acceptance

Environment sweep: −40/25/85/125 °C, ±10% supply, pre-bias and power-down conditions.
Pass lines: t_r ≤ 0.1·T_FEED (or ≤1 µs), I_sink ≥ spec, no ping-pong or false release, conflict current < protection limits.
Documentation: record R_PU, C_BUS estimate, worst-node waveforms & trigger conditions.

Level Domains & Cross-Domain Pull-Ups

Core Principles

OD: always pull up to the target domain (e.g., RESET#=1.8 V → pull-up to 1.8 V).
PP (source > target): add 100–330 Ω series + Schottky to VDD_target to prevent clamp-diode back-power.
Power-up order: “disconnect then power” — pull-up rail last or synchronized with the target domain.

Clamp Paths & Self-Bootstrap

PP VOH can feed the target VDD via input clamps, lifting the rail during partial power. Validate especially in power-down and half-powered states with dual-channel probing (VDD vs RESET).

Acceptance & calculations: back-power current I_bp (target domain off) must keep ΔV_VDD < 100 mV and remain below the device clamp limit; cross-domain glitch window (dV/dt overlapping threshold) < 50 µs or per your system budget.

OD uses target-rail pull-up; PP down-leveling needs series + Schottky; measure self-bootstrap on power-down. Alt: Three cross-domain patterns with probe points.

Do

OD → any domain (pull-up to target); single-point pull-up; verify dV/dt vs threshold window.
PP cross-domain with series + Schottky; scope VDD/RESET/pull-up simultaneously.

Don’t

PP → low-voltage domain without guards.
Multi-point pull-ups on shared lines.
Rely on MCU internal pull-ups for timing or fan-in guarantees.

Procurement Notes

Pick Schottky parts with low V_F/low leakage and suitable height; series resistors rated for edge conflicts; pull-ups in E96 1% for reproducibility. Keep small-batch second-source options ready.

Design Recipes

Three copy-ready wiring recipes focused on the output stage & cross-domain pull-ups. Use them as implementable defaults. Threshold windows, delays/debounce, and reset-tree topics are covered on sibling pages to avoid overlap.

Recipe A — Cross-domain & Mass-friendly (Default)

Topology: OD output → pull-up to target domain (10–47 kΩ) → far-end small RC (100 Ω / 1–4.7 nF).
Use for: cross-domain, wire-OR, multi-source resets.

Sizing: t_r ≈ 2.2·R_PU·C_LINE, target t_r ≤ 0.1·T_FEED. Check I_sink ≥ (V_PU − V_OL,max)/R_PU.

Acceptance: no far-end double-bounce; no power-down back-power.
Don’t: multi-point pull-ups on the same bus.

Recipe B — Low-Noise, High-Speed Same-Domain

Topology: PP output + same-domain direct; if crossing down-level, add 100–330 Ω series + Schottky to VDD_target.
Use for: AH direct drives, jitter-sensitive paths.

Targets: t_r, t_f < 200 ns (example). Choose series R vs conflict current; Schottky: low V_F/low leakage.

Acceptance: no reverse conduction beyond limits.
Don’t: wire-OR a PP with other drivers.

Recipe C — Multi-Device Wire-OR (Large Fan-In)

Topology: multiple OD sources → single-point pull-up near the load → unified debounce window (RC 1–4.7 nF).
Use for: PMIC + µP + external supervisor combined resets.

Notes: C_BUS = ΣC_TRACE + ΣC_PIN; compute worst-node and back-solve R_PU. Use lower R for long traces / large fan-in.

Acceptance: worst-node t_r meets target; no chatter; bus-C audit table archived.
Don’t: rely on MCU internal pull-ups for timing or fan-in guarantees.

Procurement notes: Pull-ups in E96 1% (keep a family of values); debounce C use C0G/NP0 (stable), X7R if tight space; Schottky with low V_F/low leakage and height within your mechanical limit. Prefer series-able part numbers for small-batch swaps.

Three recipes: A (OD + target pull-up + RC), B (PP same-domain with down-level guard), C (multi-OD wire-OR, single pull-up, unified RC). Alt: collage of wiring patterns with parameter hints.

Acceptance & Validation

Polarity Consistency

Cold start, hot reset, and brown-in/out with three slew rates. Dual-channel probe RESET vs clock/supply. Assert/release windows remain correct (no inversion glitch).

Pull-Up & Edge Timing

Measure 10–90% t_r and check the 0.1·T_FEED rule at −40/25/85/125 °C and ±10% supply. Re-validate after BOM changes.

Back-Power Test

With target domain off/half-on, record VDD lift (ΔV) and I_bp. Tune series R / Schottky until ΔV_VDD < 100 mV and I_bp below clamp limit.

Wire-OR Stability

For N-source buses, toggle each source low/release in turn. Ensure no ping-pong/chatter. Far-end RC should visibly damp rebounds.

Default pass lines (adjustable): t_r ≤ 1/10 × T_FEED (or ≤ 1 µs, stricter wins); ΔV_VDD < 100 mV and I_bp ≤ 50% of the clamp spec; on shared pull-ups, any source’s release glitch < 20 µs with no false trigger.

Acceptance examples: normal release (pass), slow edge (fail), false high from back-power (fail). Alt: waveforms with 10–90% markers and a pass-line checklist.

Traceability & Reporting

Store waveforms with identical vertical scales; annotate probes, bandwidth limits, and temperature points.
Keep a small table: R_PU back-solve, C_BUS audit, I_sink margin, dV/dt × threshold overlap time.
Any R/C/Schottky change updates BOM and re-runs the acceptance suite; keep ECO IDs in the report footer.

Cross-Brand Mapping (Output Type & Polarity)

Focus on mainstream automotive/general supervisors. Verify the exact variant (output driver & polarity) in the datasheet; families often offer multiple options.

Brand	Family / PN	Type	Polarity	Datasheet	Notes
TI	TPS3890-Q1	OD	AL (RESET#)	Datasheet (TI)	High-accuracy supervisor; open-drain reset simplifies wire-OR.
TI	TPS3808	OD	AL (RESET#)	Datasheet (TI)	Adjustable delay; common for MCU rails, wire-OR friendly.
TI	TPS3702 (Window)	OD (OV/UV)	AL flags	Product page (TI)	Independent open-drain OV/UV outputs; tie-together possible per DS.
ST	STM706 family	PP	AL / AH (RST / RST)	Datasheet (ST)	Push-pull reset outputs; variants provide both polarities.
ST	STWD100 (WDT+Supervisor)	OD / PP (by option)	Configurable	Product page (ST)	Watchdog with selectable output stage; OD suits wire-OR.
NXP	VR5510 PMIC	Reset outputs (per DS)	Typically AL	Product page (NXP)	Automotive PMIC with monitoring & reset; check pin type per HW guide.
NXP	FS5600 (PMIC)	Reset/WDT lines (per DS)	Per variant	Product page (NXP)	Window WDT + supervisors; confirm RESET pin driver per DS.
Renesas	ISL88013 family	PP (RST / RST both)	AL / AH	Datasheet (Renesas)	SOT-23 µP supervisors; complementary reset outputs available.
onsemi	NCP301 / NCV301	OD (N-ch)	AL / AH (options)	Datasheet (onsemi)	Ultra-low Iq detectors; OD with selectable active level.
Microchip	MCP100 / MCP101	PP (family-dep.)	AL / AH (by PN)	Datasheet (Microchip)	Legacy simple supervisors; choose polarity by suffix.
Microchip	MIC811 / MIC812	PP / OD (options)	AL / AH (by PN)	Datasheet (Microchip)	Tiny supervisors with multiple output/polarity options.
Microchip	MCP1316 / MCP1317	PP / OD (by option)	AL / AH	Datasheet (Microchip)	Automotive-friendly options and timing variants.
Melexis	MLX80050 (LIN SBC)	Reset (NRES)	AL (typ.)	Datasheet (Melexis)	SBC with undervoltage reset; confirm NRES drive & level in DS.

Note: Always confirm output driver (push-pull vs open-drain) and active level for the exact orderable PN; families often ship multiple variants under one umbrella page.

BOM & Procurement Notes

Required Fields

V_domain (in/out), Polarity (AH/AL), Output (PP/OD), I_sink(min), R_pullup range
AEC-Q100 grade, Temp range, Package height, Second-source (Y/N)

Optional

Wire-OR count, dV/dt limits, pre-bias behavior
Internal PU/PD present? WDT sharing semantics

Risks & Mitigations

Semantic/polarity mismatch → align schematic symbol, BOM fields, and firmware comments
PP cross-domain back-power → add 100–330 Ω series + Schottky clamp to target VDD
EOL / MOQ constraints → pre-approve dual-brand alternatives

Submit your BOM (48h)

Tip: For multi-source wire-OR across domains, prefer OD + pull-up at the target domain; validate I_sink vs R_pullup and ensure t_r ≤ 0.1×T_FEED at −40~+125 °C.

Frequently Asked Questions

How do I pick the pull-up value for an open-drain reset shared by multiple devices?

Choose R_PU so the bus meets t_r ≈ 2.2·R_PU·C_BUS ≤ 0.1·T_FEED. Estimate C_BUS=ΣC_TRACE+ΣC_PIN, then back-solve R_PU. For long traces or large fan-in, prefer the lower end of the range. Validate at the worst node by measuring 10–90% rise-time and archiving a bus-C audit table.

When is push-pull safer than open-drain on mixed-voltage boards?

Use push-pull for same-domain, low-jitter, high-speed reset where a crisp edge is required. Use open-drain for cross-domain and wire-OR cases. If a PP driver must cross down-level, add 100–330 Ω series and a Schottky clamp to the target VDD; never wire-OR PP with other active drivers.

How do I avoid back-power when a 5 V push-pull drives a 1.8 V RESET?

Clamp the down-level input by adding a 100–330 Ω series resistor at the PP source and a Schottky diode to 1.8 V. Alternatively, convert to OD output and pull up to 1.8 V. Acceptance: with the 1.8 V rail off, ΔV_VDD<100 mV and I_bp below 50% of the clamp spec.

What active polarity should I choose if the MCU exposes both RESET and RESET#?

Prefer active-low (RESET#) with OD outputs for wire-OR and cross-domain flexibility. For same-domain, low-noise paths, active-high + PP is acceptable. Lock the choice across schematic symbols, BOM fields, and firmware comments to prevent semantic mismatches during layout or procurement.

Can I wire-OR two supervisors to one reset line without chatter?

Yes—use OD outputs, implement a single pull-up point near the load, and add a small far-end RC (1–4.7 nF) for release damping. Validate by toggling each source independently; acceptance is a release glitch < 20 µs and no ping-pong behavior across temperature and supply corners.

How do rise-time and pre-bias interact to create false “release” events?

A slow t_r can linger around thresholds while pre-biased nodes appear “high”. Keep t_r ≤ 0.1·T_FEED, reduce R_PU, or add a far-end RC to sharpen crossing. Under brown-in/out slopes, ensure the dV/dt × window overlap stays short; target an effective overlap < ~50 µs for robust immunity.

What sink-current target is safe for OD outputs across −40~+125 °C?

Compute I_sink ≥ (V_PU − V_OL,max)/R_PU, then add 20–30% margin for temperature and lot variation. Verify at the hottest corner where V_OL,max typically rises. If fan-in or trace length increases, reassess R_PU and re-measure worst-node 10–90% rise-time to confirm timing headroom.

Do I need a series resistor on a push-pull reset into a lower-voltage domain?

Yes in most cases. Insert 100–330 Ω in series to limit contention and pair with a Schottky clamp to the lower VDD. Exceptions are rare and require identical domain levels and no back-power path. Always re-test during power-down to ensure ΔV_VDD remains below acceptance.

How do I validate polarity through brown-in/brown-out ramps and fast glitches?

Test with three ramp rates (fast/typical/slow). Probe RESET vs VDD/CLK using matched bandwidth limits. The assert/release windows must not invert under any slope or injected glitch. Record timing at −40/25/85/125 °C; acceptance is no polarity inversion and no false releases during fault-injection pulses.

What’s an acceptance criterion for shared pull-ups on long traces?

Measure C_BUS and worst-node t_r. Accept if t_r ≤ 0.1·T_FEED, or ≤ 1 µs whichever is stricter. Add a small far-end RC to tame rebounds. Keep a trace-of-record: topology, probe points, cable model, and before/after waveforms for ECO tracking and audits.

How do I document polarity/levels in the BOM to prevent line-side mix-ups?

Add explicit fields: Polarity (AH/AL), Output (PP/OD), V_domain (in/out), I_sink(min), R_PU range, and Internal PU/PD?. Ensure the schematic symbol and firmware comments use the same wording. For families with variants, capture the orderable suffix that locks output and polarity.

Does an MCU’s internal pull-up replace the external one for OD resets?

Usually no. Internal pull-ups are weak and vary widely, making t_r and fan-in margins unpredictable across temperature and lots. Keep an external R_PU sized for 0.1·T_FEED. On a short, single-source, same-domain path, you may waive it after worst-case timing and noise validation.

Reset Polarity & Levels