← Back to: Supervisors & Reset
What It Solves
Single source → multi-voltage
One reset source safely fans out to 1.0/1.2/1.8/2.5/3.3/5.0 V domains via open-drain trunk and per-domain pull-ups.
Deterministic timing & order
Guarantee per-leaf tRESET(min) and enforce release order using PG gating / delay / multi-rail supervisors.
EMI/ESD robustness
Leaf-side RC deglitch (1–4.7 nF) and Schmitt inputs suppress spurious releases under burst/ESD stress.
Small-batch friendly
Specify function-buckets (OD buffers / single-bit translators / supervisors) for cross-brand swaps without re-layout.
Different I/O rails
Each domain provides its own pull-up to its I/O rail; add single-bit level translation only at mismatched leaves.
Large fanout / long traces
Use a zoned OD buffer tree to control sink current and edge-rate; keep the trunk short and straight.
Ordering dependencies
RESET & PG(A) & Delay(B) → RESET_B; supervisors with programmable delays reduce discretes.
Glitch immunity
Leaf RC + Schmitt input; validate immunity threshold of 0.5–1.0 µs (automotive can be stricter).
ΣI_pullup @ RESET=LOW ≤ driver rating (typ. 8–12 mA).
t_rise(10–90%) per leaf < 1 ms (or per spec) at worst leaf.
t_RESET(min) ≥ PLL/clock settle + 20–30% margin on slowest domain.
No back-power during hot-plug/partial-rail-off tests.
BOM (paste-ready)
- Master RESET open-drain; each domain provides its own pull-up (10–47 kΩ) to its I/O rail.
- Segment with OD buffers if ΣI_pullup approaches driver rating; per-leaf 10–90% rise-time < 1 ms.
- Use single-bit translators at leaves for level mismatch; push-pull only when level-compatible and no back-power.
- Alternatives limited to TI / ST / NXP / Renesas / onsemi / Microchip / Melexis*; prefer AEC-Q100 where required.
Architecture & Signal Levels
Rise time
t_rise ≈ 2.2 · R_PU · (C_in + C_trace) → size R_PU to keep worst-leaf 10–90% < 1 ms.
Sink budget
I_sink_total = Σ(V_rail / R_PU_i) ≤ driver rating (typ. 8–12 mA). Add OD buffers when close.
Pull-up guidance
1.8 V: 15–56 kΩ · 3.3 V: 10–33 kΩ · 5.0 V: 10–22 kΩ (verify with layout C).
Where to translate
Keep trunk OD; place single-bit level translator at the leaf of mismatched rails.
Unify polarity
Active-low trunk; invert locally only when needed, ensuring level safety.
Zone buffers
When fanout > 5–8 or traces are long, add OD buffers at zone roots to cap ΣI_pullup and edge slew.
Glitch control
Leaf RC 1–4.7 nF and Schmitt input buffers; validate 0.5–1.0 µs glitch immunity.
Layout hygiene
Short straight trunk; separate from high dI/dt nodes; ensure solid return path to reduce coupled noise.
Thresholds & Timing (for Reset Signals)
Receiver thresholds aligned
Match VIH/VIL of each receiving domain to the level presented by the reset distribution: OD trunk + per-rail pull-ups, translators only at mismatched leaves.
Deterministic tRESET(min)
Define tRESET(min) from the slowest PLL/clock lock + init path, then add 20–30% margin so every leaf reliably resets under worst case.
Glitch immunity
Use leaf-side RC deglitch (1–4.7 nF) and/or Schmitt input buffers to achieve tGLITCH(min) ≥ 0.5–1.0 µs; automotive can be stricter.
Minimum pulse
t_RESET(min) = t_PLL/clk-lock + t_init × (1 + α), α = 0.2–0.3.
Rise time
t_rise(10–90%) ≈ 2.2 · R_PU · (C_in + C_trace) → target < 1 ms at the farthest leaf.
Glitch window
t_GLITCH(min) ≥ 0.5–1.0 µs with RC + Schmitt; verify across −40/25/+85 °C.
Noise margin
Ensure V_OL@driver vs V_IL(max) has ≥10–15% of rail as margin at the receiver.
Short-pulse injection
Sweep 0.2–5 µs pulses at the master reset; scope each leaf to see which pulses propagate. Record Pass/Fail vs width.
Slope/jitter scans
Vary supply ramps and superimpose ±ΔV/±Δt jitter; log false-release boundary clouds for worst-case domains.
Thermal corners
Re-run threshold and deglitch at −40/25/+85 °C; store t_RESET(meas) & t_GLITCH(min) evidence per leaf.
BOM (paste-ready)
- Each leaf must satisfy tRESET(min) defined by slowest clock/PLL + init path (+20–30% margin).
- Achieve tGLITCH(min) ≥ 0.5–1.0 µs via RC (1–4.7 nF) and/or Schmitt input buffers.
- Verify trise < 1 ms at the farthest leaf after RC tuning; keep OD trunk intact.
- Cross-brand swaps limited to TI / ST / NXP / Renesas / onsemi / Microchip / Melexis (supervisors); update validation records on change.
Integration & Sequencing
OD-first topology
Keep the master trunk open-drain; add OD buffers (LVC1G07/LVC2G07 class) as zone roots when fanout or trace length grows.
Per-domain pull-ups
Each domain pulls up to its own I/O rail; smaller RC for slow domains, larger R for fast domains to reduce sink current.
Ordering by PG & Delay
RESET_B = RESET_master AND PG_A AND Delay_B(τ). Supervisors with programmable delays reduce discrete gates.
Polarity discipline
Unify trunk as active-low; invert locally only if required—through level-safe inverters in the proper rail.
Sequencing vectors
Toggle PG_A/PG_B and observe B/C release relative to A; verify minimum pulse is preserved through logic.
Hot-plug robustness
Power-cycle zones while others remain up; ensure no premature release or back-power into unpowered domains.
Cross-rail PG integrity
When PG crosses rails, place translators at leaves/zone roots; re-check thresholds and directionality.
BOM (paste-ready)
- Topology: OD trunk; zone OD buffers as needed; per-rail pull-ups sized for t_rise at farthest leaf.
- Sequencing:
RESET_B = RESET_master AND PG_A AND Delay_B(τ). Record τ and polarity in test vectors. - Polarity: Trunk active-low; any inversion must be level-safe at the target rail.
- Alternatives: Function buckets only (OD buffers / Schmitt / level translators / multi-output supervisors) within TI / ST / NXP / Renesas / onsemi / Microchip / Melexis.
Validation
Scope
Only the reset distribution chain: master RESET_in → OD trunk/buffers/level translators → per-rail leaves RESET_x. Power-path/limiting belong to sibling pages and are treated as stress sources only.
Pass criteria
- ΣI_pullup at RESET=LOW ≤ driver/OD pin rating, ≥30% margin.
- t_rise(10–90%) at farthest leaf < 1 ms (or per spec).
- t_RESET(min) at each leaf ≥ design target (slowest PLL/clk + init + 20–30% margin).
- t_GLITCH(min) immunity ≥ 0.5–1.0 µs; no false release.
- No back-power: unpowered domains see <0.3 V bias at inputs.
Record fields
V_leaf_low, V_leaf_high, t_rise_10–90%, t_fall_90–10%, t_RESET_meas, glitch_count, I_sink_total, clamp_active?, notes.
Temperature
−40 / +25 / +85 °C（extend to +105/+125 °C if automotive). Re-measure thresholds and deglitch windows at corners.
Supply slopes
Slow 1 V/s · Medium 100 mV/ms · Fast 1 V/µs. Sweep ramps per rail and combinations of staggered domains.
Glitch injection
Negative pulses 0.3/0.5/1.0 µs into master RESET_n or leaf pull-ups via 50 Ω source and 10–100 Ω series injection.
Topology spots
Probe trunk, zone branches, and the farthest leaf. Include hot-plug and partial domain drop scenarios.
1) Static budget
Sum ΣI_pullup = Σ(V_rail/R_PU_i) at RESET=LOW. If >70% of rating, split zones with OD buffers, increase R_PU of fast domains.
2) Rise/fall timing
Measure t_rise(10–90%) and t_fall(90–10%) at each leaf. Tune RC/Schmitt so farthest leaf <1 ms while preserving t_RESET(min).
3) Min pulse proof
Inject a pulse train of narrowing resets; find leaf-wise minimum observed width. It must stay ≥ design t_RESET(min).
4) Glitch immunity
Inject 0.3–1.0 µs negative spikes; glitch_count stays 0. If not, add RC at leaf or replace with Schmitt buffer.
5) Back-power test
Bring up a high-rail domain while others are off; ensure unpowered leaves remain <0.3 V and clamps don’t conduct. If violated, move to OD + per-rail pull-ups or add level translation.
Export tip: Keep a CSV per build with the “Record fields” as headers; screenshot the heatmap and store alongside the CSV for traceability.
Cross-Brand IC Mapping
Why buckets, not PNs
Small-batch flows change suppliers frequently. Map by function bucket first, then pick representative PNs per brand to keep layout stable and validation repeatable.
Buckets for this page
A) OD buffer / Schmitt input · B) Single-bit level translator · C) Multi-output supervisor with timing. Melexis typically pairs supervisors/SBC with logic from other six brands.
| Function Bucket | TI | ST | NXP | Renesas | onsemi | Microchip | Melexis (note) | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| A) OD buffer / Schmitt Fanout zoning, deglitch at leaves |
SN74LVC1G07 / LVC2G07 (OD) SN74LVC1G17 (Schmitt) 1.65–5.5 V; OD avoids back-power |
74LVC1G07 / 74LVC2G07 74LVC1G17 Footprint-compatible across vendors |
74LVC1G07 / 74LVC1G17 Consider Nexperia continuity |
74LVC1G07GV / 1G17GV Good −40~+125 °C grades |
NC7SZ07 (OD) NC7SZ17 (Schmitt) TinyLogic, low quiescent |
(Limited logic portfolio) → Prefer their supervisors; logic buffers can be substituted by the other six vendors. | No general-purpose logic; use SBC/monitor outputs and pair with the other six vendors’ logic for fanout. | ||||||
| B) Single-bit level translator Use fixed direction for RESET |
SN74AUP1T34 (A→B) SN74LVC1T45 (DIR) Prefer fixed DIR to avoid “auto” mis-prop |
74LVC1T45 1.65–5.5 V, Ioff support |
P3A/AXC/AUP 1T family Check VOL vs VIL margins |
74LVC1T45G family DIR pin forces one-way RESET |
FXLA1T45 Tiny, wide voltage pairing |
(Does not focus on 1T) → If level shifting is required, switch to OD + per-domain pull-ups or regenerate RESET at the leaves with its supervisors. | Use equivalent 1T parts from the other six; Melexis focuses on automotive-grade SBC solutions. | ||||||
| C) Multi-output supervisor (timing) Generate clean RESET & sequencing |
TPS386000 / TPS386596 4-rail, delay MR, open-drain |
STM6717/6719/6720 2–3 rails + delay options |
(NXP usually provides RST_b via SBCs) Use SBC RST_b + OD fanout |
ISL88011/14/15 etc. Dual/multi-rail + WDI |
NCP308/NCV308 Programmable delay, low IQ |
MIC826 / MCP1316/18/19 / MIC2774 Leaf reset regeneration |
Provide the main reset via an SBC (e.g., the MLX80xx ecosystem), then fan out with OD. |
| rail | domain_voltage | R_PU(kΩ) | translator(class) | buffer(class) | supervisor(PN/class) | V_leaf_low(V) | V_leaf_high(V) | t_rise_10_90(ms) | t_RESET_meas(ms) | ΣI_pullup(mA) | glitch_count | clamp_active | note |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| leaf_A | 1.8 | 33 | AUP1T34 | LVC1G07 | TPS386000 | 0.12 | 1.78 | 0.6 | 5.0 | 0.18 | 0 | no | — |
Frequently Asked Questions
Why prefer open-drain for the master trunk instead of push-pull?
Open-drain isolates levels across domains and prevents back-power when some rails are unpowered or hot-plugged. Each domain supplies its own pull-up, so VIH/VIL follow the local I/O rail. Use push-pull only when voltages match, clamps cannot conduct, and validation shows no reverse current under worst-case ramps.
How do I size pull-ups to balance rise time and sink current?
Use t_r ≈ 2.2·R_PU·C_load and target <1 ms at the farthest leaf. Compute ΣI_pullup = Σ(V_rail/R_PU_i) at RESET=LOW and keep within the driver’s rating with ≥30% margin. Make slow domains smaller R to speed edges and fast domains larger R to reduce sink current and ringing.
How do I guarantee the minimum reset pulse at every leaf?
Define t_RESET(min) from the slowest PLL/clock lock and initialization, then add 20–30% margin. Verify with narrowing pulse trains while probing each leaf. If any leaf misses the target, generate timing with a multi-output supervisor or add gating/RC so the leaf sees a longer, clean active-low interval.
Can open-drain and push-pull mix in one tree? Where is the boundary?
Yes—keep the master and cross-domain trunk open-drain, and reserve push-pull for short, same-voltage leaf subtrees. If a translator is needed, place it near the destination and keep the upstream trunk open-drain. Mixing beyond that risks clamp conduction, reverse bias, and inconsistent thresholds across temperature.
When does fanout require additional buffers?
Add buffers when ΣI_pullup approaches the driver limit, when the farthest leaf exceeds 1 ms rise time, or when long traces cause ringing and false releases. Insert an open-drain buffer at each zone root, retune per-domain pull-ups, and re-verify rise time, t_RESET(min), and glitch immunity at temperature corners.
How do I avoid false release under EMI/ESD glitches?
At leaves, add RC deglitching (1–4.7 nF with 10–47 kΩ) or use Schmitt-input buffers so the waveform crosses thresholds once. Specify a t_GLITCH(min) target of 0.5–1.0 µs and show glitch_count = 0 in scope logs. Keep return paths short and zone the tree to limit capacitive fanout per branch.
Where should a level translator sit in the tree?
Place translators at the zone root or leaf, powered by the destination rail. Use fixed-direction parts (AUP1T/LVC1T45 class) so RESET propagates one way. Keep the upstream trunk open-drain with local pull-ups per rail. Avoid auto-bidirectional accelerators that can pass micro-pulses or oscillate with external pull-ups.
How should procurement write family-level alternatives instead of one PN?
Reference the function bucket and family class, e.g., “OD buffer: LVC1G07 class” or “Schmitt buffer: LVC1G17 class,” and limit brands to TI/ST/NXP/Renesas/onsemi/Microchip/Melexis. Require a validation update with CSV and scope captures showing rise time, t_RESET(min), ΣI_pullup, and no back-power under hot-plug conditions.
How do we prove there is no back-power into unpowered domains?
Run staggered-power tests with translators or OD fanout in place. Probe unpowered leaves and confirm inputs remain below 0.3 V while clamps stay off. Repeat across temperature and with fast ramps. If limits are exceeded, enforce OD trunk plus per-rail pull-ups or insert a fixed-direction translator at the affected boundary.
What if reset polarities are inconsistent across domains?
Keep the master path active-low for clarity and verification. Where an active-high input is required, insert a level-safe inverter or logic gate powered by the destination rail, and place it near the leaf. Re-measure t_RESET(min) at that leaf and confirm glitch immunity and back-power behavior remain within specification.
How to attach ≤1.0 V cores to the reset tree safely?
Treat sub-1.0 V cores as a separate zone. Use a fixed-direction translator or generate a fresh reset from a supervisor powered by the low-voltage rail. Verify VIL/VIH margins, ensure no leakage when the core is off, and document leaf-side t_RESET(min) and rise time at temperature corners.
Can a multi-output supervisor replace part of the buffer tree?
Yes. Supervisors generate consistent thresholds, delays, and a clean active-low pulse across process and temperature. Use the supervisor to produce per-rail release and order, then distribute via open-drain fanout with local pull-ups. This reduces RC stacks, narrows validation, and improves repeatability for small-batch builds.
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