RF Bias & PA Supply PMIC
This page focuses on power supplies and biasing for RF power amplifiers—including Envelope Tracking (ET), Average Power Tracking (APT) buck/boost stages, post-LC/LDO low-ripple rails, and negative gate bias generators. We cover the design links to EVM and ACLR without spilling into battery charging, eFuse, general LDO, or power-mux topics.
Target systems include 4G LTE and 5G NR FR1 (Sub-6), Wi-Fi 6/6E/7, and IoT classes such as NB-IoT/LTE-M. For mmWave (FR2), guidance applies to the baseband-side rails that interact with the PA linearity budget.
Architecture: ET/APT Path, Low-Ripple Post-Filter, and Bias Control
The supply path is organized left-to-right: APT/ET reference → Buck/Boost (with clock sync) → LC → optional LDO → PA. A separate Bias Generator provides −Vg and power-good based sequencing. Telemetry/Protection report to a system controller via I²C/SPI/PMBus.
Rule of thumb: sync fSW to an RF-friendly reference or fixed phase, then shape Zout(f) so that in-band ripple is dominated by LDO/LC while out-of-band content is filtered by the PA’s linearization budget.
Still unsure how to route ET/APT and bias sequencing for your PA? Submit your BOM (48h)
Siblings: Battery Charger PMIC · eFuse/Hot-Swap · Load Switch · Power Mux · Low-Noise LDO (RF)
Working Principle: ET Waveforms, APT Mechanism, and Linearity Path
RF PA linearity depends on how its supply rail follows the modulation. Envelope Tracking (ET) drives a fast rail proportional to the signal envelope, while Average Power Tracking (APT) adjusts the rail more slowly to improve efficiency. Their dynamics couple into EVM and ACLR through in-band ripple, out-of-band components, and timing skew.
ET focus
- Match envelope bandwidth with rail loop bandwidth and slew rate.
- Align timing (rail vs RF) to minimize AM/AM and AM/PM error.
- Use post-LC/LDO to push residual ripple below in-band limits.
APT focus
- Optimize efficiency with slower rail movement and wider margins.
- Stabilize against DRX/Burst load steps (avoid undershoot/overshoot).
- Verify recovery in EVM/ACLR during traffic peaks.
Design Rules: Loop Bandwidth, Zout(f), fSW & Sync, Spread-Spectrum, Decoupling
Shape the rail so that in-band noise stays below the PA linearity budget while out-of-band content is filtered by LC and the PA chain. Then pick fSW and sync to avoid beating into the channel.
Loop bandwidth & stability
- Set loop bandwidth ≤ 1/3–1/5 of the effective envelope bandwidth.
- Target ≥ 45–60° phase margin; check for peaking in Bode and time-domain ringing.
- Validate with load-step + spectrum + EVM/ACLR captured at the same conditions.
fSW, sync & spread-spectrum
- Avoid carrier, subcarriers, symbol and sampling clocks and their beats.
- Sync rails to a common reference; stagger phases across rails to reduce beating.
- Use spread-spectrum only if spectral energy does not encroach in-band/adjacent channels.
Decoupling, magnetics & LDO
- Parallel caps of varied values/ESR; place closest at PA pins; add RC/π damping if needed.
- Select inductor ripple ΔI ≈ 20–40% of Iload; check saturation and thermal drift.
- Use an LDO post-stage to enforce in-band ripple targets; keep dropout margin at worst case.
Layout & EMI: Hot Loop, Kelvin Sense, Ground Returns, Shielding & Routing
Focus on the RF-PA supply path only: minimize the hot loop, use true Kelvin sense to the PA pins, manage RF vs digital returns with a single-point tie, and route sensitive bias/PG lines away from the SW node.
Hot loop & decoupling
- Close the SW–L–Cin loop; place small MLCCs at the switch and PA pins.
- Keep the SW copper short and internal if possible; avoid long exposed traces.
- Use damping (RC/π) where ringing pollutes in-band ripple.
Kelvin sense & grounds
- Sense at the PA pins (post-LDO/LC) to preserve Zout(f) targets.
- Star/bridge RF-to-digital grounds; avoid split-plane gaps under high-frequency returns.
- Fence shields with short pitch; stitch vias around the PA island.
Routing discipline
- Route bias/PG/telemetry far from SW; guard with ground if needed.
- No signal routes under the inductor; keep LC–LDO as a short, direct loop.
- Phase-stagger multi-rails to reduce beating into CE bands.
Validation & Debug: EVM/ACLR, CE 150 kHz–30 MHz, Beating, Burst/Load-Step, VSWR
Validate linearity and emissions together: capture the rail’s waveform + spectrum alongside EVM/ACLR, then scan 150 kHz–30 MHz for conducted peaks near fSW and its harmonics.
EVM / ACLR
- Log rail waveform + spectrum together with EVM/ACLR for the same burst.
- Map: in-band ripple → EVM; out-of-band/sidebands → ACLR.
- Re-check after sync phase changes and LC/LDO tweaks.
CE 150 kHz–30 MHz
- Correlate peaks to fSW and its harmonics or beats with RF clocks.
- Tune in order: sync/phase → damping/LC → input π → routing edits.
- Stagger phases across rails to reduce summed tones.
Burst / Load-Step / VSWR
- Measure undershoot/overshoot and recovery time during DRX/DTIM.
- Test VSWR 3:1 and extremes; verify OCP/Foldback/T limits and recovery.
- Archive plots per condition for fast regression and DPD tuning.
Still unsure how to validate sync choices and in-band ripple for your PA? Submit your BOM (48h)
Applications: Handset PA, Small Cell / RRH, Wi-Fi AP, IoT PA Modules, Automotive T-Box
Choose a topology and validation focus per scenario. Each card lists a recommended rail, key KPIs, design notes, and common pitfalls so your RF PA supply meets EVM/ACLR and conducted emissions goals with predictable effort.
Handset PA
Compact layouts, tight thermal budgets, and premium EVM at high MCS. Prefer APT with optional ET on flagship tiers.
- KPIs: ΔV@Tx burst, EVM in-band, idle Iq, skin-temperature.
- Notes: shortest LC–LDO loop; sync fSW; small MLCC at PA pins.
- Pitfalls: over-exposed SW copper; LDO dropout too small; no true Kelvin.
Small Cell / RRH
High current rails with telemetry and protection. Use APT/ET with clock sync and dual-stage filtering.
- KPIs: Ipeak, Zout(f) in-band, ACLR under multicarrier, thermal rise.
- Notes: phase-stagger rails; VSWR 3:1; cable drop compensation.
- Pitfalls: unsynchronized rails; PG chain gaps; connector heating.
Wi-Fi 6/7 AP
OFDMA makes in-band ripple sensitive; CE limits are strict. Favor synced APT with short post-filter.
- KPIs: ΔV@DTIM, EVM at high MCS, CE peaks around fSW.
- Notes: avoid spread-spectrum encroaching adjacent channels.
- Pitfalls: wrong input π placement; no damping on LC ringing.
IoT PA Module (NB-IoT / LTE-M)
Large battery ESR and sharp bursts. A slow APT rail with generous capacitance protects EVM.
- KPIs: undershoot/overshoot, recovery, sleep Iq.
- Notes: size C for cold ESR; ensure LDO margin at min VIN.
- Pitfalls: ignoring harness drop; dropout on peaks.
Automotive T-Box
Survive cold-crank and load-dump; pass EMC and AEC-Q100. Sync rails and reinforce in-band filtering.
- KPIs: EVM/ACLR vs temperature, CE/EMC, thermal headroom.
- Notes: robust PG/FLT; thermal vias and copper spread.
- Pitfalls: missing automotive transients; undersized heat path.
Still unsure which PA supply topology fits your platform? Submit your BOM (48h)
IC Selection: Function Buckets & Brand Mapping (Fields Only)
We don’t list part numbers here. Instead, use these function buckets and data fields to request a cross-brand short-list that fits your EVM/ACLR and CE targets.
ET PMIC
- VOUT range & DAC resolution; envelope BW & delay alignment
- Peak/avg current capability; slew rate
- Sync range; spread-spectrum (if any)
- Protection: OCP/OVP/OTP; PG/FLT
Active brands in mobile & small-cell ET space.
APT Buck / Boost
- VOUT range; Iavg/Ipeak/transient rating
- fSW & sync window; phase-stagger support
- Ripple & noise vs load; efficiency
- Foldback & soft-start; telemetry options
Strong coverage across handset, Wi-Fi AP, and base-station rails.
RF Bias / −Vg / Sequencer
- Bias voltage range & resolution; leakage
- Programmable sequencing; delays & dependencies
- Interfaces (I²C/SPI); PG/enable logic
- Noise density & PSRR in band
VGA/LNA/PA biasing and gate protection focused vendors.
Low-Noise LDO (Post-Rail)
- PSRR at target bands; noise density
- Dropout at worst VIN; thermal resistance
- Iq in sleep/Tx; start-up behavior
- Stability with MLCC; damping guidance
RF-tuned LDO lines for in-band shaping.
Power Sequencing & Telemetry
- PMBus / I²C / SPI; voltage/current/temperature readback
- PG/FLT granularity; fault logging
- Sync/phase control; multi-rail coordination
- AEC-Q100/industrial grades; package & thermal
System controllers used in RRH and automotive telematics.
Unified Data Fields to Collect
- Path type (ET / APT / Buck→LDO), VOUT range & resolution, Iavg/Ipeak/transient
- fSW range, sync window & phase control, spread-spectrum (Y/N)
- Ripple/noise (in-band & out-of-band), target Zout(f) points
- Protection (OCP/OVP/OTP), soft-start/slew, PG/FLT granularity
- Telemetry (V/I/T) and bus (PMBus/I²C/SPI); logging
- LDO PSRR vs frequency, noise density, dropout, Iq
- Package & thermal (RθJA, copper area), AEC-Q100/industrial/commercial
- Reference designs & evaluation board availability
Still unsure which PA supply & bias PMIC fits your design? Submit your BOM (48h)
FAQs
When should I choose ET instead of APT for my PA rail?
Use ET when peak linearity and efficiency at high PAPR are critical, and you can meet envelope bandwidth, delay alignment, and rail slew requirements. Choose APT when simplicity and lower ripple matter more than instantaneous headroom. See Working Principle and Design Rules for trade-offs.
How do I set loop bandwidth relative to the modulation envelope?
Start with loop bandwidth ≤ one-third to one-fifth of the effective envelope bandwidth to balance tracking and stability. Confirm ≥45–60° phase margin and check time-domain ringing. Correlate Bode peaking with EVM changes under traffic. See Design Rules.
What Zout(f) profile should I target for in-band performance?
Aim for low Zout across the in-band region using an LDO post-stage and damping, then let LC handle out-of-band roll-off. Validate with load-step plus spectrum and map to EVM/ACLR. See Design Rules and Architecture.
How do I pick fSW and avoid beating with RF clocks?
Place fSW away from carrier, subcarriers, symbol and sampling rates, then sync the converter to a stable reference. Stagger phases across multiple rails to reduce summed tones. Re-verify CE peaks after changes. See Design Rules and Validation & Debug.
Is spread-spectrum switching safe for Wi-Fi 6/7 or 5G NR?
Only if measured energy remains outside in-band and adjacent channels. Spread-spectrum widens spectral content that can creep into ACLR masks. Validate with CE scan and on-channel EVM. Prefer sync and phase management first. See Design Rules and Validation.
How does rail ripple map to EVM and ACLR degradation?
In-band ripple perturbs PA gain/phase, increasing EVM. Out-of-band tones and beats fold as sidebands that raise ACLR. Capture rail waveform and spectrum time-aligned with RF metrics to diagnose. See Working Principle and Validation.
Why must Kelvin sense land at the PA pins, not at the LDO?
Sense at PA pins to remove IR drop in traces and vias from the regulation loop, preserving the intended Zout(f) at the device. Incorrect sense points inflate ripple and undermine linearity. See Layout & EMI.
How do I define and shrink the hot loop around the SW node?
Draw the high-di/dt path (HS switch → inductor → input caps → back to switch). Place MLCCs tight, keep SW copper short and internal, and avoid routing signals beneath the inductor. Add damping where needed. See Layout & EMI.
What’s the right order to tune conducted emissions (150 kHz–30 MHz)?
First synchronize rails and set phase, then adjust LC and damping, next add input π if necessary, and finally refine routing/grounding. Map peaks to fSW harmonics or beats to confirm fixes. See Validation & Debug.
How should I test burst/DRX or DTIM load steps for IoT and Wi-Fi?
Record undershoot/overshoot and recovery time while simultaneously logging EVM/ACLR. Size capacitance for cold ESR, and keep dropout margin at worst VIN. Re-test after sync/phase changes. See Applications and Validation.
How do I measure and document VSWR mismatch resilience?
Test 3:1 and corner cases while monitoring rail ripple, temperature, and PA protection (OCP/Foldback/thermal). Log recovery behavior and thresholds for audits. See Validation & Debug.
How much LDO dropout margin do I need on the post-rail?
Ensure the LDO maintains regulation across cold crank/battery sag and peak currents. Validate at minimum VIN with temperature corners, and confirm PSRR at target bands. See Design Rules and Applications.
What fields should I collect before asking for a cross-brand short-list?
Capture path type, VOUT range/resolution, Iavg/Ipeak, fSW/sync, ripple/noise targets, Zout(f) points, protections, telemetry, LDO PSRR/noise/dropout, package/thermal, and certifications. See IC Selection.
How do I align rail delay with the RF envelope in ET systems?
Calibrate rail timing versus the RF path so the envelope and carrier align at the PA. Mismatch produces AM/AM and AM/PM errors that DPD may not fully remove. Verify with time-aligned captures. See Working Principle.
Resources & CTA
Send us your rail targets and constraints. We’ll return a cross-brand recommendation within 48 hours based on the function buckets and data fields outlined above—no PDFs required.
Submit your BOM (48h)Siblings: Battery Charger PMIC · eFuse / Hot-Swap · Load Switch · Power Mux · Low-Noise LDO (RF) · PMIC Home
We keep shared schematics confidential.
