← Back to Low Dropout Regulators (LDOs)
This page focuses only on RF front-end / PA bias rails that need an LDO to clean up switching ripple, protect phase-noise performance, and recover quickly after RF or PA events. It is not about audio LDOs, automotive AEC-Q100 LDOs, or rad-tolerant/space LDOs. Those topics should go to their dedicated pages to avoid content overlap.
Introduction & Scope
Typical targets: LNA, mixer, PLL/VCO, small-cell or Satcom PA bias, TDD/slot switching, DPD or envelope-driven PA stages. In these cases, the LDO is placed right before the RF/PA device to suppress high-frequency components coming from a DC-DC stage. Efficiency can be slightly sacrificed in exchange for high-frequency PSRR and phase-noise-friendly behavior.
Because the upstream supply is usually a switching regulator, the PSRR we care about is in the 100 kHz – a few MHz range, including harmonics and system reference tones. That is why this page treats RF LDOs differently from “generic low-noise LDO” guides.
RF-Oriented Power Noise Model
For RF rails, the power path is DC-DC → LDO → RF block. Each stage contributes to the final noise that the RF device will see. Unlike generic analog loads, RF front-ends care about ripple and spurs near the RF, LO, and reference frequencies, not only at 100 Hz or 1 kHz.
Therefore, the LDO you pick must show useful PSRR at these frequencies: the switching frequency of the DC-DC (often 400 kHz–2 MHz), its 2nd/3rd/5th harmonics, and any PLL/IF-related tones already present in the system. If the LDO’s high-frequency PSRR has already rolled off, those tones will leak straight into the RF rail and appear as phase-noise or unwanted spurs.
Next sections will map these noise points into concrete selection criteria (PSRR@100k/1M/10M, noise spectrum, recovery time).
Selection Criteria for RF/PA LDO
RF-oriented LDOs are selected differently from generic low-noise parts. Here we assume the rail is DC-DC → RF/PA bias LDO → RF front-end / PA, so high-frequency PSRR and fast recovery are higher priority than minimal Iq. Use the criteria below in this order.
1) Noise spec — check the right band
Many LDO datasheets show noise only in the 10 Hz – 100 kHz band. For RF/PA rails, you should also verify noise and PSRR in the 100 kHz – 10 MHz region, because that is where switching supplies, LO/reference tones, and IF-related signals sit. If the datasheet does not show it, plan for board-level measurement in the validation phase.
- PLL / VCO sensitive band: 10 Hz – 1 MHz
- DC-DC related band: 100 kHz – 2 MHz (and harmonics)
- RF / IF related: device-specific tones to be checked
2) PSRR @ 100 kHz / 1 MHz / 10 MHz
RF rails must attenuate the switching fundamental and its high-order products. Treat any LDO that has already rolled off by 1 MHz as non-RF for this page.
- @100 kHz: rejects most control-loop and digital switching noise
- @1 MHz: rejects typical DC-DC switching frequency and its ringing
- @10 MHz: rejects harmonics, clock/LO sidebands and RF-coupled noise
Later in the IC matrix we can tag parts with PSRR_100k / PSRR_1M / PSRR_10M fields for fast filtering.
3) Recovery / settling time for PA / TDD events
PA bias, TDD slot change, or TRX switching can cause a rapid load step. The RF LDO must return to its window quickly (for example, ±2 %) within a defined time at the given current step. If the datasheet does not specify it, scope it on the target RF board with real decoupling in place.
Recommended wording for validation: “Recover to ±2% of VOUT within ≤X µs for a +Y mA step, with RF decoupling mounted.”
4) Bias current / Iq / headroom / dropout
Unlike ultra-low-Iq battery nodes, RF rails can trade some quiescent current to keep high-frequency PSRR alive. Check:
- Iq <= your thermal / standby budget for the RF island
- Headroom: VIN from DC-DC to LDO dropout must cover PA bias at worst case
- Dropout @ Imax: if dropout is too high, place the LDO nearer to the RF DC-DC stage or raise VIN
5) Package & placement (close to PA / RFIC)
RF LDOs often need to sit inside the RF zone. Choose packages that can be placed close to the PA/RFIC bias pin, with short traces and local ground via stitching. Small packages are good, but check RθJA and derating because PA rails can run hot when RF activity is dense.
Stability & Layout on RF Boards
RF boards are usually built with low inductance, short traces, and a solid ground plane. This is good for RF performance, but it can shift the LDO’s pole/zero locations and destabilize parts that rely on a certain ESR or minimum output capacitance. In this section we fix that.
1) Small inductance, short runs, ground plane
Place the RF LDO and its required output capacitor very close to the PA/RFIC bias pin. Keep the power loop short and stitch the ground right next to the capacitor. This keeps the RF supply impedance low but also means the LDO will “see” a very low-ESL, low-impedance network — re-check stability in this condition.
2) RF decoupling (C0G, X7R) vs LDO compensation
RF devices often require a very close C0G 100 nF or 220 nF capacitor. The LDO, however, may require 4.7 µF or 10 µF X7R with a specific ESR window. Use both:
- place the LDO-required capacitor at the LDO output first
- place the RF-only C0G/X7R right at the RF/PA pin
- re-measure loop stability with both caps in place (after reflow)
3) Separate sensitive analog/RF ground from power ground
Keep the RF/analog return quiet and tie it to the power ground at a single, controlled point — usually near the LDO return or near the PA return. Avoid probing PSRR across different ground zones as it can hide real problems.
PA Bias Events & Fast Recovery
This section covers the events that make an RF/PA bias LDO look “slow” even when its datasheet looks fine. We focus on (1) TDD / slot changes, (2) envelope or DPD peaks, and (3) using PG / EN to control the rail so that the PA does not come up before the LDO is clean.
1) TDD / slot switching transients
When the PA moves from idle / RX to TX, the bias current can jump from tens of mA up to a few hundred mA. The RF LDO must return to its window (for example, ±2% of VOUT) in microseconds, not milliseconds. If you do not see this number in the datasheet, you must measure it on the target RF board.
2) Envelope / DPD power hold-up
With envelope tracking or DPD, the supply rail sees repeated high-power bursts. The LDO must keep its high-frequency PSRR at those instants; otherwise, the PA sees residual switching tones from the DC-DC. This is why we selected parts with good PSRR at 100 kHz, 1 MHz and even 10 MHz (for example, TI TPS7A52-Q1 and TPS712xx RF LDO family). :contentReference[oaicite:0]{index=0}
3) Rail control with PG / EN
Prefer LDOs with a PG / POK pin or with independent EN on each rail. Tie the PA’s enable to the LDO’s PG, or have the baseband / RF controller check PG before enabling TX. onsemi’s NCP59801 and NCP59800 expose a Power-Good output specifically for RF and sensitive analog circuits. :contentReference[oaicite:1]{index=1}
Mini IC Matrix — RF / PA Bias LDO (7 brands)
Real, shipping parts as of October 30, 2025, based on public datasheets or product briefs. Focus is on LDOs explicitly described as low-noise / high-PSRR / RF / sensitive analog, or on PMIC LDO rails that NXP exposes for radar / ADAS RF blocks. :contentReference[oaicite:2]{index=2}
| Brand | PN / Family | Key RF Reason | VIN / VOUT | IOUT | PSRR notes | PG / EN | Placement |
|---|---|---|---|---|---|---|---|
| TI | TPS71202 / TPS71247 (dual 250 mA RF LDO) :contentReference[oaicite:3]{index=3} | Tailored to noise-sensitive and RF applications; fast start-up | 2.5–6 V in / 1.2–5.5 V out | 2 × 250 mA | High PSRR to MHz, stable with 2.2 µF | Dual EN pins | Place in RF island near PA / RFIC |
| TI | TPS7A52-Q1 (2 A) :contentReference[oaicite:4]{index=4} | Low-noise 4.4 µVRMS, high-frequency PSRR, automotive grade | 2.7–6.0 V in / 0.8–5.2 V out | 2 A | Good PSRR at 1 MHz for DC-DC → LDO chains | EN | Use for high-power PA bias |
| ST | LDLN025 (250 mA ultralow-noise) :contentReference[oaicite:5]{index=5} | Designed for VCO / RF modules; clean output, high PSRR | 1.5–5.5 V in / fixed & adj. | 250 mA | High PSRR in RF-relevant band | Shutdown pin | Closest to VCO/PA, with required COUT |
| ST | LD56050DPU110R (500 mA, low dropout) :contentReference[oaicite:6]{index=6} | For higher PA bias current, still low noise | 2.5–5.5 V in / 1.1 V out | 500 mA | PSRR suited for DC-DC post-reg | EN | Place on RF side, short trace |
| NXP | PF5103 — LDO1 / LDO2 for ADAS/RF rails :contentReference[oaicite:7]{index=7} | PMIC level LDOs used with radar / vision SoCs; sequenceable | 0.5–3.3 V domain | up to 300–500 mA (per LDO) | Good HF rejection for ADAS/radar processors | I²C-config EN / sequencing | Use when platform already uses PF51x3 PMIC |
| NXP | PF5113 — LDO_A / LDO_B for radar front-ends :contentReference[oaicite:8]{index=8} | Targeted at S32R41 / TEF82xx / SAF85xx radar systems | programmable via I²C | platform dependent | Sufficient PSRR for radar/RF processors | I²C / OTP sequence | Place near radar/RF SoC power island |
| Renesas | ISL80510 (1 A high-performance LDO) :contentReference[oaicite:9]{index=9} | Fast transient, 2.2–6 V in, 0.8–5.5 V out, good for sensitive loads | 2.2–6 V / 0.8–5.5 V | 1 A | PSRR up to a few MHz (check board) | EN | Use for larger PA or multi-channel RF cards |
| Renesas | ISL9008AIECZ / ISL9000A family (low noise) :contentReference[oaicite:10]{index=10} | Low-noise LDOs for analog/RF section | typ. 2.3–6 V / 1.5–3.3 V | 150–300 mA | High PSRR in low–mid band; check layout for HF | EN | Close to PLL / RFIF |
| onsemi | NCP59801 (1 A, high PSRR, PG) :contentReference[oaicite:11]{index=11} | Datasheet explicitly: “for RF and sensitive analog circuits” | 1.6–5.5 V in / 0.6–Vin-Δ out | 1 A | High PSRR, good load/line transient | Power Good (open collector) | Perfect for PG→PA EN rail control |
| onsemi | NCP164 / NCP163 (300 mA, ultralow-noise) :contentReference[oaicite:12]{index=12} | Small current RF/analog rails | 1.6–5.5 V / up to 3.3 V | 300 mA | High PSRR, low noise | EN | Close to RFIC / PLL island |
| Microchip | MIC94310-4YM5-TR (200 mA, Ripple Blocker) :contentReference[oaicite:13]{index=13} | Provides switching noise rejection to a regulated output; explicitly for RF where DC-DC noise cannot be tolerated | up to 3.6 V in / fixed out | 200 mA | Rejection across 100 Hz–10 MHz band | EN | Use as last stage right at RF block |
| Microchip | MIC94300 series (LDO + current limit + LPF) :contentReference[oaicite:14]{index=14} | Good for DC-DC → LDO → RF with inrush control | to 3.6 V | up to 200 mA | Switching noise rejection integrated | EN | Place closest to RF load |
| Melexis | — (no dedicated RF/PA LDO identified) | Use TI TPS71202 or onsemi NCP59801 as companion LDO for Melexis RF / sensing chains | — | — | Pair with high-PSRR device above | Follow main LDO PG/EN | Co-locate on RF island, short traces |
Frequently Asked Questions — RF / PA Bias LDO
How do I choose an LDO for RF/PA rails instead of a generic low-noise LDO?
Start from high-frequency PSRR (@100 kHz, @1 MHz, and if possible @10 MHz), then check fast recovery under PA/TDD steps, and only then look at Iq and package. A generic low-noise LDO that rolls off by 1 MHz is not suitable for a DC-DC → RF/PA chain.
What PSRR level do I actually need at 1 MHz when the upstream is a DC-DC?
You need enough PSRR at 1 MHz to bury the switching ripple and its ringing below the RF sensitivity floor — typically 40 dB+ at 1 MHz for clean PAs and PLLs. If the chosen LDO has rolled off by 1 MHz, switch to an RF-intended part like TPS712xx or NCP59801 and re-measure on board.
How fast should the LDO recover after a TDD or PA bias step?
Target microsecond-class recovery back into ±2% of VOUT at the actual PA load step you use in the slot change. Always test with RF decoupling mounted, because extra C0G/X7R changes the loop. Millisecond recovery is too slow for real TDD/DPD radios.
Can I gate the PA enable with the LDO PG pin?
Yes, and it is recommended. Tie PA EN or RFIC TX-enable to the LDO PG/POK so the PA never starts on a sagging rail. onsemi RF LDOs with PG and TI dual RF LDOs make this easy — just add the right pull-ups and you have deterministic sequencing.
What if the RF LDO datasheet does not show PSRR at 10 MHz?
Measure it on the real RF board with the exact capacitors and layout. At 10 MHz, parasitics dominate, so vendor curves may no longer match. If it looks poor, add the RF-only C0G at the PA pin or switch to a ripple-blocking LDO such as MIC94310.
Do I need separate LDOs for PLL/VCO and for PA bias?
In high-performance radios, yes. PLL/VCO wants the quietest band at low–mid frequencies; PA bias wants current steps and high-frequency PSRR. You can use a dual RF LDO in one package, but keep the rails decoupled and check crosstalk under PA bursts.
Why does my RF board oscillate only after reflow?
After reflow, small X7R MLCCs lose capacitance and ESR, so the LDO no longer “sees” the capacitor window it was designed for. Add the required output cap near the LDO and leave the RF C0G near the PA pin; then re-check phase margin.
How close should I place the RF LDO to the PA / RFIC?
Same RF island, same layer, short and wide trace, and ground stitching around the output capacitor. The LDO-required capacitor stays with the LDO; the RF-only capacitor stays at the PA pin. Long routes between them make the loop harder to stabilize.
Can I cross TI → onsemi or TI → Microchip when stock is tight?
Yes, but re-validate PSRR at 1 MHz, EN/PG polarity, and package thermals. TI TPS712xx → onsemi NCP59801 → Microchip MIC94310 is a typical chain, but each has slightly different start-up and decoupling requirements. Always run the RF board test again.
What should I tell the supplier when I submit a small BOM for RF LDOs?
Tell them it is an “RF / PA bias rail behind a DC-DC” and that you need high PSRR at 1 MHz, fast recovery, and an EN/PG pin for rail control. Without that, they may send you a cheaper generic LDO that fails under slot switching.
How do I test high-frequency PSRR on the actual RF board?
Inject ripple/noise at the DC-DC output, keep the real RF decoupling in place, probe at the LDO output ground, and sweep across 100 kHz–10 MHz. If PSRR collapses only on the board, your layout or capacitor stack is the cause, not the silicon.
Why do some RF LDOs draw more Iq than general-purpose parts?
Because they keep their error amplifier and internal filters active at high frequency to sustain PSRR and ensure fast recovery. It is a deliberate RF trade-off — you spend some current to keep the rail clean during PA bursts.
Can I share one RF LDO between LNA and PA bias?
Only if the LDO has dual outputs or you add RC isolation. PA bias steps can couple into the LNA and raise the noise floor. In most RF boards it is cleaner to dedicate one LDO to the PA and another to the sensitive receive path.
Can an RF LDO run from noisy USB / PoE front-ends?
Yes, but prefer a DC-DC pre-regulator and then the RF LDO, or use a ripple-blocking LDO like Microchip MIC94310. Directly from USB/PoE the LDO will have to work harder and you must check thermal headroom and dropout.
