Architectures (Integer-N / Fractional-N / DDS+PLL / ext-VCO / mmWave), VCO types, key loop blocks, specs (phase noise, jitter, spurs, lock time), application targets, spur/noise mitigation, frequency planning, design hooks & pitfalls, quick cheats, and typical pairings.
Architectures
Integer-N PLL
Low spurs; step size = fREF; great for fixed/channelized LOs.
Fractional-N PLL
Fine step & fast lock; manage ΣΔ noise and fractional spurs.
Integrated VCO Synthesizer
On-chip LC-VCO with dividers/buffers; compact with isolation/PN trade-offs.
External VCO + Divider
Higher f and lower PN; needs careful layout/shielding.
DDS or DDS+PLL
Micro-step with wide tuning; handle close-in spurs and image products.
Multi-Core / Quadrature LO Gen
I/Q & array LOs with phase matching and cross-coupling isolation.
mmWave LO with Multipliers
×2/×3 chains plus filtering; balances power and phase noise.
Reference & Jitter Cleaner
TCXO/OCXO/MEMS with on-board jitter cleaners to feed RF PLLs.
VCO Types
LC-Tank VCO
Best PN, mid tuning range; on/off-chip inductors.
Ring VCO
Very wide tuning with higher noise; good for broadband/low-power SoCs.
YIG / DRO
Ultra-low PN for microwave instruments; larger size/cost.
Switched-Cap / Varactor Bank
Linearize KVCO and avoid dead-zones/notches.
Key Blocks
PFD / Charge Pump
Dead-zone/leakage/mismatch drive ref spurs; match currents & add bleed.
Loop Filter (Passive/Active)
Poles/zeros set BW & margin; sensitive to EMI/coupling.
Divider / Pre-Scaler
Jitter/delay & routing coupling; sync vs async trade-offs.
LO Buffer / Splitter
Isolation/drive and leakage paths blocking to RF ports.
Reference Mult/Div
Raise fPFD to lower ΣΔ noise; balance ref spurs & lock time.
Key Specs & Selection
Phase Noise
Offsets at 1k/10k/100k Hz; near/far-out impact on EVM/ACLR.
RMS Jitter
Integration window dependent; derive from EVM for wideband links.
Step Size & Tuning Range
Channel raster and hop/switch timing.
Spurs
Ref/integer-boundary/fractional/mixer images; adjacent-channel limits.
Lock Time
Settle frequency & phase for hops and beamforming sync.
Output Level / Impedance
SE/differential options to drive mixers/distribution nets.
Supply & Isolation
PSRR, sensitive-node decoupling, analog/digital ground split.
Application-Focused
Cellular / 5G NR
Frac-N with DPD feedback; PN/spurs limit ACLR/EVM.
Wideband SDR / Test
DDS+PLL micro-steps; fast locks with low close-in PN.
Microwave / mmWave Radar
Multiplier chains with low close-in PN and linear sweeps.
Phased-Array / Many TRx
Shared ref + local PLLs; manage leakage and crosstalk.
SATCOM / Backhaul
Ultra-low PN, drift/aging control and loop redundancy.
Spur & Noise Mitigation
Higher fPFD
Cuts ΣΔ quantization-noise density and fractional spur levels.
DSM Order & Dither
Higher order + dither to spread fractional sidebands.
CP Matching / Bleed
Bleed current for linearity and integer-boundary spur relief.
KVCO Linearization / Banking
Stabilizes loop gain and avoids out-of-band ripple.
Supply & Isolation
Independent LDOs/filters; keep LF and VCO away from digital noise.
Reference Clean-Up
Low-noise refs + jitter cleaners; spur-filter networks.
Frequency Planning
Image / LO Planning
Pick IFs to avoid LO±n·fREF sensitivities.
Integer-Boundary Avoidance
Tweak ref or ratios when fLO≈M·fREF.
Mul/Div Chains
Multipliers raise PN by 20·logN (ideal); dividers reduce by same.
Multi-LO Isolation
Partitioning, shields/ground slots and coupled-path monitoring.
Design Hooks & Pitfalls
Loop BW & Stability
Wider BW locks faster but rolls up ref noise; target ζ≈0.7, PM≈50–70°.
Loop-Filter Layout
Shortest grounds, far from switching rails; star grounds and guard rings.
Reference Path
Differential/controlled-Z; no return across splits; matched RC if needed.
LO→RF/IF Leakage
Keep symmetry/balance; detect with couplers; terminate & shield.
Thermal & Mechanical
VCO is temp/stress sensitive; avoid screws/pressure and large gradients.
Digital Proximity
Keep ΣΔ/dividers/MCU clocks away from VCO tank; cross-decouple supplies.
Fast Hopping
Preset cap banks & preload loops with out-of-band pre-charge.
Quick Cheats
Divider on PN
Ideal divide-by-N → PNout ≈ PNin − 20·log10(N) dB.
Phase-Noise → Jitter
Choose [f1,f2] window (e.g., 12 k–20 MHz for W-CDMA) to integrate L(f).
Free Parameters Triangle
Raise fPFD, increase ICP, right-size KVCO & LF RC to balance lock-time/PN/spurs.
Integer-Boundary Spurs
When fLO≈M·fREF, avoid or use bleed/phase re-mapping.
Pairings
With Clock Jitter-Cleaner
Keep SYSREF/sample-clock cleaning separate; RF LO only synthesizes frequency.
With PA Linearization
DPD/ET need low close-in PN; match delay & gain in the feedback loop.
With Mixers & Filters
Plan images/spurs early; leave VGA/DSA headroom for blockers.
