← Back to: Supervisors & Reset
Why Self-Test Matters
Build a repeatable, measurable self-test loop around three paths—thresholds, reset, and watchdog—to raise first-pass yield, reduce false resets, and cut FRU recovery time. This page is scoped to detectability and testability for those three paths only (no multi-rail sequencing, reset tree fanout, or RTC details here).
Failure Modes
- UV/OV drift; window threshold chatter
- Late/early reset; delay instability vs ramp
- WDT feed errors (early/late/missed)
- Reset-cause overwritten or lost
- Temp drift and ripple coupling
Detectability Matrix
Stimuli: DAC steps / ladder / source-measure
Observables: PG / RESET / WDT / local log
Metrics
- Coverage = detected / key failure cases
- False-reset rate (per hour)
- Critical-point repeatability (σ / Hyst)
- FRU self-test elapsed time
Target KPIs: false-reset rate < 1e-6/h; 3σ of trip point ≤ 30% of Hyst; field FRU self-test ≤ 2 minutes.
Threshold Injection Basics
Inject UV/OV/window thresholds, hysteresis and delay without disturbing rail impedance or loop stability. We cover single-rail techniques (no multi-rail dependencies here).
Trip point model:
V_trip(actual) = V_set × (1 ± Acc%) ± ΔT × (ppm/°C) ± Tol_divider ± I_in × R_src
“No-chatter” hysteresis rule-of-thumb:
Hyst ≥ 1.5 × max( V_ripple(pk-pk), V_ramp_noise )
SOP
- Programmable DAC → isolation switch → divider node (or SMU sweep)
- Bypass/decouple large caps or add series isolation to protect phase margin
- Measure up- and down-sweeps, record trip and retrip to get Hyst
- Add ripple 20–50 mV @ 100–500 kHz and repeat
- Test −40/25/85/125 °C; ≥10 reps per point for mean/σ
- Separate delay vs voltage by re-running at slow (1–5 mV/ms) and fast (≥100 mV/ms) ramps
Acceptance
- Up/down delta ≤ 40% of Hyst
- Injection path induced error ≤ 0.5% × V_set
- No false resets at max ripple or within project PPM budget
Pitfalls → Fix
- Injection loading → buffer/high-Z source; cross-check with bypassed path
- Divider leakage/offset → evaluate I_in × R_src; consider buffer
- Ripple injected upstream → inject at the DUT node, not only at the source
- Delay misread as drift → compare slow vs fast ramps at the same setpoint
| Rail | V_set | Acc% | ppm/°C | Hyst | Delay | V_trip↑ | V_trip↓ | Δ(V↑−V↓) | Temp (°C) |
|---|---|---|---|---|---|---|---|---|---|
| VDD_5V | 4.65 V | ±1.0% | 50 | 60 mV | 20 ms | 4.66 V | 4.60 V | 60 mV | 25 |
| VDD_3V3 | 3.10 V | ±1.5% | 70 | 40 mV | 15 ms | 3.13 V | 3.09 V | 40 mV | -40 |
Automated Sweeps & Coverage
Establish a fully automated plan that spans three axes—ramp slope, temperature, and ripple—to quantify stability and jitter of trip point, hysteresis, and delay. We only measure detectability quality here; higher-level restart behavior is out of scope.
Recommended DoE
- Ramp: slow 1–5 mV/ms; fast ≥100 mV/ms
- Ripple: 20 / 35 / 50 mV (pk-pk) at 100–500 kHz
- Temp: −40 / 25 / 85 / 125 °C
- Repeats: ≥10 per point (borderline: 30)
Recorded Metrics
- V_trip↑, V_trip↓, Hyst = V_trip↑ − V_trip↓
- Reset/PG delay distribution (mean/σ)
- Chatter (toggle counts), false resets, late/early reset events
Pass/Fail Criteria
- 3σ ≤ 0.3 × Hyst
- Chatter = 0; false resets = 0
- Late/Early reset within spec or project PPM limit
Automation hooks: SCPI control of SMU/function generator (ripple), electronic load, and temperature chamber. Export CSV/JSON per sweep ID with timestamps. Use scope/datalogger triggers to collect trip markers and build result bins.
| Sweep ID | Ramp (mV/ms) | Ripple (mV@kHz) | Temp (°C) | V_trip (mean/σ) | Chatter count | Pass/Fail |
|---|---|---|---|---|---|---|
| SP-001 | 3 | 20@200 | 25 | 4.642 V / 6 mV | 0 | Pass |
| SP-002 | 120 | 50@400 | 85 | 4.651 V / 9 mV | 0 | Pass |
Watchdog Fault Injection
Validate simple WDT and windowed WDT under early, late, and missed feeds. The goal: illegal feeds must reset; legal feeds never false-trigger; reset latency stays within spec (±10%).
Simple WDT
- Missed feed: must assert Reset/IRQ
- Early feed: allowed for simple WDT; no false reset
- Measure trigger→reset latency
Windowed WDT
- Early (forbidden window) → must reset
- Late (after open window) → must reset
- Edge jitter: legal feeds with ±Δt must not false-trigger
Acceptance
- Illegal feed pass-through = 0
- Legal feed false reset = 0
- Reset latency within ±10% of datasheet spec
Script hooks: SCPI timers + MCU timestamping; independent timebase for window-WDT; ≥10 runs per case (window edges: 30). Record reset-cause where available and verify W1C clear after persistence.
| Mode (simple/window) | Timeout (ms) | Injection (early/late/miss) | Expected | Observed | Reset delay (ms) | Pass |
|---|---|---|---|---|---|---|
| simple | 120 | miss | Reset | Reset | 118 | Yes |
| window | 80 | early | Reset | Reset | 78 | Yes |
Reset-Cause Readback & Logging
Ensure every reset has traceable evidence and a race-safe “read → verify → write-1-to-clear → persist” flow. Focus only on Supervisor/WDT/external reset cause bits; RTC/time-stamp details are out of scope.
Stage-0 Minimal Loop
- Early read: at the earliest boot point, read cause register (POR/BOR/WDT/EXT).
- Classify: map bit-fields to standard event classes; allow multi-bit combos.
- Cache-then-clear: buffer to SRAM/EEPROM/FRAM before any W1C.
- Brown-out safe: if supply unstable, write only to a ring buffer; defer commit.
- Atomic W1C: read-modify-write masks; verify by post-read.
- Persist: evidence tuple (cause_bits, source_path, boot_id, stage, crc/hash).
Acceptance (KPI)
- Single-board evidence present for any reset path
- No causal loss under brown-out (ring buffer → later commit)
- No overwrite of concurrent bits after W1C (mask verified)
Pitfalls → Fix
- Clearing before logging → cache then W1C
- Multi-bit overwrite → mask-based W1C + pre/post read
- Power-loss writes → ring buffer + CRC and replay on boot
- Late boot read → move to Stage-0, no FS dependency
| Cause bit | Meaning | W1C? | Source path | Test case ID | Persisted? | Notes |
|---|---|---|---|---|---|---|
| POR | Power-on reset | Yes | Supervisor | RC-01 | SRAM→EEPROM | Verify first boot counter |
| BOR | Brown-out reset | Yes (mask) | Supervisor | RC-02 | Ring buffer | Commit after stable PG |
| WDT | Watchdog reset | Yes (mask) | WDT block | RC-03 | SRAM→EEPROM | Check window mode flag |
| EXT | External reset pin | Yes | EXT pin | RC-04 | SRAM | Debounce duration recorded |
Production Hooks & Field Service
Convert lab self-tests into a Golden-Sequence usable on the line and in the field. ICT fixtures and FRU scripts share the same evidence model and signature format. JTAG/boundary-scan specifics are intentionally out of scope.
Factory Self-Test (FST)
- Micro-sweep: 5–7 points within ±3% of V_set (up/down) → confirm Hyst & 3σ
- WDT injection: simple/ windowed (early / miss / late)
- Cause match: observed bit-map vs expected matrix
- Signature: key values + cause_bits + version hash → store
- Failure path: step re-run → sequence re-run → reject
FRU Quick Script (≤2 min)
- 3-point threshold probe at V_set−Δ / V_set / V_set+Δ (up/down)
- 1 WDT edge-case injection (boundary of window)
- Read reset-cause; compare against expectation
- Export CSV/JSON + mini-signature; attach board temp
Acceptance (KPI)
- In-lot repeatability: 3σ ≤ 0.4% × V_set at key points
- WDT: illegal feeds reset; latency within ±10%
- Signatures: factory ↔ FRU comparable by the same schema
| Station | Step | Stimulus | Expected | Observed | Signature | Pass |
|---|---|---|---|---|---|---|
| ICT | Threshold micro-sweep | V_set±3%, 5–7 points, up/down | Hyst & 3σ within limits | Hyst=60 mV; 3σ=14 mV | ae3d… hash | Yes |
| ICT | WDT injection | early / miss / late | Reset; latency ±10% | Reset; 118 ms | b94a… hash | Yes |
| FRU | 3-point + 1×WDT + cause | ΔV around V_set; boundary feed | Match cause; pass window | Matched; latency OK | mini-sig d2f1… | Yes |
Feature Mapping (Self-Test & Diagnostics)
Use this table to shortlist parts by threshold programmability, window supervision, and WDT type, then gate by reset-cause readability, AEC-Q100 grade and package height. Notes explain why each PN fits self-test/diagnostics workflows.
| Brand | Family / PN | Threshold programmability | Window supervisor? | WDT type | Reset-cause readable | AEC-Q100 grade | Pkg height | Datasheet | Notes (why selected) |
|---|---|---|---|---|---|---|---|---|---|
| TI | TPS37-Q1 / TPS38-Q1 | Delay/Hyst pins; per-rail options | Yes (variants) | External (pair with WDT) | — | Grade 1/2 (device-dep.) | Low (SOT/DFN) | TPS37-Q1 PDF / TPS38-Q1 PDF | Window/precision UV/OV for threshold injection & delay jitter tests. |
| TI | TPS389x-Q1 (e.g., TPS3890-Q1) | Fixed/accurate; configurable delay | No | External (pair with WDT) | — | Grade 1/2 | Very low | TPS3890-Q1 PDF | Clean ±3% micro-sweep baseline; great for FRU quick checks. |
| TI | TPS386000 | Multi-rail timing/threshold config | Yes (multi-rail) | External (pair with WDT) | — | — | TSSOP | Parallel coverage for multi-rail test matrices; PG aggregation. | |
| TI | TPS3436-Q1 (Window WDT) | — | — | Windowed WDT | Status readable (MCU) | Grade 1/2 | Small DFN | Ideal for early/late/miss feed injections; “illegal feed ⇒ reset”. | |
| ST | STM703 / STM706 | Fixed thresholds; delay options | No | External (pair with WDT) | — | — | SOT-23 | STM703 PDF / STM706 PDF | uP supervisors for Stage-0 baseline; robust for ±3% micro-sweep. |
| ST | STWD100 / STWD180 / STWD912 | — | — | Independent / Window WDT | MCU readable | — | Tiny (SOT/DFN) | STWD100 / STWD180 / STWD912 | Window mode supports strict illegal-feed testing in production. |
| NXP | FS85 / FS84 / FS66 / FS56 (Safety PMIC) | I²C/Reg programmable | Yes | Windowed WDT | Yes (regs) | Grade 0/1 | QFN/LQFP | FS84/FS85 / FS66 / FS56 | End-to-end self-test with cause readback & W1C integration. |
| NXP | PF5020 / PF8100 (PMIC) | Programmable (I²C) | Per-rail windowing (family-dep.) | Integrated WDG (family-dep.) | Yes (status regs) | — | Low QFN | PF5020 / PF8100 | Multi-rail micro-sweep + PG aggregation diagnostic friendly. |
| Renesas | ISL88002/003/021/031 | Fixed/precision; delay options | No | External (pair with WDT) | — | — | SOT/DFN | ISL88002/3 / ISL88021/31 | Low-drift thresholds—great for high-temp stability sweeps. |
| Renesas | RAA271000 / RAA271082 (PMIC) | Reg programmable | Multi-rail supervision | Integrated WDG | Yes (regs + W1C) | Grade 1/2 (device-dep.) | QFN | RAA271000 / RAA271082 | Cause bits + W1C match Stage-0 evidence chain. |
| onsemi | NCP302 / NCP303 / NCP304 | Fixed; delay variants | No | External (pair with WDT) | — | — | SOT-23/SC70 | NCP302 / NCP303 / NCP304 | Cost-effective micro-sweep baseline; simple FRU scripts. |
| onsemi | NCV809 / NCV811 / NCV8110 | Fixed; automotive variants | No | External | — | Grade 1/2 | Ultra-low | NCV809 / NCV8110 | Height-restricted boards; drop-in car-grade supervisors. |
| Microchip | MIC2775 / MIC2776 (Dual supervisor) | Two thresholds; delay control | Window-like (dual rails) | External/MCU | — | — | MSOP/DFN | MIC2775 / MIC2776 | Dual thresholds useful for window-style coverage. |
| Microchip | MCP1316 / MCP1318; MCP130/131 | Fixed; some delay options | No | WDT + reset (family-dep.) | MCU readable | — | SOT/DFN | MCP130/131 / MCP1316/1318 | Combines WDT + reset path to simplify FRU sequences. |
| Melexis | MLX81116 / MLX8111x (LIN body SoC) | System-level (via regs) | System-level | Integrated WDG (SoC) | Yes (SoC regs) | — | QFN | MLX81116 | When main controller is Melexis SoC, reuse internal WDG/Diag; pair with discrete supervisor if needed. |
Tip: For second-source migration, first match RESET polarity, PG semantics, WDT window logic, then verify pins. Run the minimal golden-sequence before release.
BOM & Procurement Notes
- V_rail, n_rails, threshold tolerance (±%), Hyst/Delay
- Output type (OD/PP), WDT type (simple / window)
- AEC-Q100 grade (0/1/2…), package height
- Second source (Y/N) + pin/semantics compatibility statement
Optional: I²C/PMBus (thresholds/delays), reset-cause readable/latchable, fixture access pins (inject/measure/reset).
- Pin/semantics mismatch → map a “minimal golden sequence” first (three threshold points + 1×WDT + cause readback + W1C).
- EOL/MOQ → maintain a “second-source equivalence table” and lock the substitution priority.
- Fixture variance → standardize SCPI/CSV fields, sampling cadence and timeouts; keep a dedicated script for FRU ≤ 2 minutes.
Ready to validate with a 48-hour loop? Submit your BOM and we’ll return a cross-brand shortlist aligned to your self-test hooks.
Submit your BOM (48h)| TI | TPS38-Q1 | Window supervisor | Supports threshold micro-sweeps and delay jitter checks; clean window semantics for pass/fail bins. | Yes (grade-dep.) | Low | |
| TI | TPS3436-Q1 | Window WDT | Enforces illegal-feed ⇒ reset; perfect for early/late/miss fault injection in FST/FRU scripts. | Yes | Small DFN | |
| ST | STWD100 / STWD912 | WDT (independent/window) | Window option for strict timing acceptance; independent type for baseline miss-feed checks. | — | Tiny | STWD100 / STWD912 |
| ST | STM706 | uP Supervisor | Simple, repeatable thresholds for ±3% sweeps; ideal FRU anchor. | — | SOT-23 | |
| NXP | FS85 / FS84 | Safety PMIC (supervisor+WDT) | Registers expose status/cause; tight WDT windowing for production bins. | Grade 0/1 | QFN/LQFP | |
| NXP | PF5020 | PMIC (multi-rail) | Programmable thresholds; PG aggregation favors coverage maps. | — | QFN | |
| Renesas | ISL88021 / ISL88031 | Supervisor (precision) | Low drift helps high-temp sweep repeatability (3σ). | — | DFN/SOT | |
| Renesas | RAA271000 | PMIC + WDG | Cause bits + W1C fit Stage-0 evidence model. | Grade 1/2 | QFN | |
| onsemi | NCP302 / NCV809 | Supervisor | Fixed thresholds for quick pass/fail at ±3% points. | (NCV) Yes | Ultra-low | NCP302 / NCV809 |
| Microchip | MIC2776 | Dual supervisor | Two thresholds emulate window coverage; good for migrations. | — | MSOP/DFN | |
| Melexis | MLX81116 | SoC (LIN; WDG/Diag) | Reuse internal WDG/Diag when SoC is main controller; pair with discrete supervisor as needed. | — | QFN |
Replace each “PDF” with the official datasheet URL and keep rel="nofollow noopener". For second-source, attach your minimal golden-sequence result to the RFQ.
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FAQs — Self-Test & Diagnostics
How do I inject UV/OV thresholds without disturbing the rail impedance?
Inject with a DAC or source-measure unit through a high-impedance buffer and isolation switch into the divider node, and temporarily bypass large capacitors. Keep the stimulus equivalent source resistance ≤10% of the node impedance and bound offset via ΔV≈Iin·Rsrc ≤0.5%·Vset. Sweep up/down and repeat with ripple. See threshold-injection and table T1.
What hysteresis is “just enough” when ramps are slow and ripple is 20–50 mV?
Use Hyst ≥ 1.5×max(Vripple,pk-pk, Vramp_noise). For 1–5 mV/ms ramps, include ADC sampling jitter and comparator input noise in Vramp_noise. Acceptance: chatter count = 0 and trip 3σ ≤ 0.3×Hyst across temperature and slopes. Validate with the DoE in sweep-plans.
How do I plan up/down sweeps and choose ramp slopes to expose chatter?
Use a three-factor DoE: slow ramps 1–5 mV/ms, fast ramps ≥100 mV/ms; ripple 20/35/50 mV at 100–500 kHz; temperatures −40/25/85/125 °C. Repeat ≥10 per point, record mean/σ and chatter events. Pass when chatter = 0 and 3σ ≤ 0.3×Hyst. See sweep-plans and T2.
When should I pick ±1% vs ±1.5% threshold accuracy in automotive rails?
Build a full budget: device accuracy, divider tolerance, temp drift, and injection offset. If “3σ + aging drift” approaches 0.3×Hyst, choose ±1% to protect margins; otherwise ±1.5% improves availability and second-source options. Confirm with micro-sweeps and temperature points. See threshold-injection and BOM.
How do I translate ppm/°C into mV drift on a 5 V supervisor threshold?
Use ΔV = Vset × (ppm/°C × 10⁻⁶) × ΔT. Example: 50 ppm/°C over 100 °C on 5.00 V → 25 mV drift. Acceptance: |ΔVmeas − ΔVcalc| ≤ 30% at temperature corners. Capture results in T1 per rail and correlate with hysteresis. See threshold-injection.
What’s a safe delay/blanking to avoid false resets on pre-biased rails?
Set blanking ≥ 3× the largest RC discharge constant of the input network plus the comparator sampling window. Add “power-up inhibit” and PG de-bounce when soft-start or pre-bias exists. Acceptance: no false resets across slopes and temperatures. Validate per threshold-injection and sweep-plans.
How do I size the divider to limit leakage error on a 1 MΩ-class input?
Ensure the divider’s Thevenin resistance is small versus the input leakage: pick Rtop∥Rbot ≪ Vset/(10×Iin). Bound offset via ΔV≈Iin·Rsrc ≤ 0.5%·Vset. If power allows, buffer the divider or add a small series resistor to the sense pin. See threshold-injection.
Does OTP-fixed threshold beat I²C-programmable for stability and spread?
OTP reduces part-to-part spread and guarantees power-on determinism; programmable thresholds accelerate bring-up, multi-rail tuning, and field calibration. Typical flow: use programmable during self-test, then freeze via OTP or locked registers for production. Re-verify with the minimal golden-sequence. See brand-mapping and BOM.
How do I structure watchdog fault-injection for window vs simple WDT?
Simple WDT needs miss-feed and early-feed tests; windowed WDT defines allowed and forbidden windows, then inject early, late, and edge-jitter cases. Acceptance: every illegal feed must assert reset and reset delay must meet data-sheet ±10%. Record in T3. See wdt-fault-injection.
What’s a robust acceptance criterion for self-test pass/fail at −40~+125 °C?
Require chatter = 0 at all corners; trip 3σ ≤ 0.3×Hyst; reset delay within spec ±10%; measured drift vs calculation ≤30% at extremes. Sample size ≥10 per DoE point, logging means/σ and temperature. Gate release on these metrics. See sweep-plans and threshold-injection.
How do I log reset-cause codes so power-loss cannot erase the evidence?
In Boot Stage-0, read cause registers, classify POR/BOR/WDT/EXT, then persist to SRAM/FRAM/EEPROM ring buffer before any W1C. Under unstable power, cache to a small buffer, then commit when supply is safe. Each reset path must leave single-station evidence. See reset-cause and T4.
Can I reuse the ADC sense divider for the supervisor without skewing trips?
Shared dividers add sampling currents and alter the node’s Rsrc, shifting trip points. If reuse is necessary, use a high-impedance ADC front-end with sample-and-hold, or buffer the supervisor input. Acceptance: |ΔV| ≤ 0.5%·Vset across DoE conditions. See threshold-injection and the KPI in intro.
