Server-Class Sequencing & Supervisor: PMBus, Voting, FRU

Start with a DAG of rails and consumers, then topologically sort to obtain release order. Break feedback loops by selecting a bootstrap rail. Provide cold/warm variants, add brown-in/out guards, and document SerDes/DDR prerequisites. Export a timing table and log dependencies so audits can confirm that enables followed the declared order.

Set Min_PW to exceed the worst-case PLL lock and clock tree settle time. For synchronous domains, require Min_PW ≥ N×clk_period + margin, with N equal to your synchronizer stages. Verify across temperature and oscillator start-up variance, and measure POR flags to prove the target domain latched a full reset.

Prefer open-drain where rails span different logic levels or need wired-AND aggregation. Place pull-ups in the target island to prevent back-power. Use push-pull only for same-domain, point-to-point connections with defined level tolerance. For large fan-out, regenerate PG with level buffers to control rise times and eliminate sneak currents.

Sum DC/DC tolerance, sense-path error, ADC quantization and temperature drift to form an effective error band. Choose hysteresis ≥ noise + drift, and compensate for sampling delay. Add debounce or K-of-N voting on the comparator status so slow ramps do not generate toggling PG. Verify with worst-case ramp slopes.

Debounce each channel first using time windows or K-of-N sampling, then feed the debounced results into the voter. Select 1oo2 to maximize availability or 2oo3 to suppress false positives. Apply Min_Hold before enabling loads, and isolate channels that exceed timeout to prevent a stuck-high path dominating the vote.

Prioritize VIN, VOUT, IOUT, temperature and consolidated status bits. Keep counters for fault classes and store a rolling window of the most recent N events. Batch writes and respect your write-deadline budget so logs persist through brown-outs. Include firmware/hardware versions and board serials to keep audits consistent.

Introduce a brown-in blanking period and a re-qualification window before re-enabling rails. Clear or re-sync PG states, gate enable lines until pre-bias is safe, and enforce a cool-down timer between retries. Record each incident in FRU so repeated occurrences can be correlated with slot position or airflow constraints.

Place isolators close to sink domains and pull up on the target side. Use open-drain drivers for mixed levels and stretch the reset pulse so every domain meets its POR requirement. Coordinate release with either multi-flop synchronizers or a windowed release pulse to avoid metastability across clock islands.

Classify by criticality and hazard. Allow limited retries with cool-down for non-critical rails; de-rate loads to preserve core domains; and shut down when safety or integrity is at risk. Always record failure class, attempt count and policy chosen so field returns can be analyzed against environmental conditions.

Trigger logging on thresholds and batch writes to reduce overhead. Reserve a write-ahead window and honor an early power-fail signal when available. Prove T_total = sample + decide + queue + write ≤ window under worst-case bus contention, then measure loss rate by cutting power near the deadline.

Target sub-millisecond alignment, bounded by the receiver’s lock requirements and the interface’s power-up window. Validate with a timing assertion band and phase the dependent rails within that window. Use a common release reference, then confirm the eye or training sequence is not degraded by residual skew.

Normalize PG polarity and minimum pulse, then align threshold step size and hysteresis model. Insert glue logic where semantics diverge and re-run your validation matrix across cold/warm and failover cases. Treat “pin-compatible but semantic-different” parts as non-equivalent until regression results are clean.