Buck / Boost / Buck-Boost Regulators
Clean power bring-up and shut-down protect silicon, prevent brown-outs, and make multi-rail systems repeatable. This guide turns soft-start, pre-bias handling, rail tracking, PG/RESET hygiene, and power-down policies into practical wiring and validation steps.
You’ll get formulas, layout tips, test playbooks, and real IC options for USB-PD and automotive conditions—so ramps stay monotonic, reverse current is blocked, and RESET behavior is deterministic.
Why Sequencing Matters
Center idea: Start-up and shut-down are timing problems. Rails must rise (and fall) in the right order, at controlled slew rates, with deterministic PG/RESET handoff. Good sequencing prevents inrush trips, non-monotonic ramps, latch-up, and reverse current.
Typical Failure Modes
- Glitch-induced resets: VOUT dip or PG chatter releases RESET too early → boot loops.
- Latch-up / reverse conduction: IO before core, or negative injection paths are left open.
- Overshoot / non-monotonic ramps: Soft-start too fast or loop + large COUT ESR zero interaction.
- Reverse current at pre-bias: Synchronous FETs sink current on enable without diode emulation.
Where It Shows Up
- MCUs/MPUs: Core before IO; release RESET after rails settle.
- RF bias chains: LO/PA/LNA rails need ordered, gentle ramps to avoid clicks/IMD.
- FPGAs (core + IO + AUX): Coincident or offset tracking with strict PG windows.
- Automotive cranks: Deep VIN sag → PG races; hold-up and brown-out policies matter.
Minimal Working Recipe
- Define rail order (dependencies/core→IO/analog→digital).
- Set ramp rates (soft-start / tracking) and PG de-glitch windows.
- Gate RESET with “min-good” time; verify monotonic ramps.
- Plan power-down: hold-off, soft-off, discharge, reverse-path control.
Validate with timelines: EN, VOUT, IIN, SW, PG, RESET (cursor tPG, de-glitch, release order).
Soft-Start — Ramp Control & Inrush
Goals
- Limit inrush current so source/upstream stages don’t trip.
- Reduce overshoot; ensure monotonic rise so PG/RESET is trustworthy.
- Let the control loop engage smoothly (avoid current-limit/hiccup starts).
Key Rules of Thumb
Soft-start time (IC-specific):
t_SS ≈ (V_REF · C_SS) / I_SS
Inrush quick estimate:
I_IN,rush ≈ (C_OUT · ΔV_OUT) / t_SS · (1/η)
η = ramp efficiency (typically 0.8–0.95).
Worked Example
Target 5 V rail, C_OUT = 220 µF, desired t_SS = 10 ms, η = 0.9:
I_IN,rush ≈ (220e-6 · 5) / 0.01 · (1/0.9) ≈ 0.122 / 0.9 ≈ 135 mA
Check against upstream limits and connector/cable ratings.
Picking C_SS
- Start from allowed inrush and startup time → compute
t_SS→ deriveC_SSfrom IC’sV_REF,I_SS. - Mind datasheet limits: some devices cap
t_SSor require min/maxC_SS. - If hiccup/UVLO may trigger (weak source/crank), slightly increase
t_SSand/or raise UVLO falling threshold.
Interactions & Pitfalls
- Current limit & hiccup: Too small
t_SS→ high di/dt → early limit → hiccup. - Large C_OUT & ESR zero: Late loop engagement can overshoot; verify near end of ramp.
- PFM↔PWM boundary: AUTO mode may dither at low load; lock PWM if the IC allows.
- Pre-bias start: Enforce diode-emulation/no-sink so ramp begins from existing VOUT.
t_SS, inrush indication, and PG de-glitch window.Measurement Checklist
- Scope EN, VOUT, IIN, SW, PG (1–2 ms/div).
- Confirm monotonic rise; measure PG de-glitch and release time.
- Sweep VIN min, max load, and temperature; log
t_SSdistribution. - Verify no negative current at pre-bias and no overshoot beyond the target.
Pre-Bias — Starting into a Live Output
Idea: Pre-bias means VOUT is already above 0 V when the regulator enables. Without sink control, synchronous FETs can pull that stored charge back into the converter, causing back-discharge, brown-outs, or damage.
What & Why
- Pre-bias: Residual charge or another rail keeps VOUT>0 (hot-plug, rail sharing, USB-PD step).
- Back-discharge path: Low-side FET/body diode sinks current into SW/GND during start.
Requirements
- Synchronous FET gate management: enable diode emulation / zero-current detect (ZCD).
- No negative current: sense + control mode must prevent sink at light load.
- Ramp from existing VOUT: soft-start and PG/RESET logic must respect the pre-bias level.
Do / Don’t
- Do: blank soft-start and current-limit comparators until zero-current is detected.
- Do: use ideal-diode (OR-ing) FETs when rails can pre-charge each other.
- Don’t: force output discharge unless the datasheet explicitly requires it.
- Don’t: leave modes that allow reverse inductor current at light load.
Validation
- Scope VOUT, SW, inductor current, PG/RESET with 0.5–1.0 V pre-bias.
- Confirm: no negative current spikes; monotonic rise from pre-bias level; PG releases after de-glitch.
Rail Relationships — Tracking Modes & Implementation
Idea: Multi-rail systems must rise in a defined relationship so clamp diodes and bias chains stay quiet. Choose ratiometric, coincident, or offset based on the silicon’s needs, then implement with TRK pins, error-amp summing, or an external DAC/reference—keeping slew rates aligned.
Modes & When to Use
- Ratiometric: Proportional slopes (V2/V1 ≈ constant). Good for core/IO when absolute timing is flexible.
- Coincident: Rails finish together (same Δt, different slopes). Great for FPGA core+IO.
- Offset: Fixed lead/lag by V or time. Use for analog-before-digital or RF bias staging.
Implementations
- Tracking pin (TRK/SS): Slave rail follows master; low BOM, predictable.
- Error-amp summing: Ratio/offset shaping by injecting master/reference into FB/EA node.
- External DAC/reference: Precise slopes/plateaus; hand off to controller EA.
Slew-Rate Alignment
- Keep each rail’s dV/dt within ±10–20% of the intended relationship.
- Make TRK ramp ≤ soft-start ramp; the slower source dominates actual dV/dt.
- When VIN is moving (USB-PD, crank), hold downstream rails or rate-limit to avoid brown-out.
Quick Choices
- FPGA core+IO: coincident or tight ratiometric; RESET after both PG windows.
- RF bias (LNA/LO/PA): offset (LNA/LO first), then PA; gentle slopes to reduce clicks/IMD.
- Analog + digital: bring analog references slightly early, then core/IO.
Pitfalls & Checks
- Mismatched TRK vs SS capacitors → relationship breaks under load.
- Daisy-chain PG adds variable delays; prefer a centralized sequencer if tolerances are tight.
- TRK pin current limits with long RC networks → non-linear ramps; verify slopes on scope.
Validate across VIN min, temperature max, and load extremes; compute slopes from scope cursors.
Sequencer Architectures — PG Chain, Supervisor IC, and GPIO/PMBus
Idea: Multi-rail power needs a “central brain.” From a simple PG daisy-chain to dedicated supervisor/sequencer ICs and fully programmable GPIO/PMBus control, centralization increases policy control, diagnostics, and field flexibility—at the cost of BOM and complexity.
Patterns Overview
- PG daisy-chain: distributed, low BOM, easy to wire; vulnerable to race and weak diagnostics.
- Supervisor/Sequencer IC: central policy, precise thresholds, latching faults, retry, telemetry pins.
- GPIO/PMBus: programmable timing and brown-out responses; supports field updates and logging.
Quick Selection Rules
- Few rails + budget-sensitive → PG chain (with proper de-glitch and gating).
- Many rails + high reliability → Sequencer IC with fault policy.
- Need remote updates/policies → GPIO/PMBus (with safe hardware bootstrap).
Daisy-Chain with PG
- Pros: simple, distributed; minimal components.
- Risks: PG thresholds/hysteresis mismatch → variable delays; limited fault visibility.
- Do: PG de-glitch, consistent pull-ups, one-way gating (avoid backfeed), soft-off on the last rail.
Supervisor & Sequencer ICs
- Centralized timing/thresholds; window comparators and hysteresis; programmable delays/dependencies.
- Fault strategies: latch-off vs timed retry; distinct cold-start vs warm-reset behavior.
- Best when: ≥3–4 rails, strict timing, diagnostics, automotive/industrial grading.
GPIO / PMBus Control
- Firmware-defined sequencing and brown-out handling; logs events; field-updatable.
- Bootstrap caveat: before firmware runs, use a safe hardware “pre-sequence.”
- Combine with supervisors for power-fail capture and deterministic safe-off.
Validation & Fault Injection
- Prove order and delays over temperature/load; inject UV/OV/short and confirm policy (latch/retry).
- Record PG edges, RESET, and per-rail status; confirm logs match oscilloscope timelines.
PG Windows & Reset Hygiene
Idea: PG indicates electrical readiness; RESET gates system readiness. Unify definitions, add de-glitch and min-good time, release RESET in dependency order, and safely OR multiple PG sources with hysteresis/window comparators.
Definitions
- PG (Power Good): rail within window (threshold + hysteresis) and stable.
- RESET: gate allowing CPUs/PMICs/FPGAs to exit reset after all conditions are met.
De-Glitch & Min-Good
- De-glitch filter: RC or digital (typ. 1–20 ms), sized ≥ soft-start + loop settle near the threshold.
- Min-good: hold-off after PG true to guarantee stable operation before RESET release.
Release Order
- Order by dependency: clock → core → IO → peripherals (or FPGA/DDR training needs).
- Release RESET after the slowest rail has passed PG + min-good.
Hysteresis & Window Comparators
- Windows reduce sensitivity to small ripple; add hysteresis to avoid chatter near the threshold.
- Calibrate to worst-case temp/load and expected ripple envelopes.
OR-ing Multiple PG Sources
- Normalize levels; de-glitch each source locally before logic combine (AND/OR/majority).
- Prevent back-pull: open-drain or ideal-diode gating; avoid hard-wired contention.
Pitfalls & Checks
- “EA OK” ≠ true VOUT: always measure the real rail for PG.
- Min-good too short → CPU boots before clock locks or DDR trains.
- Hard-wired PG tie without level match/de-glitch → mutual dragging and false decisions.
Implementation Notes
- Use window comparators on critical rails; add hysteresis consistent with ripple/temp drift.
- Apply per-rail de-glitch before logic AND/OR; then enforce a global min-good timer.
- RESET fans out to CPUs/PMICs only after “slowest rail PG + min-good.”
Validate with scope cursors on PG edges, combined PG, min-good window, and RESET. Inject brown-outs to confirm no false release.
Power-Down — Soft-Off, Discharge & Reverse Paths
Idea: A good shutdown mirrors a good start-up: monotonic decay, no reverse injection, and enough data flush time. Combine active discharge, a bleeder network, load-side OR-FETs, and a supervisor-controlled HOLD-OFF → RESET flow for predictable soft-off.
Objectives
- Monotonic decay: no rebounds or step drops.
- No back-injection: block reverse paths into upstream rails or interfaces.
- Flush time: guarantee time for logs/files/MCU tasks before rails collapse.
Methods
- Active discharge pin: deterministic pull-down; check thermal stability.
- Bleeder network: sets discharge time constant; prevents long tail voltage.
- Load-side OR-FETs: ideal-diode isolation to stop back-feed.
- Supervisor flow: HOLD-OFF (save) → assert RESET → controlled power-off.
Hold-Up Energy Budgeting
Maintain a keep-alive rail for t_hold during outages. Use either power- or current-based sizing:
Power model: C ≥ (2·P·t_hold)/(V_start² − V_min²)
Current model: C ≥ (I · t_hold) / ΔV, where ΔV = V_start − V_min.
Account for diode/OR-FET drops and temperature drift; verify worst-case load.
Reverse Path Control
- Identify sinks: synchronous low-side FETs, load caps, interface ESD diodes.
- Use ideal-diode controllers or series FETs; orient returns to avoid cross-coupling.
- Disable active discharge during pre-bias handover unless explicitly required.
Validation
- Test hard unplug, brown-out, and load steps; verify monotonic decay and no reverse current.
- Measure
t_hold, RESET timing, and data flush completion indicators. - Thermal-check active discharge and bleeder elements at high ambient.
Transitions — USB-PD, Automotive Crank, and Mode Boundaries
Idea: Voltage transitions are failure-prone moments. Use pre-bias-friendly re-ramp, rate limiting, and proper UVLO windows to prevent brown-outs and reverse currents; near start-up, manage PFM↔PWM transitions to avoid artifacts.
USB-PD PDO Changes
- Freeze or slow downstream rails during input step; then re-ramp with pre-bias + rate-limit.
- Extend de-glitch or mask PG/RESET during the PDO step to avoid false trips.
Automotive Crank & Load Dump
- Set UVLO windows (rise/fall with hysteresis) to avoid chatter during cold-crank dips.
- Use staged brown-out: keep-alive rails first, then controlled shed of non-critical rails.
- Clamp load-dump; reuse soft-start for post-event re-ramp.
Mode Boundaries
- Near start-up or light load, force PWM (if available) to avoid PFM ripple and reverse current.
- In AUTO modes, add hysteresis/delay to prevent flapping around the boundary.
Validation & Pitfalls
- USB-PD sweep: 5→9→15→20 V; verify no brown-out or reverse current spikes.
- Automotive profiles: cold-crank curves + load steps; confirm PG/RESET stability and keep-alive budget.
- Artifacts: avoid letting downstream rails follow fast input transients; don’t set only UVLO rising threshold.
Layout — Practical Wiring for a Clean Start
Idea: Clean start-up is mostly a wiring and signal integrity problem. Keep high-current loops short and tight, keep small-signal nodes quiet and short, and size RC filters that tame glitches without destabilizing the loop.
Sense Lines & PG Routing
- Kelvin sense (FB/SENSE±): route as a pair, away from SW node and inductor; avoid vias near noisy copper.
- PG/RESET: use quiet layers; open-drain pulls up to the same logic domain; keep away from power loops.
Local RCs & Filters
- EN/PG de-glitch: target 1–10 ms with RC; mind threshold shift from the divider.
- Comp/FB parts: treat Cff (10–100 pF) as compensation, not noise bandaid; changing it moves zeros.
Return Paths
- Power loop: switch FET → inductor → COUT → return; keep compact and tight-coupled.
- Small-signal returns: FB/PG/EN avoid power return; star or single-point reference when needed.
Avoid Long SS Nodes
- Place CSS next to the IC; long SS traces pick up noise → ramp jitter.
- For remote tracking, route a TRK/reference instead of stretching SS.
Bleed Paths Placement
- Prefer bleeder/active discharge on the load side so current does not flow back through the controller.
- Check worst-case voltage and thermal rise on bleeders.
Keep EN/PG Quiet
- Shield with ground guard or opposite layer; series 50–200 Ω + 1–10 nF to ground for RC de-glitch when needed.
- Normalize logic levels before PG combining; de-glitch individually first.
RC Values That Won’t Destabilize the Loop (Safe Starting Points)
- EN/PG de-glitch: R = 10–100 kΩ, C = 0.1–1 µF → 1–10 ms.
- SS series resistor: 100–1 kΩ (only if the datasheet allows); size CSS from
t_SS ≈ (V_REF · C_SS) / I_SS. - Cff on FB: 10–100 pF typical; re-verify phase margin after any change.
Always re-check loop stability (load step + phase/Bode where available) after RC changes.
Validation — Measurement Playbook
Idea: Turn “looks right” into “proven.” Capture full timelines (EN, VOUT, IIN/inductor current, SW, PG, RESET), place cursors for tPG, de-glitch, release order, then sweep VIN/load/temp and repeat with PDO changes.
Timelines & Cursors
- Scope: EN, VOUT, IIN/Lcurrent, SW, PG, RESET.
- Start with 1–2 ms/div; capture start-up and power-down separately.
- Mark tPG, PG de-glitch window, RESET release, and VOUT slope (ΔV/Δt).
Sweep Matrix
- VIN: min/typ/max, add cold-crank profile; include USB-PD steps.
- Load: 0–100% plus up/down steps; emphasize light load behavior.
- Temperature: −40/25/85 °C (or device limits), repeat worst cases.
Pass Criteria
- Monotonic ramps: no negative steps or rebounds.
- ΔV/Δt bounds: within spec; overshoot ≤ +3–5% over target.
- No negative current: no significant negative IIN/inductor spikes.
- Deterministic RESET: released only after “slowest PG + min-good;” re-asserts cleanly on brown-out.
Artifacts to Watch
- PFM ripple/whine at light load; PG chatter/false-good near thresholds.
- PDO step reverse-current spikes; low-temp ESR causing overshoot.
Report Template
- Annotated screenshots (with cursors) + table of conditions.
- Pass/Fail summary against criteria above; list of corrective actions (BOM/layout).
- Re-test plan for worst cases (VIN min, temp max, light load + PDO steps).
Repeat USB-PD steps (5→9→15→20 V) and automotive crank profiles; confirm no brown-out and deterministic RESET.
Implementation Options — Controllers, Sequencers, USB-PD Front Ends & Automotive Picks
How to use this section: Pick a bucket that matches your sequencing strategy, then choose parts (PNs) by brand. You can swap equivalent PNs later when supply or policy changes. Badges hint typical capabilities.
A) Controller with Tracking Pin
Tracking/TRK
Soft-Start
Simple BOM
LTC3851A— Sync buck controller with TK/SS pin for tracking.LTC3789— 4-switch buck-boost controller, TRACK/SS for up/down conversion.LM5146-Q1— 100 V sync buck controller (auto-grade); supports external tracking network.ISL68222— Digital multiphase controller (PMBus) enabling coordinated ramps.NCP81239— USB-C/PD buck-boost controller; programmable ramp control.MP2965/MP2884A— Digital multiphase controllers for core/IO tracking.L6983(ST) — Buck with SS; implement tracking via FB summing network.
Use coincident/ratiometric by tying slave TRK to master rail (via divider) and matching dV/dt.
B) Controller + Supervisor
Window PG
Hysteresis
Reset
LTC2937— 6-rail programmable supervisor/sequencer with fault logging.LM3880-Q1— 3-rail simple sequencer (fixed delays), chainable, AEC-Q100.ISL70321SEH/ISL73321SEH— 4-channel sequencing supervisors (Renesas).TLF35584— Infineon system basis chip with watchdog/supervision for automotive.STM706/STWD100— ST supervisors for PG/RESET hygiene.NCP302/NCP308— onsemi supervisors with adjustable thresholds.
Let the supervisor gate PG/RESET and enforce min-good; the power controller focuses on regulation.
C) All-in-One Sequencer / Power System Manager
PMBus
Telemetry
Fault Latch/Retry
LTC2977— 8-rail PMBus power system manager (sequence/margin/telemetry).LTC2974— 4-rail variant; stack for higher rail counts.UCD9090A/UCD9090-Q1— 10-rail PMBus sequencer/monitor (TI).UCD90160A— 16-rail supervisor/sequencer, extensive logging (TI).ISL68222/ISL68220— Digital controllers used as central managers (Renesas).
Choose this when you need strict timing across ≥4–10 rails, margining, black-box logs, and field updates.
D) USB-PD Aware Front End
USB-C/PD
PDO steps
Re-ramp
TPS65987D— Stand-alone USB-C/PD controller; policy engine + GPIO/INT for rail masking.TPS25750— Next-gen PD controller with I²C control (sink/source profiles).STUSB4500/STUSB4500L— ST PD sink controllers (auto-contract options).CYPD3171 (EZ-PD CCG3PA)— Infineon PD controller family for adapters/sinks.RAA489204— Renesas USB-C sink/source PD controller (configurable PDOs).NCP81239— onsemi buck-boost PD controller bridging front-end and rails.MP5031/MP5032— MPS USB-C/PD port controllers (fast-charge support).
Mask downstream PG during PDO changes; re-ramp with pre-bias and rate-limit to avoid brown-outs.
E) Automotive-Grade (AEC-Q100) Options
AEC-Q100
Cold-Crank
Load-Dump
LM5146-Q1— 100 V sync buck controller (TI) with programmable UVLO/hiccup.UCD9090-Q1— 10-rail PMBus sequencer/monitor (TI automotive).TLF35584— Infineon SBC (watchdog + supervisors) for ASIL systems.A6986— ST automotive buck regulator family (AEC-Q100).NCV8871— onsemi automotive boost controller (cold-crank pre-regulator).ISL78268— Renesas automotive buck regulator.MPQ8633A— MPS automotive buck converter (sync, fast transient).
Pair an auto-grade controller with an auto-grade sequencer/supervisor for deterministic crank behavior.
Brand Quick Picks (editable placeholder grid)
Texas Instruments (TI)
LM5146-Q1Buck Ctrl
UCD9090A / Q1PMBus Seq
TPS65987DUSB-PD
LM3880-Q13-Rail Seq
Analog Devices (ADI/LTC)
LTC3851ATRK/SS
LTC3789Buck-Boost
LTC2977PMBus PSM
LTC2937Supervisor
STMicroelectronics
L6983Buck
STUSB4500/LUSB-PD
A6986Auto Buck
STWD100Supervisor
Infineon (incl. Cypress)
CYPD3171USB-PD
TLF35584SBC
IR/IMC SeriesBuck Ctrl
ICE Power MonMonitor
Renesas
ISL68222Digital Ctrl
ISL70321/73321Supervisor
RAA489204USB-PD
ISL78268Auto Buck
onsemi
NCP81239PD B-B Ctrl
NCV8871Auto Boost
NCP302/NCP308Supervisor
NCP45491Monitor
Monolithic Power (MPS)
MP2965 / MP2884ADigital Ctrl
MP5031/MP5032USB-PD
MPQ8633AAuto Buck
MPM54304PMIC (multi)
Use the grid as a shopping shortlist. You can replace any PN with your preferred in-stock or NDA parts later.
Selection Hints
- Few rails, simple timing: Bucket A or B.
- Many rails, strict logs & field updates: Bucket C (PMBus system managers).
- USB-C input with PDO changes: Bucket D + PG masking + re-ramp.
- Automotive/industrial extremes: Bucket E (AEC-Q options + UVLO/hiccup strategy).
Always confirm datasheet limits for tracking range, PG thresholds/accuracy, UVLO windows, and temperature grades before finalizing the BOM.
Engineering FAQ — Start-Up & Sequencing
1) How do I size the soft-start capacitor?
Use the IC’s soft-start current and reference: tSS ≈ (VREF·CSS)/ISS. Pick tSS from allowed inrush and start-time targets, then back-calculate CSS. Verify monotonic rise at VIN minimum, maximum load, and temperature extremes; increase tSS if current limit or hiccup triggers during ramp.
2) What’s acceptable inrush current for my rail?
Estimate IIN,rush ≈ (COUT·ΔVOUT)/tSS·(1/η). Compare to source limits (adapter, cable, hot-swap) and converter current limit. If margin is small, lengthen tSS, add input impedance or NTC, or pre-charge. Confirm with scope and review supply fold-back thresholds and protection timings.
3) How do I start into a pre-biased output without sinking current?
Enable diode emulation or zero-current detection so the low-side FET turns off at zero current. Begin the ramp from the existing VOUT level, not from zero. Avoid active discharge unless required. Validate no negative inductor-current spikes and a monotonic rise from the pre-bias level under load and temperature.
4) Coincident vs ratiometric tracking—when should I choose each?
Use coincident when rails must finish together (e.g., FPGA core and IO), reducing clamp-diode stress. Use ratiometric when proportional slopes are acceptable and timing windows are looser. Keep dV/dt aligned within ±10–20%. Implement via TRK/SS pins, error-amp summing, or a DAC; verify slopes on the scope.
5) Do I need a sequencer IC or can I daisy-chain PG?
PG daisy-chains are simple and inexpensive but suffer from threshold variation, temperature drift, and weak diagnostics. Sequencer ICs centralize policy, add fault latching/retry, and telemetry. Choose daisy-chains for a few tolerant rails; pick sequencers for ≥3–4 rails or when strict timing and field troubleshooting are mandatory.
6) How should I wire PG and RESET?
Treat PG as “electrical ready” and RESET as “system release.” Apply per-rail de-glitch and a global min-good timer before RESET fan-out. Combine PGs only after local filtering and level normalization. Use window comparators plus hysteresis on critical rails; scope tPG and verify deterministic RESET release order.
7) How do I guarantee a monotonic power-down?
Reserve a HOLD-OFF window for data flush, then assert RESET, then discharge rails in a controlled, monotonic way. Use load-side bleeders or active discharge and block reverse paths with ideal-diode FETs. Confirm no rebounds, no reverse current, and deterministic sequencing during hard unplug and brown-outs.
8) How much hold-up capacitance do I need?
Power-based sizing: C ≥ 2Pthold/(Vstart²−Vmin²). Current-based: C ≥ I·thold/ΔV. Include OR-FET or diode drops and temperature derating. Validate by removing input power and measuring time until VOUT reaches the minimum operating level with representative loads and firmware activity.
9) How do I avoid brown-outs during USB-PD PDO changes?
Mask PG/RESET during input steps, hold downstream rails, then re-ramp with pre-bias and a limited dV/dt. Keep the downstream ramp slower than the upstream transition. Confirm no PG chatter and no negative current. Repeat tests across 5→9→15→20 V steps with realistic cable resistance and load transients.
10) What UVLO and hysteresis should I choose for cold-crank?
Set rising/falling UVLO with sufficient hysteresis to avoid chatter throughout the crank sag. Add staged brown-out: keep-alive rails maintained while non-critical rails shed. After the dip, reuse soft-start/tracking for a clean re-ramp. Validate with standardized crank profiles and temperature extremes per the target environment.
11) Why does my ramp overshoot with large COUT?
Large COUT and ESR zeros shift loop dynamics; a short soft-start can hand control to the loop near weak phase margin. Lengthen tSS, review compensation (Cff/RCOMP/CCOMP), and test a near-end-of-ramp load-step. Force PWM during bring-up if AUTO-PFM introduces ripple or reverse current artifacts.
12) How do I filter EN/PG without destabilizing the loop?
Use RC de-glitch on EN/PG (≈1–10 ms) away from the feedback path. Keep SS short and close to the IC; avoid adding large capacitors to FB unless intended for compensation. If Cff or other compensation parts change, re-validate transient response and—where available—phase margin or Bode plots.
13) What measurements prove my sequencing is solid?
Capture EN, VOUT, PG, RESET, SW, and input/inductor current. Place cursors on tPG, de-glitch, RESET release, and ΔV/Δt. Sweep VIN (min/typ/max, crank), load (0–100% and steps), and temperature; repeat with PDO changes. Pass when ramps are monotonic, currents non-negative, and RESET behavior is deterministic.
Each answer is intentionally concise (≈45–60 words) and action-oriented. Expand locally on your product page if needed.
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