Ultralow-IQ / Nanopower LDO Guide

Aim for sub-µA quiescent current, ideally 25–600 nA depending on duty cycle and advertisement interval. Validate average current as Iavg = Iq + Iactive·duty, and include wake energy per event. Check wake time under cold, small Cout values, and RF burst coupling. Confirm stable startup with pre-bias cases.

Divider leakage, meter burden, and temperature drift inflate readings. Disconnect or account for FB resistors, measure with a high-accuracy DMM or SMU at VIN min/nom/max, and soak at low and high temperature. Ensure EN state and any pull-ups are known. Log Iq_off separately from normal Iq.

Probe EN, Vout, and load simultaneously. t_ref is bandgap/reference start, t_EA is error-amp settling, t_BYP is bypass-cap charging, and t_SS is soft-start ramp. Repeat with BYP on/off and different FF values. Record each segment across VIN and temperature corners for budget and regression.

Start with 1–4.7 µF MLCC and the vendor’s ESR range. Very low ESR shifts the ESR zero upward and reduces damping. Sweep Cout and add small series ESR if needed. A tiny feed-forward cap often improves phase margin, but verify overshoot and ringing under load steps and cold conditions.

Yes. Bypass capacitors usually lower reference noise and improve PSRR but add a charging delay. Quantify the trade-off by measuring noise or PSRR vs wake-up segments with BYP on/off. Use the smallest effective BYP value, and confirm timing budgets for sleep-to-active transitions at cold temperatures.

Force Vout > Vin and measure I(Vin) with a shunt or SMU. Test EN low and power-fail scenarios. With reverse-current blocking the current should be near zero. Without RCB, evaluate an ideal-diode path. Log peak and duration to check energy impact and validate no latch-up or brown-out resets.

Some devices need a tiny load to maintain regulation or stability. If required, choose a value that does not dominate Iavg, or gate a small current only during active windows. Validate regulation at 0 → I_min → I_step and confirm no oscillation with the intended Cout and ESR range.

Ultra-low Iq can reduce loop bandwidth and PSRR. Budget noise and PSRR at your sensitive frequencies, not just at 100 kHz. Consider a low-noise family member or a small pre-reg plus RC filter. Verify with spectrum and burst-load tests that mirror radio or conversion transients.

Inject a controlled pre-bias near 0.7×Vout_nom and check EN timing versus load enables. Watch for discharge paths or auto-discharge creating glitches. Record overshoot and undershoot with different Cout and BYP settings. Ensure the downstream supervisor threshold and delay tolerate the startup shape.

MLCC capacitance and ESR shift lower the effective output pole; dropout margin shrinks as device parameters drift. Sweep VIN downward at low temperature and record regulation error and wake-up segments. Confirm the worst-case VIN_min still meets timing, and consider larger Cout or controlled ramp if needed.

Divider current adds directly to Iavg. Use higher resistor values within the device’s bias current and noise limits, and add a small capacitor to shape bandwidth. Verify line regulation and noise. Measure Iq with and without the divider connected to isolate its contribution accurately.

If your rail needs wideband PSRR, very low noise, or extremely fast wake-up, a slightly higher-Iq regulator or a filtered pre-reg may outperform nano-Iq parts. Compare PSRR at your disturbance frequencies, noise in µV_rms, and t_wake budgets. Prototype both paths and measure with system-realistic loads.