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Battery-powered devices demand regulators that keep output stable while drawing microamp-level quiescent current. Ultralow-IQ buck converters use PFM/auto-save strategies, deep-dropout sustain, and UVLO guards to extend runtime under low-VIN and burst-load conditions.
Introduction
What is an Ultralow-IQ Buck?
An ultralow-IQ buck is a step-down converter optimized to keep its own quiescent current in the microamp range during standby and light-load operation, while preserving output regulation and fast wake-up. Typical building blocks include PFM/auto-save control, burst/skip logic, deep-dropout sustain paths, and UVLO guards.
Why it matters in battery systems
Duty-cycled devices spend the majority of time asleep. The average power Pavg ≈ D·Pactive + (1−D)·Psleep, where Psleep is dominated by the regulator’s Iq. As batteries age, internal resistance rises, VIN sags, and burst loads (RF TX, flash writes) demand quick mode transitions. Ultralow-IQ bucks extend runtime precisely under these constraints.
Compared with LDO and conventional PWM buck
- LDO: excellent noise but efficiency equals Vout/Vin; average energy loss grows as Vin − Vout increases.
- Conventional PWM buck: great mid/high-load efficiency and spectral control, but light-load Iq is higher and idle losses are non-trivial.
Operating Principle: How Ultralow-IQ Buck Saves Power
PFM / Auto-Save (light-load pulsed power)
The converter periodically delivers energy packets to hold Vout, then idles large parts of its control loop, drivers, and comparators. This drastically reduces Iq at light load. The trade-off is a low-frequency ripple that may couple into sensitive ADC/RF paths and needs filtering or selective PFM disable windows.
Burst/Skip & transition thresholds
When the load or error accumulation exceeds a device-specific threshold, control transitions back to constant-frequency PWM; with hysteresis, it returns to PFM once the load/ripple budget relaxes. A too-high threshold increases light-load losses; too low brings larger ripple and slower response. Thresholds vary by device and temperature—verify them during validation.
Deep-dropout sustain
As VIN approaches VOUT, the buck can enter a near-linear path where the high-side RDS(on) and inductor DCR behave like a series resistance, approximately VOUT ≈ VIN − ILOAD·(RHS + RL(DCR)). This extends useful time near end-of-life batteries but increases thermal stress and limits deliverable current.
UVLO guards with hysteresis
UVLO thresholds (th_on/th_off) with proper hysteresis prevent brown-out thrash and protect deeply discharged cells. Align UVLO with the MCU’s brown-out detector to ensure stable shut-down and re-start behavior.
Start-up / Re-start (from depleted battery & pre-bias)
Soft-start limits inrush; phase power-up for burst loads such as radios and storage writes. Check pre-bias support to avoid back-feeding or pulling the load down. Define power-down order so sensitive analog and storage shut off cleanly before the main rail.
Key Parameters & Design Considerations
Iq (µA/nA class)
Quiescent current dominates average power when the duty cycle is low. Always review Iq(max) and temperature behavior,
not just typical. For battery devices with duty cycle D:
Pavg ≈ D·Pactive + (1−D)·VIN·Iq
- Test with peripherals off; fixture leakage < 100 nA; log mode (PFM/PWM), VIN, VOUT, and temperature.
- For winter performance, validate Iq at −20/−40 °C.
Dropout definition & sustain window
Near end-of-life batteries, the buck may run in a near-linear path. Minimum VIN to hold regulation:
VIN(min) ≈ VOUT + ILOAD·(RHS + RL(DCR))
- Define acceptable load and hold time under deep-dropout; include pulse loads (RF TX, flash writes).
- Validate by stepping VIN downward and logging the loss-of-regulation point vs. load & temperature.
Efficiency across load
Optimize for the integrated energy over time, not a single point. Track three regions: light load (PFM), mid-load (transition pit), and heavy load (conduction loss, inductor saturation).
- PFM ripple may require a post filter or secondary LDO for sensitive rails.
- Measure with identical harnessing and probing to ensure curve comparability.
Thresholds: UVLO, PFM↔PWM, PG
- UVLO: use th_on/th_off with hysteresis; align with MCU BOD to prevent brown-out thrash.
- PFM↔PWM: transition point sets light-load loss vs. ripple; check temp & lot dependency.
- PG: threshold & delay define sequencing—critical in multi-rail systems.
Noise & ripple under PFM
Low-frequency ripple can couple into ADC, audio, and RF. Mitigate with compact input loops, post RC/π filters, or secondary LDO. For critical windows, force PWM (see Modes).
Thermals & package
- Short bursts can raise junction temperature quickly; θJA and exposed-pad copper area limit sustain time.
- Small packages favor Iq but penalize thermal headroom—evaluate against burst envelope (10–60 s).
Architecture Modes: PFM, AUTO, FORCED PWM
PFM
- Ultra-low Iq; frequency follows demand; larger low-frequency ripple.
- Best for long-standby, light-load dominant designs.
- If sensitive rails exist, filter or switch to PWM during critical windows.
AUTO
- Automatic PFM↔PWM transition across load; balanced efficiency and performance.
- Good default for battery products with variable load profiles.
- Validate transition thresholds and hysteresis across temperature.
FORCED PWM
- Fixed frequency; well-controlled spectrum; higher light-load Iq.
- Use for ADC/audio/RF-sensitive intervals; revert to AUTO/PFM afterward.
- Coordinate with PG/UVLO to avoid mode chatter near shutdown.
Quick selection: If light-load >= 90% and noise tolerance is moderate → PFM. Mixed profile with broad load variation → AUTO. Noise-critical measurement/audio/RF windows → FORCED PWM during the window, then revert.
Applications: Where These Regulators Win
Ultralow-IQ buck regulators excel in long-standby + short burst battery designs. They minimize average energy when devices sleep most of the time and must briefly deliver higher current for sensing, compute, or RF transmission.
IoT Nodes (duty-cycled sensing / TX)
Long sleep with short TX peaks. Average power depends on duty cycle, payload size, and TX peak current.
- Mode: AUTO by default; force PWM during TX windows.
- Grips: Iq(max at −20/−40 °C), PFM↔PWM threshold, UVLO vs MCU BOD, Cout/ESR sizing.
- Validate: D=1–5% power audit; Vout droop and recovery during TX bursts.
Wearables & Medical
ECG/PPG front-ends plus BLE beacons. PFM low-frequency ripple can modulate sensitive analog paths.
- Mode: PFM baseline; force PWM during ADC/AFE sampling and—if needed—during BLE TX.
- Grips: ripple budget (mVpp), post LDO bandwidth, switching frequency vs sampling band.
- Validate: ENOB delta (PFM vs PWM), noise floor of ECG/PPG, BLE adjacent-channel.
Industrial Sensors (long-life primary cells)
Low-temperature ESR rise causes VIN sag. End-of-life operation requires stable dropout sustain and robust UVLO hysteresis.
- Mode: AUTO; near EOL, maintain deep-dropout sustain; ensure UVLO hysteresis.
- Grips: VIN(min), path resistance, UVLO on/off, package θJA.
- Validate: Iq at −20/−40 °C, UVLO return gap, VIN step-down sustain time.
Backup Power / Data Loggers
Deep sleep with short peaks for flash writes or telemetry. Pre-bias and power sequencing are essential.
- Mode: PFM default; force PWM during write/TX; pre-charge or larger Cout for high peaks.
- Grips: soft-start, pre-bias support, PG delay, Cout/ESR, thermal headroom.
- Validate: write success vs droop; PG sequencing and clean power-down.
Battery Chemistry Differences
Li-ion / Li-SOCl₂ / NiMH differ in internal resistance, voltage plateau, low-temperature behavior, and protection needs. Assess cold start capability, soft-start time, pre-bias tolerance, and deep-discharge sustain limits (RHS + DCR induced error).
| Use Case | Load Profile | Recommended Mode | Must-Verify Thresholds | Notes |
|---|---|---|---|---|
| IoT Node | Long sleep, short TX | AUTO; PWM during TX | PFM↔PWM, UVLO, PG | Cout/ESR; recovery time |
| Wearable / Medical | Analog + BLE beacons | PFM; PWM in ADC/BLE | Ripple budget, freq plan | Post LDO band |
| Industrial Sensor | Low temp, EOL sustain | AUTO; deep-dropout | UVLO hysteresis; VIN(min) | θJA limits |
| Backup / Logger | Deep sleep + short write | PFM; PWM in write/TX | PG delay; pre-bias | Pre-charge or larger Cout |
IC Selection by Brand (placeholders – final picks require datasheet verification)
The cards below are to-verify placeholders. Final recommendations must be confirmed against official datasheets (Iq typ/max, VIN/VOUT, IOUT, PFM/AUTO/PWM, UVLO on/off, package/thermals, pre-bias, PG).
Texas Instruments (TI)
To-verify- TPS62740 — ultralow-Iq buck, PFM/AUTO (verify: Iq typ/max, UVLO, pre-bias).
- TPS62840 — low-IQ, wide VIN (verify: PFM threshold, IOUT, PG delay).
- Alt route by params if constraints differ: target Iq ≤ few µA, VIN 1.8–5.5 V, PFM + UVLO hysteresis.
STMicroelectronics (ST)
To-verify- ST1PS01/02/03 — nano-power family (verify: Iq, UVLO, dropout behavior).
- Other ST nano/power series—confirm PFM/AUTO modes and light-load efficiency.
Renesas
To-verify- ISL9123A — buck-boost (verify if pure-buck alternatives are needed).
- Check low-Iq buck families; confirm PFM↔PWM thresholds, UVLO hysteresis, pre-bias.
onsemi
To-verify- Screen for µA-class Iq buck series; verify true ultralow-Iq positioning.
- If not available, apply cross-brand parameter route (Iq, VIN, PFM/AUTO, UVLO, package/thermals).
Microchip
To-verify- Some bucks show tens of µA Iq (not strictly “ultralow”); filter for the lowest-Iq options.
- Use cross-brand route if tighter Iq limits are required.
NXP
To-verify- Focus on mobile/auto power families; confirm presence of dedicated ultralow-Iq buck parts.
- If absent, map parameters to TI/ST/Renesas alternatives.
Melexis
To-verify- Primarily sensing/automotive; if no suitable buck, use cross-brand parameter route.
- Check AEC-Q qualification needs if targeting automotive sensors.
Cross-brand parameter route: target Iq (typ/max & temp), VIN/VOUT, peak & average IOUT, PFM/AUTO/PWM availability, UVLO (hysteresis), dropout limits (RHS+DCR), package/θJA, and features (pre-bias, PG, AEC-Q).
| Brand | PN | Iq (typ/max) | VIN / VOUT | IOUT | Mode | UVLO (on/off) | Notes |
|---|---|---|---|---|---|---|---|
| TI | TPS62740 (tbc) | — | — / — | — | PFM/AUTO | — / — | Pre-bias? PG? |
| ST | ST1PS01/02/03 (tbc) | — | — / — | — | PFM/AUTO | — / — | Dropout curve |
| Renesas | ISL9123A (bb, tbc) | — | — / — | — | Buck-boost / alt buck | — / — | Confirm pure-buck option |
Need verified picks matched to your BOM and constraints? Jump to the RFQ section and submit your design for a 48-hour cross-brand recommendation.
Layout & EMI
Inductor & Input Bypass: Minimize VIN–SW–GND Loop
- Place inductor tight to SW pin; keep the VIN–SW–GND high-di/dt loop as small as practical.
- Use a bulk MLCC plus a small low-ESL MLCC in parallel, routed with short, wide traces.
- Select inductor with Isat ≥ peak current; balance DCR for drop/thermal vs size/cost.
- Add an RC snubber at SW if ringing/EMI spikes violate limits.
Ground Reference: Split AGND/PGND with Single-Point Tie
- Physically separate AGND and PGND; star-connect at a single point to the system ground.
- Kelvin-sense VOUT for FB from a clean node; keep FB thin/short and away from the SW area.
- Use via arrays to stitch power loops to inner ground planes; avoid long ground returns.
PFM Low-Frequency Ripple Isolation
- Front-end: add π/RC filtering (L or R + two MLCCs) to reduce input-borne modulation.
- Back-end: insert RC or a small LDO for ADC/AFE/audio/RF-baseband rails.
- Mode strategy: force PWM during sensitive windows (sampling/audio/RF), otherwise PFM/AUTO.
- Place filters near the target loads; keep sensitive traces off the SW hot-zone (above/below).
Thermal Path
- Fully solder the exposed pad (EP); use dense thermal via arrays to inner/bottom copper.
- Expand copper in VIN/SW/GND regions for heat spreading—avoid oversized “antenna” shapes.
- Board stack-up and plane continuity set effective θJA; size for burst envelopes.
- Cross-check with temperature rise under 10–60 s burst profiles (see Validation).
Validation & Measurement
Iq Testing
- Disable peripherals; ensure fixture leakage < 100 nA; control ambient EMI.
- Use µA/nA-range meter or SMU; log mode (PFM/PWM), VIN, VOUT, temperature.
- Stabilize 2–3 minutes before averaging; test at 25 °C and −20/−40 °C.
PFM Ripple & Transition Thresholds
- Scope: AC coupling, bandwidth limit (e.g., 20 MHz), short ground spring; ≥10× fundamental sample rate.
- Measure Vout mVpp and spectral traits; record pulse sparsity in PFM.
- Sweep load to capture PFM→PWM and PWM→PFM thresholds and hysteresis.
Dropout Sustain
- Step VIN downward (or emulate rising ESR); log VOUT deviation vs load and temperature.
- Compare with VIN(min) ≈ VOUT + ILOAD·(RHS+RL(DCR)); note wiring/connector and thermal effects.
- Record sustain window and thermal limits under EOL conditions.
UVLO & Power-Good (PG)
- Sweep VIN slowly; capture th_on/th_off and hysteresis width; align with MCU BOD.
- Measure PG delay and glitch behavior; verify power-up/down sequencing for downstream rails.
Temperature & Lifetime
- Characterize Iq at −40/−20/25/85 °C; track PFM/PWM and UVLO threshold drift and lot variation.
- Repeat dropout tests with elevated ESR at low temperatures.
- Run burst cycles (TX/writes) and monitor long-term drift of temperature rise and recovery time.
Pass Criteria (per use case)
- Iq ≤ budget at cold/room.
- PFM ripple ≤ noise budget; no aliasing into ADC/audio bands.
- PFM↔PWM thresholds within target bands; stable hysteresis.
- VIN(min) sustain window meets EOL requirements.
- PG timing matches downstream sequencing.
Artifacts to Capture
- Iq vs temperature curve.
- PFM ripple waveform and spectrum.
- PFM→PWM / PWM→PFM threshold table.
- Dropout curve vs load & temperature.
- UVLO/PG timing plots.
FAQs
Practical answers for battery-first designs. Each entry links to deeper sections such as Parameters, Modes, Layout, and Validation.
1) What is the key difference between an ultralow-IQ buck and a “low-power” buck?
An ultralow-IQ buck targets microamp or even sub-microamp quiescent current and relies on PFM/auto-save and UVLO hysteresis, while a generic “low-power” buck may still draw tens of microamps at light load. Always compare Iq(max) and temperature drift, not only typical values. See Parameters.
2) Will PFM low-frequency ripple affect ADC or RF, and how can I mitigate it?
Yes; PFM ripple can modulate sensitive analog and RF paths. Use post RC or a small LDO for the affected rail and force PWM during sampling or TX windows to avoid aliasing. See Modes and Layout.
3) How do I estimate and verify the PFM↔PWM transition thresholds in AUTO mode?
Base the estimate on load profile and ripple budget, then sweep load slowly to capture PFM→PWM and PWM→PFM thresholds and hysteresis across temperature. Avoid transitions during critical tasks. See Validation.
4) How do I evaluate efficiency and thermal risks during deep-dropout sustain?
Use VIN(min) ≈ VOUT + ILOAD·(RHS + DCR) to predict when regulation is lost, and measure temperature rise because conduction loss increases in near-linear mode. Inductor DCR, HS RDS(on), and wiring resistance dominate. See Parameters.
5) How should I set UVLO thresholds and hysteresis to match the battery curve?
Align UVLO on/off thresholds with the MCU brown-out level and expected VIN sag near end-of-life. Adequate hysteresis prevents brown-out thrash, especially at low temperatures where ESR rises. See Parameters.
6) After deep battery discharge, how can I ensure reliable start-up?
Choose parts that support low-VIN start, soft-start, and pre-bias, then validate PG sequencing and consider pre-charging or larger output capacitance for burst tasks. See Operating Principle.
7) What are common pitfalls when measuring Iq?
Fixture leakage above 100 nA, meter range and bandwidth errors, and insufficient settling time can distort results. Log mode, VIN, VOUT, and temperature and repeat at −20/−40 °C. See Validation.
8) When should I use LDO + buck versus a direct buck?
For very noise-sensitive rails, a post LDO gives predictable ripple at the cost of efficiency and area; otherwise a direct ultralow-IQ buck is simpler and more efficient. Match LDO dropout and bandwidth to switching frequency. See Layout.
9) When is forced PWM mandatory?
Use forced PWM during measurement, audio, or RF-critical windows or whenever ripple must be tightly bounded; revert to AUTO/PFM afterward to save energy. See Modes.
10) How should I size output capacitance and compensation for burst loads?
Increase Cout and select ESR for stability and recovery, use soft-start and PG timing, and consider short forced-PWM windows or pre-charge for heavy bursts such as RF TX or flash writes. See Parameters.
11) How do low temperatures (−20/−40 °C) affect Iq, UVLO, and thresholds?
Iq typically rises and thresholds can drift at cold; repeat validation at multiple temperatures and account for cell ESR increase and deeper VIN dips under load. See Validation.
12) Will pre-bias start-up disturb the load?
Use devices specified for safe pre-bias operation to avoid back-feeding or pulling the rail down; confirm with power-sequence tests and external source injection. See Operating Principle.
13) How do I translate Iq (typ) vs (max) into battery life?
Estimate worst-case life using Iq(max) at cold and plug it into the average power model with your duty cycle and payload; typ values can over-predict life in winter. See Applications.
14) How do inductor, diode/synchronous FET, and capacitors affect ultralow-power behavior?
Inductor DCR and saturation, rectifier behavior or synchronous timing, and capacitor ESR/ESL shape the light-load efficiency and ripple; layout loop areas and parasitics are equally critical. See Layout.
15) For small-volume cross-brand substitution, which three parameters should I lock first?
Lock Iq (typ/max with temperature), availability of PFM/AUTO/forced-PWM and their thresholds, and UVLO with hysteresis; then check VIN/VOUT, IOUT, package/thermal, and features like pre-bias and PG. See IC Selection and Submit BOM.
Submit Your BOM (48h)
Still unsure which ultralow-IQ buck fits your battery device? Submit your BOM for a 48-hour cross-brand recommendation.
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