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1. Intent & System Context — Why we need “USB-C Sink + Charging Coordination”
Modern battery packs and BMS-based systems no longer take a fixed 5 V input. They take a programmable DC that comes from a USB-C / PD / PPS source, and this DC must be matched to the dynamic demand of the downstream charger or BMS. The USB-C side and the charger/BMS side are therefore two different worlds.
On the USB-C side, power is negotiated once (PDO list, PPS range, source capability). On the charger/BMS side, power is changing all the time: CC → CV → derate by JEITA → system-first. If the sink only “takes power” but does not coordinate, you get classic field issues: “plugged but not fast”, “drops when CV starts”, “long cable causes under-voltage”.
This page focuses on the sink role only. We assume the device is the one that wants power, that it must track or even drive PPS, that it may expose OTG/reverse-boost, and that it needs cable-drop-aware behavior. It is not the 2:1 / 4:1 charge-pump fast-charge path, and it is not the multi-cell charger controller itself; it is the bridge between the USB-C side and those downstream charging blocks.
In practice, engineers need a way to tell purchasing: “We are not buying a generic Type-C attach chip. We are buying a USB-C sink that can do PPS following, PDO power-share, cable drop compensation, and OTG/reverse boost, because our charger/BMS is not static.”
USB-C is only the entry
It provides negotiated power, not the final charging profile.
PD/PPS is the adjustable part
Charger/BMS must be able to tell what voltage/current it needs now.
Coordination decides matching
Without it, PPS may be valid but charging still looks “broken”.
2. USB-C / PD / PPS Front-End — Where the capability really comes from
A USB-C powered BMS or charger can only ask for what the PD source advertises. The source publishes a list of fixed PDOs (for example 5 V, 9 V, 15 V, 20 V) and sometimes a PPS range (for example 3.3–11 V, 50 mV step). The sink must match its downstream charger demand to one of these advertised capabilities.
The CC line is responsible for attach/detach, orientation, and initial current capability advertisement. Only after that can the PD capability discovery run. If discovery shows only 5 V or a BC1.2 fallback, the system must degrade to limited-power charging.
PPS is required when your downstream charger or BMS does dynamic input tracking (CC → CV → derate). PPS following, however, is not infinite: it has a step size, a timing limit, and it can never exceed the power of the adapter itself. This is why “just add USB-C” is not enough.
2.1 CC line
Attach/detach, orientation, initial current. No PPS yet.
2.2 PD capability discovery
Source gives PDO list + PPS range. Sink must choose.
2.3 PPS following
Tracks charger’s changing demand, but within step/time/power limits.
2.4 Fallback
BC1.2 or 5 V only → limited-charge mode.
3. Coordination Layer with Charger/BMS — who owns the decision
The coordination layer is the bridge between the USB-C / PD / PPS front-end and the dynamic charger/BMS backend. The front-end negotiates power once, but the charger/BMS keeps changing its demand (Precharge → CC → CV → Recharge → JEITA derate → system priority). Without a coordination layer, a sudden current request from the charger can trip the PD source, cause OCP, or even drop the USB-C link.
This layer collects inputs from the charger status machine, from BMS temperature/NTC/JEITA windows, and from the current system load, then translates “I need Vin / Vin_min / Iin_max” into a PD/PPS request that the USB-C sink can actually pull from the source. It also decides when to reduce power, for example when the battery pack is in protection, when a 2S–6S charger suddenly asks for 15 V, or when system load must stay alive.
Inputs to the layer
Charger state (Precharge, CC, CV), BMS thermal/JEITA, system load.
Translate to PD/PPS
Map Vin / Vin_min / Iin_max into actual PDO / PPS request.
Protect the USB-C link
Smooth sudden current ramps, avoid front-end OCP and detach.
Work with pack protection
If pack FETs are off, reduce or stop PD draw.
Two typical coordination styles
Charger-as-leader: the charger/BMS tells the USB-C front-end “I need 15 V @ 2.5 A now”. The PD/PPS engine then tries to get that from the source.
PD-as-leader: the USB-C front-end exposes “I can give 36 W” and the downstream charger adapts its charge current to stay under that budget.
5. Cable Drop Compensation — not every USB-C cable is the same length
Even if the USB-C / PD negotiation is correct (for example, 15.0 V requested), the charger/BMS input may only see 13.9–14.2 V because of line/cable/connector loss. The charger then says “I can’t enter fast-charge / multi-cell mode” and the engineer thinks “PD didn’t give me enough”. In reality the PD did its job — the cable dropped the voltage.
This section defines how to push VBUS up to compensate IR/cable drop, how to link it to PPS (because PPS is not fixed), and why the charger/BMS side must have a tolerance window to avoid oscillation. For automotive/industrial harnesses, where the cable is longer and hotter, this feature is even more important.
Fixed compensation
Add +0.2 / +0.3 / +0.5 V for short and known cables.
Current-based estimation
ΔV = I × R_line, scales with PPS current.
Table-driven / harness-aware
PD IC stores cable/connector profiles; automotive harness → larger ΔV.
Charger tolerance
Downstream must accept a window to avoid “step-chasing”.
For purchasing, specify a PD/USB-C controller that supports line-drop / IR compensation or exposes registers so the host/charger can push a compensation value. This applies across TI, ST, NXP, Renesas, onsemi, Microchip, and in automotive harnesses can be paired with Melexis sensing/diagnostic parts.
6. OTG / Reverse Boost Back to VBUS — obey BMS even in reverse
OTG or reverse-boost means the system has energy in the battery/VSYS and wants to push power back to VBUS to feed a phone, a sensor node, or another board. This does not mean we can bypass pack protection. Reverse direction still has to go through the pack FET / protection / gate-driver path, so that all BMS rules (OVP, UVP, OTP) stay valid.
Reverse mode must also be exclusive: when OTG is active the USB-C port should not act as a sink at the same time, or connector/policy will conflict. And reverse power must still respect the system-first / PDO power-share policy from the previous chapter — OTG is residual, not primary.
Reverse path
Battery/VSYS → protection path → boost → VBUS.
No simultaneous sink
OTG active ⇒ disable sink role to avoid conflicts.
Power-share applies
System first, charge second, OTG only if budget allows.
Diagnostics
Check detach, temp, pack status; Melexis-type sensors for automotive.
Verification points
• Start OTG → unplug USB-C → device must detect detach and stop boost.
• Start OTG in hot conditions → system must derate output or stop.
• If pack/BMS is in protect state → block OTG or limit to safe current.
7. Integration with Multi-Cell / System Power-Path — connect to the other BMS pages
A USB-C PD / PPS front-end is only the entry. Behind it you may have a 2S–6S charger that wants 12–20 V, or a single-cell buck charger that is happy with 5–9 V, and very often you also have a VBAT↔VSYS power-path that must keep the system alive even when the battery is empty. This chapter defines how the USB-C sink + coordination layer chooses PDO/PPS and forwards power to downstream blocks without breaking the “system-first” rule from your BMS home page.
Multi-cell (2S–6S)
Pick 12–20 V PDO or open PPS to match charger input.
Single-cell buck charger
5–9 V fixed PDO is enough, PPS changes less often.
VBAT↔VSYS power-path
System-first, battery is residual, follow PD budget.
Fixed upstream / OBC
If DC-DC already fixed, this layer downgrades to “fixed in + charge limit”.
8. Faults, Fallbacks & Safety Windows — typical field failures
USB-C negotiation can succeed but the real device still cannot fast charge. This is usually not because the protocol is wrong, but because the coordination with the charger/BMS wasn’t finished: PD fell back to 5 V, PPS couldn’t track CV, cable drop was worse than expected, OTG had no load, or a JEITA window forced derating. This section groups the most common faults and the correct actions an engineer should implement.
Negotiation fail → fallback 5 V
Charger must drop to low-power mode; host should be notified.
PPS can’t follow CV
Step down to closest fixed PDO or slow down charger ramp.
Cable drop still too large
Warn + reduce current + request better cable.
OTG no load
Timeout and exit OTG to avoid wasting energy.
NTC / JEITA not OK
Notify PD front-end to derate; log thermal limit.
I²C / SMBus address clash
Plan addresses for PD + charger + BMS; add retry.
9. Procurement / Small-Batch Notes — for sourcing people
This page is not about USB-C in general, it is about a USB-C sink that must coordinate with a separate battery charger/BMS. Not every PD controller can do that. For small-batch, automotive, or cross-brand sourcing, tell buyers exactly what to look for so they don’t send back “just a C port chip” that has no I²C-control or no PPS.
9.1 Pick PD controllers with I²C-controllable PDO/PPS
Many USB-C/PD sink chips only let you pick from a fixed set of PDOs. In this BMS flow, the charger/BMS tells the front-end what Vin / Iin_max it needs, so you must source parts that expose PDO/PPS selection over I²C / SMBus / policy registers. That’s the key difference.
9.2 Order extra for engineering validation
Chips that combine tight packages + full PD3.0 + PPS + cable compensations are typically harder to rework. For trial runs, buy +2~3 pcs beyond the BOM so R&D can validate PPS following, cable-drop behavior, and reverse/OTG policies on real harness length.
9.3 Lock parts earlier for automotive / wide-temp
If the design is going into automotive / industrial harness where the cable is longer, warmer, and with more connectors, line-drop compensation and thermal reporting become mandatory. These PD controllers tend to have longer lead times → lock them earlier.
Tell purchasing to check: AEC-style qualification (where available), PPS support, I²C visibility, and whether the vendor offers matching charger/BMS front-ends.
9.4 Keep room for brand swaps (TI ↔ ST ↔ NXP ↔ Renesas ↔ onsemi ↔ Microchip ↔ Melexis)
Your site is on a cross-brand replacement route. That means on every PD sink + charger pair you should document at least one alternative from the seven core brands: TI, ST, NXP, Renesas, onsemi, Microchip, Melexis.
For buyers, write: “PD sink must support PPS and expose I²C registers; if TI part is not available, look for ST / Renesas / onsemi PD with the same I²C exposure.” This keeps the coordination logic in firmware the same.
Submit BOM (48h): cross-brand PD front-ends + charger pair
Submit BOM (48h)10. Frequently Asked Questions
Only questions that this page can answer — we stay in scope: USB-C sink role, PPS following, charger/BMS coordination, cable drop, OTG through protection, and procurement issues.
Does every USB-C controller support PPS following?
No. Some only expose fixed PDOs. For BMS coordination you need I²C-controllable PDO/PPS so the charger can request new voltage/current.
What happens if PD negotiation fails and we only get 5 V?
The downstream charger must enter low-power mode. Log the fallback and notify the host; do not try to fast-charge on 5 V.
How do we prevent cable drop from blocking fast charge?
Use line-drop / IR compensation linked to PPS current, and keep a ±2–3% window on the charger input detection to avoid oscillation.
Can OTG / reverse boost run while the port is in sink mode?
No. Keep roles exclusive. OTG must go through the protected pack path and must not collide with a simultaneous sink.
What if the multi-cell charger suddenly needs 15 V?
The coordination layer must request a higher PDO/PPS from the source. If the adapter can’t supply it, throttle the charger, keep system alive.
Why is “system-first” always enforced?
Because USB-C power can be limited (30–45 W). If the system turns off, the whole BMS path is meaningless. So VSYS first, battery charge is residual.
Can we use a non-PD USB-C source (5 V only)?
Yes, but the charger must downgrade to 5 V charging. Document this for purchasing so they know not all C ports are equal.
How to handle NTC / JEITA temperature limits?
Let BMS tell the PD front-end to reduce power. No derate on the back-end alone — front-end must know to avoid link drops.
What to tell purchasing about brand flexibility?
Ask for PD sinks with I²C-exposed PPS across TI, ST, NXP, Renesas, onsemi, Microchip, Melexis. This keeps your firmware strategy.
Why does my charger report “input too low” even after PPS?
Probably cable drop is still larger than the compensation. Add more margin or switch to a better/shorter cable.
Can one I²C bus serve PD + charger + BMS?
Yes, but plan addresses first. Avoid clashes and add retry/backoff logic.
Where do I submit BOM for a 48h cross-brand match?
Use the form: Submit BOM (48h). We can propose PD sink + charger pairs across the 7 brands.
