123 Main Street, New York, NY 10001

Submit Your BOM

Hold-Up & Backup for AC Adapters with Supercapacitors

Hold-Up & Backup for AC Adapters with Supercapacitors

← Back to: Power Supplies & Adapters

This page walks you through energy sizing, supercap charging, power-path OR-ing and fast shutdown handshakes so adapter-powered systems stay reliable even when mains power flickers.

What this page solves – adapter brown-out and data-loss risk

Small AC dips, loose connectors or quick adapter plug events can pull the DC rail down in milliseconds, forcing MCUs to reset mid-write, corrupting file systems and freezing protocol stacks.

  • Users experience “black screen” or lost settings when the adapter is touched or briefly unplugged.
  • Bulk electrolytics at the adapter output provide only a short, poorly controlled hold-up window.
  • Brown-out recovery is unobservable, with no event logging for field diagnostics.

This page focuses on converting random power loss into controlled shutdown: a supercapacitor-based hold-up/backup stage that keeps the rail alive long enough to flush data, park actuators and log a precise power-loss event.

Scope: this page does not cover PFC/LLC topologies. It stays at the adapter output and the small hold-up module that lives close to the adapter or on the front-end board.
Adapter brown-out risk versus supercapacitor hold-up concept Diagram comparing a basic adapter output with only a bulk capacitor that drops during AC disturbances and resets the MCU, against a supercapacitor hold-up path that keeps the rail alive long enough for controlled shutdown and logging. No hold-up With supercap hold-up AC Adapter Bulk cap only DC rail MCU & Storage File system / settings Brown-out reset · random data loss Adapter Main output DC rail with hold-up Supercap hold-up Controlled rail support MCU & Storage Controlled shutdown & log Hold-up window keeps logic alive long enough to flush data, park outputs and store a tagged power-loss event.

Where hold-up lives in an adapter system – architecture & boundaries

Hold-up energy can be placed on the high-voltage DC bus after PFC or on the low-voltage adapter output. High-voltage hold-up is typical for ATX and server PSUs; this page focuses on low-voltage hold-up near 12 V / 19 V / 24 V rails that feed system electronics.

  • High-voltage bus hold-up: PFC output capacitors or dedicated hold-up banks. Suited to ATX/CRPS/server designs and covered on the server PSU page.
  • Low-voltage side hold-up: supercap pack, ideal-diode/OR-ing stage and supervisor directly on the adapter output rail. This is the main architecture on this page.

For USB-C adapters, the hold-up rail attaches at the negotiated high-voltage output (for example 20 V) after the PD stage and eFuse, without modifying PD/QC protocol behavior.

Boundary: downstream multi-rail DC-DC sequencing and board-level power trees belong to the “Downstream rails & supervisors” pages. Here the perspective is the adapter or a small front-end board living next to it.
High-voltage bus hold-up versus low-voltage adapter-side supercap hold-up Diagram showing a PFC and high-voltage DC bus hold-up path, contrasted with a low-voltage adapter output where a supercapacitor, ideal-diode and supervisor provide local hold-up, including the connection point for a USB-C PD stage. High-voltage bus hold-up Low-voltage adapter hold-up (focus) AC PFC High-voltage DC bus HV hold-up mainly used in ATX / server PSUs (covered on server PSU page). Adapter 12 V / 19 V / 24 V LV rail Supercap hold-up Local energy storage Hold-up node near system rail Supervisor PG / reset / fault System board DC-DC / logic USB-C PD / eFuse For USB-C adapters, the supercap hold-up attaches after the PD / eFuse stage at the negotiated high-voltage rail.

Supercap energy budgeting for hold-up time

This section explains how to translate an adapter’s hold-up requirement into a practical supercap bank size, using the classic energy formula and a clear, step-by-step sizing flow that stays at adapter time scales (hundreds of milliseconds to a few seconds), not ESS-level storage.

The designer first fixes the allowable voltage sag window on the adapter rail (for example a 12 V system that can run down to 9 V), then estimates the power of the protected load. With these two numbers, the required stored energy for a given hold-up time window is computed.

Energy in the supercap bank is approximated by: E = ½ · C · (Vstart2 − Vend2), and the usable hold-up time by thold ≈ E / Pload. The text walks through how to plug in numbers for different hold-up goals, such as 200 ms for MCU flush and relay release, versus 1–2 s for logging and reporting.

Finally, the section maps the required equivalent capacitance into a real supercap stack: series strings to meet voltage rating, parallels to reach total capacitance, and the trade-offs between footprint, cost and safety margin. It also hints at how more generous hold-up targets quickly push capacitance and volume, helping readers choose realistic design points.

Supercap energy sizing and hold-up time window for adapter rails Block diagram showing adapter output feeding a load and a supercap bank, with a voltage sag window from Vstart to Vend and a hold-up time window used to size capacitance using energy equations. Supercap energy budget for adapter hold-up Adapter rail 12 V / 19 V / 24 V Load Pload Supercap bank Ceq & V rating Rail voltage vs time during power loss V rail time Vstart Vend t hold E = ½ · C · (V 2 start − V 2 end) t hold ≈ E / P load

Supercap charging, balancing and inrush control

This section focuses on how to charge and manage a supercap bank on the adapter side without collapsing the adapter rail or tripping upstream protection. The goal is a predictable, limited inrush and a well-balanced stack, not a full BMS like an energy storage rack.

The text walks through constant-current limited charging at start-up, transitioning to constant-voltage or trickle once the supercaps approach the target voltage. Designers see how a simple current limiter or dedicated supercap charger IC prevents the adapter from seeing a hard short at plug-in.

For series-connected supercaps, passive or active balancing is needed to keep individual cell voltages within rating. The section compares resistor bleed, shunt regulators and simple active balance controllers, highlighting where each approach fits in adapter-scale hold-up designs.

Finally, the diagram and text hint at temperature and ESR monitoring as optional hooks for deeper health tracking, but detailed diagnostics and hot-swap behavior are left for the dedicated eFuse and protection pages to avoid overlap.

Supercap charger, current limiting and balancing for adapter hold-up Block diagram showing adapter output feeding a current-limited supercap charger, series supercap stack with balancing, and a separate path to the load, emphasizing inrush control and voltage equalization. Supercap charging, balancing and inrush control Adapter rail 12 / 19 / 24 V Load rail normal adapter load Supercap charger I-limit & CV / trickle Supercap stack balancing T ESR Charger inrush profile I charge limited ramp • Charger limits inrush into supercaps • Balancing keeps each cell within rating

Power-path OR-ing and fast switchover

In an adapter hold-up system there are two supply paths feeding the same downstream bus: the main adapter rail and the supercap backup rail. The power path must steer the load to the preferred source under normal conditions and transfer quickly to the backup source during brown-out without cross-conduction.

The main adapter output usually passes through an eFuse or ideal-diode controller before reaching the system load, while the supercap pack is connected through back-to-back MOSFETs or another ideal-diode stage. OR-ing controllers and Hot-Swap ICs enforce reverse blocking, safe operating area (SOA) limits and fast but controlled switchover timing.

  • Main path: Adapter output → eFuse / ideal diode → system rail.
  • Backup path: Supercap pack → ideal diode / back-to-back MOSFETs → system rail.
  • Switchover delay: Must be short enough to keep the bus within the allowed droop window during adapter brown-out.
  • Cross-coupling: OR-ing design prevents the two sources from back-feeding each other during startup, brown-out or fault conditions.
  • IC roles: eFuse, ideal-diode controllers and Hot-Swap drivers placed in the hold-up path, complementing the higher-level eFuse page that covers their full feature set.
Power-path OR-ing between adapter and supercap hold-up Block diagram showing an adapter path and a supercap backup path feeding one system rail through eFuse, ideal-diode and Hot-Swap stages with fast switchover and reverse blocking. Adapter Main Output Supercap Hold-Up Pack eFuse / Ideal Diode Main Path Control Ideal Diode / FETs Backup Path Control System Rail & Load Shared Hold-Up Rail Main Path to Rail Backup Path to Rail Switchover Timing UV detect & delay budget eFuse & Hot-Swap devices enforce OR-ing and SOA limits
OR-ing between adapter and supercap paths for fast, safe switchover.

Fast shutdown, data flush and system handshakes

Once a mains or adapter failure is detected, the hold-up system must notify the digital controller quickly enough that firmware can execute a graceful shutdown script within the available supercap energy budget. Power-good, AC-fail and bus undervoltage signals form the handshake between power hardware and software.

Typical sequences assert an interrupt or PMBus alert, shed non-critical loads and keep only storage and communication rails alive from the hold-up path. Logs are written, faults are recorded and remote alarms are sent before the system allows the bus to fall to a defined cutoff level. This section focuses on the adapter and hold-up module side; the Digital PSU Controller page covers the full PMBus parameter and logging strategy.

  • AC/bus sensing: PFC bus undervoltage, adapter power-good and mains comparators provide early warning of brown-out.
  • Signalling: GPIO, dedicated AC-fail pins or PMBus alerts notify the MCU or digital PSU controller.
  • Shutdown script: Firmware disables heavy loads, prioritizes storage and communication, and schedules log writes.
  • Event logging: Supply drop and recovery events are tagged with rail voltages, counters and timestamps.
  • Coordination: Handshakes guarantee that the system reaches a safe state before the hold-up energy is exhausted.
Fast shutdown and data flush using hold-up energy Block diagram showing AC fail sensing, a hold-up controller, MCU interrupt and shutdown sequence, with selected loads kept alive from a supercap-backed rail. AC / Bus Sensing PFC UV, AC Fail, Adapter PG Hold-Up Controller UV detect, PG, Alert MCU / Digital PSU ISR / PMBus Engine AC Fail / UV PG / Alert / IRQ Supercap Rail Hold-Up Voltage Critical Loads Storage & Comms Shutdown Sequence Flush, Log, Notify Hold-Up Power Control & Status Firmware actions Early AC fail detection maximizes time for data flush and logging
AC fail sensing, hold-up control and firmware handshakes for graceful shutdown.

Design checklist & IC role mapping for adapter hold-up modules

Use this checklist to turn vague “survive brown-outs” wishes into a concrete, reviewable hold-up/backup design with clear IC roles.

1. Requirement definition

  • Hold-up time target (thold-up): for example, 100–300 ms for safe reset, 0.5–2 s for log write and network reporting.
  • Load power window (Pload): nominal and worst-case power during backup, including peaks from CPUs, memory and communication modules.
  • Allowed bus droop: start and end voltage, such as 19 V → 12 V, or 12 V → 9 V while the system stays functional.
  • System state during hold-up: full functionality, reduced performance, or “keep-alive only” with storage and communication rails.

2. Supercap and capacitor selection

  • Working voltage margin: choose rated voltage above Vstart with derating for temperature and lifetime.
  • Effective capacitance: size C from E = ½·C·(Vstart2−Vend2) and thold-up≈E/Pload, then map to series/parallel supercap stacks.
  • ESR and surge current: verify that ESR supports the required di/dt without excessive droop or self-heating during switchover.
  • Lifetime and environment: check cycle life, operating temperature, vibration profile and safety ratings appropriate for the adapter’s target market.

3. Charging, balancing and thermal behaviour

  • Input current limiting: define maximum allowed inrush into the supercap bank at plug-in so the adapter does not trip OCP or hiccup.
  • Charge profile: constant-current region, transition to constant-voltage, and trickle/maintenance strategy when the adapter stays online for long periods.
  • Series balancing: choose passive or active balancing and set thresholds so cell voltages remain within safe limits over temperature and aging.
  • Thermal design: estimate loss in series resistors, FETs and balancers, and plan copper area or heat-spreading paths around the supercap bank.

4. Power-path and protection strategy

  • Number of paths: define how many rails need hold-up (for example, main 12 V rail only, or additional backup for 5 V/3.3 V logic rails).
  • OR-ing implementation: decide between diode OR-ing, ideal-diode controllers or Hot-Swap/eFuse devices with back-to-back MOSFETs.
  • Reverse and back-feed blocking: ensure that the supercap bank cannot feed back into the adapter or upstream PFC/LLC stages.
  • Fault responses: define behaviour for supercap short, FET short, open sense lines and over-temperature, including safe disconnect rules.

5. Monitoring points and measurement resolution

  • Voltages to monitor: adapter output, hold-up rail, individual supercap stack voltages and key downstream system rails.
  • Currents to monitor: charge current into supercaps and discharge current into the load, with suitable shunt or isolated sensing.
  • Temperature sensors: locations on the supercap bank, hot FETs and series resistors for thermal derating and protection.
  • Resolution and sampling rate: choose ADC resolution and sampling speed to reliably detect brown-out, over-current and runaway charging.

6. System interfaces and handshakes

  • Digital alarms: plan PG/FAULT pins, “AC fail” flags and power-loss early-warning signals to the system controller.
  • Bus interface: decide whether PMBus, SMBus, I²C or simple GPIO is required for configuration and logging.
  • Event logging: define which events (brown-outs, abnormal discharge, thermal limits) must be timestamped and stored in non-volatile memory.
  • Coordination with other pages: align status flags and telemetry with the Digital PSU Controller and eFuse/Hot-Swap protection strategies.

7. IC role mapping (no vendor names)

  • Supercap charger / balancer IC: handles controlled current-limited charging, voltage regulation and passive or active cell balancing.
  • Ideal-diode / eFuse / Hot-Swap controller: drives back-to-back MOSFETs for OR-ing, reverse blocking, programmable current limit and fault isolation.
  • Voltage and current measurement front-end: current-sense amplifiers, shunt monitors or ΣΔ / multi-channel ADCs for rail and supercap monitoring.
  • Supervisors and comparators: UV/OV comparators, window supervisors and timing devices to generate early-warning and reset signals.
  • System controller / PMBus interface: MCU or digital power controller that interprets alarms, manages power-loss scripts and exposes telemetry to higher-level software.

With these checklist items and IC roles defined, the adapter hold-up module becomes a structured part of the power architecture, ready for schematic capture, BOM selection and safety review.

Request a Quote

Accepted Formats

pdf, csv, xls, xlsx, zip

Attachment

Drag & drop files here or use the button below.

H2-10. FAQs – Adapter hold-up & supercap backup

1) When is an adapter hold-up module actually needed?
A hold-up module is needed when even short AC dips or connector wobbles can corrupt data, reset controllers, or break network sessions. If users expect “graceful shutdown” and reliable logging instead of random black screens, a defined hold-up time with supercaps and system handshakes becomes a system requirement, not a luxury.
2) How much hold-up time is typical for small adapters?
Typical hold-up targets range from 100–300 ms for microcontroller state saving, up to 1–2 seconds if logs must be flushed and a final message sent over Ethernet, Wi-Fi, or fieldbus. Longer times demand larger and more expensive supercap banks, so requirements should be negotiated carefully instead of assuming seconds of backup “for free.”
3) How is supercap size chosen for a given load and time?
Supercap sizing starts from energy: E = ½·C·(Vstart² – Vend²), then relates that to hold-up time with thold ≈ E / Pload. Designers choose Vstart near the adapter rail, Vend at the minimum operating voltage, and solve for C. The result is mapped into series/parallel stacks considering voltage rating, ripple current and ESR.
4) What are the pros and cons of supercaps versus big electrolytics?
Supercaps store much more energy per volt swing and tolerate many more charge cycles, making them ideal for frequent brown-outs and controlled shutdowns. However, they need careful charging, balancing, and inrush limiting, and they occupy volume. Large electrolytics are simple and cheap but provide only short, poorly controlled hold-up and suffer lifetime limits.
5) How should supercap charging avoid tripping the adapter OCP?
Supercap charging should use a current-limited profile that ramps up gently from zero and respects the adapter’s rated output and OCP threshold. Many designs use a dedicated supercap charger or a DC-DC stage with programmed current limit, often combined with soft-start and thermal monitoring so the adapter does not see a hard short at plug-in.
6) Why is cell balancing important in multi-supercap stacks?
In series stacks, small capacitance and leakage differences cause unequal voltage sharing, so one cell can exceed its rating even when the total stack voltage looks safe. Passive balancing resistors or active balancer ICs keep cell voltages aligned, improving lifetime and safety and allowing the full stack voltage rating to be used confidently.
7) How does power-path OR-ing prevent the adapter and supercap from fighting?
Power-path OR-ing uses ideal-diode controllers, eFuses, or back-to-back MOSFETs so current flows from the preferred source while reverse flow is blocked. When the adapter drops, the supercap path turns on within microseconds to milliseconds. Proper thresholds and timing prevent both sources from pushing against each other or circulating current between rails.
8) What determines whether switchover is fast enough?
Switchover speed must be compared with the load’s ride-through capability and local capacitance. If the bus droops below the minimum logic or converter input voltage before the supercap path takes over, resets and glitches occur. Designers combine timely AC-fail or rail-fail detection with low impedance paths so the bus barely sags during transfer.
9) How is fast shutdown and data flush typically orchestrated?
A power-fail or AC-fail signal triggers an interrupt or alert to the controller. Firmware then stops non-essential loads, freezes configuration changes, and writes only critical logs or counters. After confirming that data is safe and communications are finished, the system deliberately enters a known-off state before the supercap voltage reaches the defined cutoff.
10) How should supercap voltage and temperature be monitored?
Monitoring usually includes stack voltage, sometimes individual cell taps, charge current, and at least one temperature sensor near the capacitors. Simple comparators may be enough for brown-out thresholds, while higher-end designs use ADCs or monitoring ICs. The readings feed firmware that can limit charging, shorten hold-up time, or flag early degradation trends.
11) How does the hold-up module interact with a digital PSU controller or PMBus host?
The hold-up module can expose PG, PFAIL, or ALERT signals and optionally PMBus or I²C telemetry so the main controller sees remaining energy and recent power events. Digital PSU controllers may then adjust load profiles, log brown-outs, or trigger controlled shutdown scripts, making the adapter and hold-up section part of a coordinated power system.
12) What are common pitfalls when adding hold-up to an existing adapter?
Frequent mistakes include underestimating energy needs, ignoring supercap inrush, placing OR-ing devices in the wrong order, and forgetting thermal design. Another pitfall is providing hold-up on the main rail but not coordinating with downstream sequencing, so some rails collapse early. Early system-level budgeting and lab testing helps avoid these surprises.

icnavigator

ICNavigator helps engineers find verified ICs, alternatives, and fast quotes.

Explore
Categories
  • Power Management
  • MCU
  • Automotive ICs
  • Sensors
  • Interface & Transceivers
  • Analog Front-End
Get in Touch
  • Email: hello@icnavigator.com
  • WeChat/WhatsApp: +86-xxxx

© 2025 ICNavigator. All rights reserved.