Iin(t) = Isig(t) + Idark(T) + Ileak_total

Integrator / CSA readout (per sample window Tint):
  Qwin = ∫ Iin(t) dt  ≈ Iin_avg · Tint
  Vout ≈ Qwin / Cf

Leakage-to-code constraint (practical budgeting):
  Require V_leak = (Ileak_total · Tint)/Cf  ≤  k · LSB
  Where LSB = VFS / 2^N, k is margin (e.g., 0.25 for "¼ LSB" drift target)
  ⇒ Ileak_total ≤ k · (VFS / 2^N) · (Cf / Tint)

• Why this matters: Ileak and Idark are not “noise”; they create baseline shift that looks like random instability unless explicitly budgeted and measured.
• Cdet impact: larger input capacitance raises stability demands and increases susceptibility to coupling; it can also slow settling and break timing aperture consistency.
• Order-of-magnitude requirement: capture Imin/Imax and Idark(T) as bounds (not a single number). If bounds span multiple decades, integrator/CSA is often easier to budget.

• Why “it looks random”: small Ileak variations (humidity, contamination, handling) create a slow-moving baseline that inflates RMS unless separated by drift analysis.
• Front-end mitigation: guard sensitive nodes, minimize exposed high-impedance copper, keep ESD choices consistent with leakage budget, and validate with a long-run dark drift test.
• Acceptance tie-in: the leakage budget should be expressed as “≤ k·LSB drift over Tint” so it remains compatible with ADC resolution changes.

• Windowed sampling: is there a stable per-sample window Tint (fixed aperture and cadence)?
• Dynamic range: how many decades does Imax/Imin span under real exposure conditions?
• Input capacitance: how large is Cdet + Cpar at the AFE input node (including ESD/switch parasitics)?
• Baseline drift allowance: what is the maximum permitted drift within one window (e.g., “≤ ¼ LSB per Tint”)?
• Saturation & recovery: do near-full-scale bursts occur, and how quickly must the chain recover?
• ADC interface shape: is the ADC capture inherently sampled/held (window-friendly) or continuously tracked?

1. Pick the unit: use Qrms per Tint (Integrator/CSA) or Irms (TIA), then commit to it.
2. Define the mapping to codes: for Integrator/CSA, Vn = Qrms / Cf, then convert to ADC LSB RMS via full-scale.
3. Compute shot noise: include both signal current and dark current contributions at your operating temperature.
4. Compute reset/kTC term: treat it as a real floor unless CDS (or equivalent subtraction) measurably suppresses it.
5. Add amplifier + ADC + reference terms: map each to the same unit, then combine with RSS.
6. Validate with mode switches: use controlled toggles (CDS on/off, reference test mode, input short, timing variants) so each term can be isolated.

Shot noise is not only about “useful photons.” The dark current Idark(T) also produces a shot component. That is why low-signal stability can collapse at high temperature even if the analog chain is unchanged. In budgeting, always compute the shot term at the same operating point used for acceptance tests (temperature, window cadence, and baseline conditions).

Validation idea: run a dark acquisition across a temperature sweep and track RMS. If RMS rises strongly with temperature, the Idark-related term is likely consuming your low-dose budget.

In an integrator/CSA, each reset places the integration capacitor into a thermal state that appears as baseline uncertainty. This term can dominate the floor when Cf is small or when the reset cadence is aggressive. CDS (or two-sample subtraction) is valuable because it is a measurable mechanism to suppress reset-correlated uncertainty and slow drift components.

Validation idea: compare baseline RMS with CDS on/off using identical timing. If the measured delta is small, the floor is likely dominated elsewhere (shot, amplifier noise, or reference/ADC paths).

Amplifier voltage noise (en) typically maps through the loop’s noise gain, which becomes more sensitive as (Cdet + Cpar) grows. Amplifier current noise (in) behaves like an extra input current source; in a windowed integrator it accumulates over Tint into additional charge uncertainty. This is why a “low en” part is not automatically a win if input capacitance is large or if current noise dominates.

Validation idea: change Tint (or the effective bandwidth) and observe whether RMS scales in a way that matches the mapping you assumed. Budget terms that cannot be experimentally separated tend to become painful in production.

Quantization is a predictable RMS term tied to LSB size and effective resolution. Reference noise is often more subtle: it modulates codes directly and can mimic analog noise even when the input is quiet. In a well-balanced design, the ADC + reference equivalent input noise should be comfortably below the analog front-end floor (a common engineering target is “≤ one-third of the analog RMS,” or a clear dB margin).

Validation idea: use an input-short or internal test mode and compare RMS with different reference conditions. If RMS changes materially, reference integrity (buffering, decoupling, routing, load transients) is part of the root cause.

1. Reset the integrator/CSA node to a known starting condition.
2. Guard / settle (do not sample during reset tail or MUX transients).
3. Sample #1 (baseline capture, CDS “reference” sample).
4. Integrate for a defined Tint window.
5. Sample #2 (signal capture, CDS “signal” sample).
6. Hold the captured level and convert (ADC activity must not disturb the sensitive node).

CDS subtracts two samples taken close in time: a baseline sample and a post-integration sample. This cancels terms that remain sufficiently correlated between the two captures (offset, slow drift, and portions of reset-correlated behavior). It does not cancel terms that change significantly between the two sample instants, such as fast noise, aperture mismatch, or a long reset-injection tail that is still decaying during sampling.

In an array, each channel must measure the same physical window. If Sample #1 or Sample #2 shifts relative to reset/integration edges, different channels capture different points on settling tails and transient behavior. That error does not look like white noise—it becomes channel-dependent bias and visible fixed-pattern structure. Bandwidth alone cannot fix this; timing determinism can.

• Dark current vs temperature: shifts the low-signal baseline and shot floor; requires dark-mode capture and temperature tagging.
• Cf/Rf effective drift: changes scaling and baseline behavior; requires injection or known stimulus for repeatable gain checks.
• Reference drift: appears as global code drift and can mimic analog drift; requires reference switching/comparison modes.
• Timing drift: changes settling capture point; requires explicit logging of timing configuration and aperture alignment checks.

A calibration run is only trustworthy if the front-end can enter a controlled mode and explicitly label it in the output stream. The purpose here is simple: produce repeatable measurements for map generation and drift tracking.

• Dark mode: zero-input equivalent; used for offset map and drift tracking.
• Flat / stimulus mode: known stimulus or known injection; used for gain map and linearity checks.
• Short / clamp mode: force a known input condition; isolates chain noise and baseline behavior.
• Reference A/B compare: separate “reference drift” from “analog drift” by controlled switching and labeling.

• Shared reference / supply coupling: many channels move together; strongly correlated with conversion or load steps on VREF/AVDD. Signature: global, in-phase modulation.
• Ground bounce / return-path coupling: spikes aligned to digital edges; magnitude depends on loop area and shared return impedance. Signature: edge-locked, often polarity-consistent.
• Control-line edge coupling: reset/MUX/S/H edges capacitively inject into high-Z nodes (integrator input, PD node). Signature: deterministic step/impulse at fixed timing offsets.
• Neighbor capacitance (routing + detector parasitics): strongest on adjacent channels; worsens with longer parallel runs and weak guarding. Signature: local, adjacency-dependent coupling map.

Many “victim” deviations are not true coupling; they are incomplete forgetting of a previous channel or a previous state. This must be treated as a timing-and-impedance problem.

• S/H memory: the hold capacitor retains previous channel level and bleeds into the next sample if discharge/settle is insufficient.
• ADC sampling kickback: SAR sampling capacitors draw impulsive current; without isolation/hold discipline it disturbs the analog node.
• Reset tail residue: reset is not an ideal instant; sampling during tail decay creates channel-dependent bias and visible fixed patterns.

The only settling that matters is the deviation at the sampling instant (Sample #1 / Sample #2). Define an acceptance bound using an epsilon target: |V(t_s) − V(∞)| ≤ ε · V_FS (or ≤ ε in LSB RMS units). This links timing, output impedance, and transient tails to an actionable limit.

1. Single aggressor stimulus: excite one channel (known injection or controlled step); keep others quiet.
2. Victim map: measure response across neighbors and far channels to classify “local” vs “global” coupling.
3. Edge correlation: align waveforms to reset/MUX/S/H/convert edges; edge-locked spikes imply control/return coupling.
4. Reference + ground observe: probe VREF and a true quiet ground point; global motion indicates shared-node issues.
5. Timing sweeps: vary guard time, hold placement, and convert position; strong sensitivity implies settling/memory mechanisms.
6. Quantify: define X_t = ΔVictim / ΔAggressor (code or equivalent input) as the regression metric.

• Tint defines an effective bandwidth: longer Tint averages more, shrinking the noise passband.
• Short Tint increases reliance on conditioning: more wideband noise is available to fold into the sampled result.
• Window shape matters: “integrate-and-dump” behaves differently than continuous TIA; the filter must match the sampling model.

• Continuous TIA output + sampled ADC input: wideband noise and ADC sampling kickback require output isolation / bandwidth shaping.
• Edge-rich control activity near sampling instants: reset/MUX/convert edges can create deterministic folding into the baseband.
• Reference driver is not quiet or not stable: reference noise or ringing becomes code noise and may bypass CDS cancellation.

The reference path must remain stable during sampling and conversion. If the reference node rings or droops under sampling currents, the ADC converts that behavior as if it were signal. Conditioning is successful when reference motion at sampling moments stays below the allowed noise contribution.

• Isolate impulsive sampling currents from the sensitive node (small series R + local C, placed to keep loop tight).
• Stabilize the driver under the real load (avoid oscillation or peaking that increases out-of-band energy).
• Schedule conversion so sampling moments do not overlap the noisiest switching edges (timing is part of anti-alias control).

• In-band ENOB: effective noise within the readout window / conditioning bandwidth, not a “headline” datasheet number.
• Sustained per-channel rate: stable throughput and consistent behavior across channels, not peak burst capability.
• Deterministic latency: fixed, defined latency from sampling instant to data word, stable across modes and conditions.
• Reference + drive stability: reference noise/drift and sampling kickback translate directly into code noise and fixed patterns.
• Channel timing: simultaneous sampling vs interleaving mismatch (offset/gain/timing) as a fixed-pattern risk.

Practical rule: SAR selection succeeds when the design can keep the reference node stable and can guarantee that sampling events are isolated from the noisiest switching edges.

Practical rule: ΣΔ is safe for CT front-end timestamps only when the conversion pipeline has a published, testable “time meaning” for each output word.

Practical rule: pipeline ADCs behave well in CT front-ends when their latency is stable and the input network is designed to meet a settling-at-sample epsilon bound.

• Simultaneous sampling keeps time meaning clean; the key spec is channel-to-channel aperture skew and its stability.
• Interleaving trades hardware for calibration burden; offset/gain/timing mismatch must be bounded and regression-tested.

• Sample-index marker: identifies the sample number; used to detect gaps and confirm ordering.
• Line marker: defines line boundary; ties sample-index ranges to a line_id.
• Frame marker: defines frame boundary; ties line_id ranges to a frame_id.

A free-running counter provides monotonic time. A latch event captures counter_value at a defined alignment point (sample, line_start, or frame_start). The output stream must declare whether the marker is attached to sample-time or output-time; the difference is the deterministic latency of the conversion path.

• Monotonic rule: counter_value is non-decreasing; discontinuities must be flagged.
• Rollover rule: overflow is expected; rollover_count (or epoch) makes reconstruction unambiguous.
• Reset semantics: a reset event must be visible (flag) so downstream can treat it as a timeline break.

• Define the endpoints: from sampling instant (t0) to the output word carrying the marker (t1).
• Declare the mapping: which output word index corresponds to each sample-index marker.
• Characterize stability: confirm latency does not shift across modes/temperature; if it shifts, set latency_mode_changed.