Current-Steering DAC (CS-DAC) for Direct-RF and Wideband Synthesis
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Current-steering DAC performance is controlled by a chain: switching core → differential output network → clock quality → return paths/layout → repeatable testing. This page shows how to turn SFDR/IMD and spur problems into checkable owners and single-variable experiments, so results stop changing with every board spin.
What this page solves
Current-steering DACs can deliver hundreds of MSPS to multi-GHz update rates, but real-world SFDR/IMD often fails to match expectations. The common failure pattern is simple: the DAC looks “high resolution / high sample rate” on paper, yet spurs appear everywhere, IMD is poor, and one PCB spin can shift the spectrum dramatically.
The practical deliverable
Performance is controlled by a chain. This page breaks CS-DAC outcomes into five controllable links and shows how to close the loop with measurements—so “mystery spurs” become repeatable root causes, and fixes become verifiable design changes.
The five-link control chain
- Switching core & array: element mismatch + switching transients create code-dependent spurs and IMD.
- Output network: balun/transformer + load + return path often dominate wideband SFDR/IMD.
- Clock: jitter/phase noise sets the “cannot-be-improved” floor and reshapes close-in noise skirts.
- Return/PDN/layout: symmetry and current-loop control decide whether results survive a PCB respin.
- Test closure: repeatable measurement conditions separate real spurs from setup artifacts.
How to avoid “random spectrum” debugging
A CS-DAC spectrum looks complex because several mechanisms overlap. The fastest way to converge is to use single-variable experiments and classify what moves and what stays fixed.
- Spurs move with code / amplitude → switching core, segmentation, major-carry behavior.
- Spurs change with balun/load → output network, compliance, return-path symmetry.
- Noise skirt changes with clock source → clock jitter/phase noise chain.
- Odd/even distortion shifts with routing → differential imbalance, PDN coupling, layout loops.
- Clock A/B: keep tone constant, only swap clock; observe skirt/floor changes.
- Output-network A/B: keep registers constant, swap balun/load; observe spur/IMD shifts.
- Mode A/B: RTZ vs NRZ (if available); observe images, even/odd distortion trends.
- Return-path probe: temporary short reference/ground or local shield; observe sensitivity hot-spots.
This approach prevents two common traps: chasing every spur with a new “theory,” and mixing multiple changes per iteration. The goal is to assign each visible artifact to an owner link, then validate the fix by repeating the same test conditions.
Definition and where CS-DACs fit
A current-steering DAC forms an analog output by switching many unit current sources on or off and summing them into a differential output. Its speed comes from a simple idea: keep internal voltage swings small and perform waveform creation through fast switching rather than through large resistor or capacitor time constants.
Three hard constraints (the reason “paper specs” are not enough)
- It is fundamentally a differential current output. The external network (balun/load/return) sets the effective voltage waveform and can dominate SFDR/IMD.
- Switching non-idealities become spectrum artifacts. Timing skew, charge feedthrough, and element mismatch show up as code-dependent spurs and intermodulation.
- Layout and return paths are part of the DAC. Differential symmetry and current-loop control decide whether performance survives routing changes and PCB respins.
Best-fit use cases
- Direct-RF / wideband synthesis: high output frequency and wide modulation bandwidth.
- RF/IF transmit chains: SFDR/IMD in a defined band matters more than DC absolute accuracy.
- Wideband AWG: waveform purity controlled by output network + clock + measurement closure.
When CS-DACs are the wrong tool
- Extreme DC accuracy and drift priority: choose precision setpoint DACs or delta-sigma DAC approaches.
- “Voltage-output only” system constraints: if a differential current output network is not feasible, another output form is usually safer.
- No access to RF measurement closure: without repeatable SFDR/IMD testing, convergence is slow and results are fragile.
Clock budgets and jitter-cleaning design, JESD204B/C alignment details, and reconstruction/anti-image filter synthesis are handled in their dedicated pages. This page only states how those topics enter CS-DAC performance and how to validate their impact.
Principle: unit current cells, switching, and segmentation
A current-steering DAC turns a digital word into a differential analog waveform by summing many unit current cells through fast switching. Its performance is not only “how many bits,” but how cleanly the architecture controls current accuracy, output modulation, and switching transients. The same mechanisms that enable GHz-class updates also create the dominant RF artifacts: code-dependent spurs, IMD, and sensitivity to layout and output networks.
The three jobs of a unit current cell
Unit mismatch becomes code-dependent spectrum errors. If spurs change with amplitude or with specific code regions, the artifact often belongs to the cell set/match domain rather than to the clock source.
The output network causes voltage swing at the DAC pins. If cell output resistance is not high enough, the “current source” is modulated by that swing, and IMD rises. This is why changing a balun/load can visibly shift SFDR/IMD.
Switching creates fast transients (feedthrough, charge injection, timing skew). Those transients translate into spurs, image leakage, and distortion. If artifacts change strongly with RTZ/NRZ mode or edge timing, the owner is usually the switching domain.
Why segmentation matters (thermometer + binary in CS-DAC context)
Segmentation is not a “bit trick.” It is how the DAC controls how many elements toggle at once and how sensitive the output becomes to skew and transient mismatch. A thermometer-coded MSB block reduces large, abrupt changes; a binary LSB block preserves efficiency; a segmented architecture limits the worst-case switching event.
Near major carry, many elements may change state within one update. Timing skew and feedthrough add up. If distortion/spurs worsen only in certain amplitude/code regions, this is a strong indicator that major-carry switching is involved.
- Timing skew: imbalance during transitions → IMD / even-order rise / image asymmetry.
- Switch feedthrough: clock/data coupling → fixed-family spurs and edge-sensitive artifacts.
- Element mismatch: code-dependent errors → spurs that track code patterns and amplitude.
Design: translate spectral targets into controllable parameters
CS-DAC design converges when requirements are expressed as a spectral target (band, mask, SFDR/IMD) and then mapped into parameters that can be owned by circuit decisions, layout constraints, and test plans. The critical shift is to treat “great datasheet numbers” as insufficient without curves and measurement closure.
Core metrics that must be specified as “band + condition”
- SFDR: meaningful only with an output-frequency band and observation bandwidth.
- IMD3 (two-tone): defines linearity under modulation; must include tone spacing and level.
- Noise floor / skirt: separate close-in skirt behavior from wideband floor.
- Output bandwidth: not just fs; it is the band where images/spurs must stay under a mask.
- Spur/mask limits: convert “clean spectrum” into explicit limits across frequency.
Map metrics → controllable parameters (what to own)
- fs and supported output frequency range for the target band.
- Interpolation / DUC / NCO capability (if integrated), and its spur implications.
- Full-scale current (IFS) and required load for target level.
- Compliance and output common-mode limits (avoid hidden IMD cliffs).
- RTZ/NRZ modes and usage constraints (images / even-order trends).
- Clock cleanliness: verify impact via clock A/B (skirt and floor behavior).
- Supply/ground partition: prevent switching return from modulating reference/bias nodes.
- Reference/bias stability: define what “stable enough” means via spur and drift tests.
Side effects to plan for (predictable trade-offs)
- Higher fs / wider band typically increases sensitivity to output-network and routing symmetry.
- RTZ mode may improve images/even-order behavior in some bands but can raise switching activity and power.
- More aggressive spectral masks demand more measurement discipline (repeatability and artifact control).
Verification closure (how to prove ownership)
- SFDR sweep: across the target output band under the same RBW/window/tone plan.
- Two-tone IMD3: fixed spacing and level; confirm trends with load/network A/B.
- Clock A/B: swap only the clock chain; observe skirt/floor changes.
- Network A/B: swap only balun/load; observe spur/IMD movement.
Clock budgeting math, JESD204B/C alignment procedures, and reconstruction/anti-image filter synthesis are handled in their dedicated pages. This section focuses on how those domains enter CS-DAC performance and how to validate their impact.
Outputs and front-end: differential current output meets the external network
A current-steering DAC does not “deliver voltage.” It delivers differential current, and the external network turns that current into the final voltage waveform seen by the system. In wideband and direct-RF designs, SFDR/IMD is often owned by the load, transformer/balun, and return paths as much as by the DAC core itself.
The current-output reality (why “paper specs” do not transfer)
- External impedance shapes distortion: any nonlinearity or imbalance in the output network becomes IMD/spurs.
- Voltage swing is created outside: the network sets the pin voltage swing and therefore how close the DAC operates to its limits.
- Symmetry is required: differential benefits (even-order cancellation) depend on matched impedance and a controlled common-mode path.
Compliance: the hidden cliff behind “sudden distortion”
Compliance limits how much pin voltage swing the current sources can tolerate while remaining linear. When the swing approaches the limit, distortion can degrade non-gradually: a small change in level, frequency, or load can trigger a visible IMD jump or introduce “unexpected” spur families.
- IMD3 jump beyond a certain output level (threshold behavior).
- Spur family growth that is strongly load/balun dependent.
- Even-order rise if imbalance and common-mode paths worsen during large swings.
- Network A/B: keep registers constant, swap balun/load; observe whether IMD/spurs move with the network.
- Level sweep: hold frequency constant, sweep amplitude; look for a repeatable “cliff.”
- Mode A/B: if available, compare RTZ/NRZ at the same level; note whether the cliff shifts.
Differential benefits (and the conditions required)
Differential current outputs can suppress even-order distortion and reduce sensitivity to external interference, but only when the external network preserves balance. “Equal length” is not enough; the system needs matched impedance and a controlled common-mode return path.
- Place balun/transformer close to the DAC pins to shrink the high-frequency loop area.
- Keep the differential loop shortest; avoid stubs and avoid asymmetrical breaks in the return plane.
- Preserve symmetry in routing, pads, and component placement (mirror where possible).
- Control the common-mode path so CM currents do not flow through sensitive reference/PDN regions.
Reconstruction and anti-image filter synthesis is handled in the dedicated filter page. This section states where the interface is sensitive and how to prove ownership with network A/B experiments.
RTZ vs NRZ: choose by band, mask, and spur tolerance
NRZ and RTZ are not “good vs bad.” They redistribute switching energy and change how artifacts appear in the spectrum. The practical decision should be driven by the target band, the spur/mask limits, and which artifact family dominates in measurements.
NRZ (default in many designs)
- Strength: efficient switching activity and common availability.
- Typical risk: images and some code-related spur families can be more visible in the band of interest.
- When it is enough: the mask is met across the band after output-network closure and symmetry control.
- Level sweep: look for repeatable spur growth or IMD thresholds.
- Network A/B: identify whether artifacts move with balun/load.
RTZ (use when the mask needs it)
- Potential benefit: can reduce visible image structure or shift even-order trends in some bands.
- Predictable cost: higher switching activity can raise sensitivity to PDN/return paths and increase power.
- When it is worth enabling: measurements show a switching/image-driven limitation and the mask is tight in the affected region.
- NRZ ↔ RTZ A/B: same tone plan and same output network; compare images, even-order, and spur families.
- Mask-driven decision: adopt RTZ only if improvement occurs inside the critical band windows.
Practical rule (band + mask + tolerance)
If the limiting artifact family belongs to switching/image structure and the mask is tight where it appears, evaluate RTZ early. If the limitation is dominated by clock skirts, output-network nonlinearity, or return-path coupling, stabilize those owners first and then re-evaluate RTZ/NRZ.
Spur and distortion root-cause map: from spectrum chaos to owned variables
“A spectrum full of spurs” becomes tractable when spur families are grouped by who modulates what. The goal is not to guess, but to identify a dominant owner with single-variable A/B experiments. The map below links each spur class to its observable fingerprints, the first places to inspect, and the fastest confirmation steps.
Code-related spurs (element mismatch / switching transient / major carry)
- Spurs change with level or code pattern (not just with frequency).
- “Hot regions” near major carry show localized IMD/spur growth.
- NRZ/RTZ switching can reshape the spur family (transient ownership).
- Major-carry region sensitivity (threshold behavior).
- Switching coupling paths and loop area near outputs.
- Mode-dependent artifacts (RTZ/NRZ).
- Level sweep at fixed frequency (look for a repeatable “cliff”).
- NRZ ↔ RTZ A/B with identical network and measurement settings.
- Change waveform/code pattern and check spur movement.
Clock-related artifacts (timing noise → skirts / image structure)
- Skirt around tones (close-in structure) changes with the clock chain.
- Artifacts worsen with higher output frequency (timing sensitivity).
- Clock swap changes floor/skirts even with an unchanged output network.
- Clock source, jitter cleaner, distribution, and isolation.
- Clock routing coupling into sensitive analog/return regions.
- Test chain phase-noise limitations (avoid blaming the DAC).
- Clock A/B: swap only the clock chain and compare skirts/floor.
- Sweep output frequency in-band and check trend strength.
- Hold everything else constant (RBW/window/averaging frozen).
Supply and return-path coupling (switching currents modulate bias/reference)
- Spurs correlate with digital activity or mode changes.
- Fixed-family spurs appear near known switching domains (PDN noise signature).
- Small layout/stack-up changes can shift results (return-path sensitivity).
- Switching current loops crossing reference/bias regions.
- Decoupling placement relative to the true HF current loop.
- Plane splits that force return detours (coupling amplifier).
- Supply A/B: external clean supply vs on-board supply.
- Activity A/B: change digital activity level and observe spur changes.
- Keep output network and measurement frozen while toggling one variable.
Layout imbalance (differential balance breaks → even-order rises)
- 2nd harmonic is elevated and sensitive to routing/network symmetry.
- IMD worsens in a way that tracks balance rather than noise floor.
- Balun/placement changes reshape even-order content noticeably.
- Impedance symmetry (pads, vias, stubs, component mirroring).
- Controlled common-mode path (avoid CM currents through sensitive planes).
- Balun proximity and symmetry from pins to the conversion point.
- Network A/B and observe 2nd movement.
- Compare 2nd/IMD change magnitude vs floor change magnitude.
- Preserve identical measurement settings for comparability.
Priority rule: isolate the owner before changing the board
Start with A/B tests that require no layout changes (clock, mode, network, supply), then perform a level sweep to detect thresholds (major carry or compliance), and only then invest in layout/return-path changes. This sequence prevents “multi-variable edits” that make the spectrum appear random.
Testing and bring-up: a repeatable spur-hunting closure loop
Bring-up converges when the test bench is stable and every experiment changes one variable at a time. The objective is to make spurs either move predictably (revealing ownership) or stay invariant (excluding a suspected owner). Freeze measurement settings first, then run structured A/B experiments.
Minimum viable bench (what must be stable)
- Clock path: clock source + (optional) jitter cleaner + distribution with a controlled return.
- Output path: balun/transformer + attenuation + DC block (as needed) to protect and linearize the measurement chain.
- Spectrum measurement: analyzer settings must be repeatable (span, RBW, averaging, reference level).
Coherent capture and windowing (keep it comparably “fair”)
When the tone aligns to the analysis bins, leakage does not masquerade as spurs. When it does not align, a window can control leakage, but comparisons remain valid only if the window and settings stay fixed. The purpose here is repeatability, not theory depth.
Spur hunting SOP (single-variable closure)
- Fix output frequency, level, and waveform.
- Freeze analyzer settings (span/RBW/window/averaging).
- Lock the output network (balun/atten/DC block).
- Clock A/B: swap only the clock chain and re-measure.
- Mode A/B: NRZ ↔ RTZ with identical bench and network.
- Network A/B: swap balun/load/atten (one change).
- Supply A/B: external clean supply vs on-board supply (one change).
- If spurs move with clock A/B: clock ownership is dominant (skirts/floor shift).
- If 2nd/IMD moves with network A/B: balance/network ownership is dominant.
- If artifacts show a repeatable level threshold: compliance/major-carry involvement is likely.
Dynamic performance & code-dependent spurs (SFDR/THD)
Separate the metrics before blaming the core
- THD is dominated by harmonic generation (nonlinearity mapping).
- SFDR is dominated by the single largest spur (harmonic or non-harmonic).
- Code-dependent spurs are often created when a repeated code sequence modulates small static errors into discrete tones.
Key reading rule
A worse SFDR does not automatically mean “more nonlinearity.” It may be a sequence-bound spur that a different code pattern would move or remove.
Common spur attribution paths (and what they imply)
Repeated code pattern
Periodic sequences act like a modulator that makes element mismatch and gradients visible as discrete tones. If the spur follows the sequence, the pattern is the lever.
Boundary mapping hotspot
Segmentation boundaries can re-map static errors into specific code bands. Repeated visits to boundary-adjacent codes can produce “structural” spurs.
Output-chain nonlinearity
Driver and load nonlinearities can amplify small code-dependent errors into harmonics or IMD. If distortion changes strongly with load or swing, the chain is the lever.
Minimal isolation experiment set (change one variable at a time)
- Change code pattern (same amplitude): keep the same output swing while changing the sequence order and periodicity. Watch whether spurs move or vanish.
- Change update rate / sampling rate: check whether the spur follows the update process (location scales with fs or its artifacts).
- Change clock cleanliness: adjust jitter/PLL/clock source and observe whether the floor or specific tones respond.
- Change load / driver configuration: observe whether harmonics or IMD change disproportionately with load or swing.
A reliable conclusion requires a controlled comparison. If code pattern and clock are changed together, the attribution becomes invalid.
Quick decision rules (pattern-bound vs clock-bound vs chain-bound)
Pattern-bound spur
The spur changes when the sequence periodicity or ordering changes at the same amplitude. Boundary-adjacent activity can be a dominant contributor.
Clock-bound issue
The floor or tones respond strongly to clock quality or PLL configuration. If jitter dominates, the floor typically shifts with clock changes.
Chain-bound distortion
Harmonics/IMD change strongly with load, swing, or driver selection. The same core can look dramatically different under different output chains.
Note on update shaping (kept intentionally brief)
Some DAC families offer update shaping options that alter spectral distribution. System-level RTZ/NRZ trade-offs belong to the current-steering / RF DAC deep dive and are not expanded here.
Diagram focus: isolate spurs by changing one lever at a time—sequence, then clock, then load/driver—until the spur clearly binds to a root cause.
Engineering checklist (bring-up, verification, production test)
Golden rule: if conditions are not comparable, results are meaningless
Record and lock: output configuration, load, bandwidth, window/threshold definitions, code pattern, and temperature state. Only then can data be compared across builds or devices.
Bring-up (establish a clean baseline first)
- Reference stability: confirm reference noise and return integrity before measuring linearity or FFT.
- Supply noise: verify analog/digital partitioning and decoupling effectiveness under update activity.
- Return paths: ensure fast digital return currents do not cross output/reference nodes.
INL/DNL (sweep strategy and repeatability)
- Sweep coverage: include full sweeps plus mandatory boundary-adjacent code coverage.
- Integration time: keep integration consistent across codes to avoid mixing noise with linearity.
- Thermal state: separate warm-up drift from static shape by controlling temperature and time.
- Repeatability: run multiple passes and confirm whether the INL “shape” is stable and reproducible.
Glitch impulse (make the measurement comparable)
Lock the condition fields
- Trigger definition
- Bandwidth limit
- Probe ground method
- Integration window
- Code-pattern set (boundary + MSB steps + extremes)
Interpretation habit
Report both typical and worst-case values, and always identify which code zone produced the worst case. Do not rely on averages to represent boundary behavior.
Large-step verification (overshoot and settling criteria)
- Key step set: boundary crossings, MSB-step patterns, and extremes transitions.
- Overshoot criterion: check whether ringing crosses the defined error band and for how long.
- Settling criterion: verify enter-and-stay behavior to 0.5 LSB / 1 LSB / ppm under the documented condition set.
Dynamic FFT (tone choice and spur identification)
- Tone selection: avoid accidental periodicity that can create misleading sequence-bound spurs.
- Windowing consistency: keep window and record length consistent for comparisons.
- Spur isolation: apply the H2-9 flow (pattern → clock → load/driver) before concluding root cause.
Production strategy (risk-based: must-test vs sample-test)
Must-test
Baseline bring-up health, boundary-adjacent worst-case steps, and any metric that historically fails in hot zones or under load sensitivity.
Sample-test
Stable shape metrics that show strong repeatability under controlled conditions, and secondary FFT checks once the root cause levers are verified.
Diagram focus: a repeatable test bench is defined by locked conditions and a structural worst-case subset (boundary, large steps, extremes), not by one-off “good-looking” plots.
IC selection logic: must-ask fields → risk gates → RFQ template
Current-steering DAC selection fails most often because suppliers reply with a single “typical” point while the system requires band-limited curves, mode constraints, and output compliance boundaries. This section turns selection into a procurement-ready process: ask for the right fields, map missing fields to hard risks, and force responses into a structured table.
Must-ask fields (CS-DAC specific)
- fs: supported range and constraints (internal PLL or external clock dependency).
- SFDR vs fout curve across the target band (not a single typical value).
- IMD3 vs fout curve (two-tone spacing stated) across the target band.
- Curves must include conditions: clock plan, mode, interpolation/DUC (if any), output chain, temperature, backoff.
- IOUTFS: programmable range and step size.
- Compliance: allowed output voltage range per pin and allowed common-mode range.
- Failure behavior: how distortion/spurs change when compliance is exceeded (curve or note).
- Output interface options: any matched output assumptions (if applicable) that impact the external network.
- Supported modes: NRZ, RTZ, mixed/2×NRZ (if offered).
- Mode constraints: which modes require specific fs ranges, interpolation, or PLL settings.
- Mode side-effects: power/thermal and noise-floor impact (field + condition, no marketing text).
- Channel count and per-channel output structure.
- Sync/trigger fields: deterministic latency, multi-device sync support, trigger input availability (capability statements).
- Interface fields: JESD204B/C lane count, max lane rate, subclass support (capability fields only).
- Package, thermal resistance, and power by mode/fs (not one number).
- Supply domains (analog/digital/PLL) and typical currents by domain.
- Reference/bias: external vs internal reference, bias/CM pins, required external components (fields).
- Built-in tones/BIST or any internal stimulus features (field + conditions).
- Register observability: PLL lock, alarms, temperature/health status (what can be read).
- Evaluation assets: availability of official EVM/reference design (yes/no + link requested in RFQ).
Risk mapping: missing fields that are hard to rescue later
- No SFDR/IMD3 vs fout curves in the target band with clear conditions.
- No clear compliance/common-mode boundaries and failure behavior.
- Mode support exists, but constraints are undefined (NRZ/RTZ/mixed limitations unclear).
- Sync/trigger capability is vague (multi-channel or multi-device timing uncertainty).
- Thermal/supply-domain currents are missing (board-to-board variation likely).
- Reference/bias requirements are unclear (bias modulation spurs become likely).
- Output network optimization and layout symmetry tuning (requires frozen bench records).
- Mode trade-offs (RTZ/NRZ) if the supplier provides clear constraints and curves.
Candidate part numbers to include in RFQs (examples)
The list below provides concrete targets for RFQs and cross-vendor comparisons. Final selection depends on band/mask, mode constraints, and compliance margins.
- Analog Devices: AD9166, AD9172, AD9174, AD9162, AD9163, AD9164
- Texas Instruments: DAC38RF82, DAC38RF89
- Maxim / ADI legacy families (for comparisons): MAX5857, MAX5868
- Texas Instruments: DAC39J84, DAC38J84, DAC37J82, DAC38J82
- Reference/legacy current-steering example: DAC5672 (for field-comparison discipline)
RFQ template (force curve + condition + acceptance gates)
Copy and send this template. Suppliers should respond by filling each row and attaching the requested evidence (plots, tables, or screenshots). If a field cannot be provided, the risk gate column must be acknowledged.
- Target band: ___ to ___ (Hz/GHz) ; mask limit: spurs < ___ dBc (in-band) ; adjacent: ___
- Clock plan: external / internal PLL ; fclk range: ___ ; jitter-cleaner: yes/no
- Output chain assumption: balun ___ ; Zload ___ ; atten ___ ; DC block yes/no
- Measurement rules: span ___ ; RBW ___ ; window ___ ; averaging ___ ; temperature ___
| Requirement | Vendor must provide (evidence) | Test conditions (explicit) | Acceptance gate | If missing → risk |
|---|---|---|---|---|
| Band-limited SFDR vs fout | Plot or data table across the target band + screenshot allowed | fclk, mode, interpolation/DUC status, output chain, RBW/window/avg, temperature, backoff | In-band spurs < ___ dBc for ___ to ___ band | RED (cannot compare or sign off) |
| Band-limited IMD3 vs fout (two-tone) | IMD3 plot/table + tone spacing stated | Same as SFDR row + two-tone spacing and per-tone level/backoff | IMD3 < ___ dBc within band under stated spacing | RED |
| Compliance and common-mode boundaries | Limits per pin + recommended operating region + any distortion cliff notes/plots | Stated output chain and load assumptions (Zload, balun model, coupling) | Compliance margin > ___ across worst-case load | RED (late-stage rescue unlikely) |
| IOUTFS range and programming | Range, step size, accuracy notes, recommended settings for target band | Specify the intended load and backoff used to claim performance | IOUTFS supports required output swing with margin | GREEN/YELLOW (system-dependent) |
| NRZ/RTZ/mixed modes and constraints | Supported modes + constraints by fs/fout + power impact fields | Curves must be tied to a mode and a clock plan | Mode usable in target band under stated constraints | RED if constraints unknown |
| Channels and sync capability (fields) | Channel count + capability statement for sync/trigger + JESD fields (lanes/rates/subclass) | System-level sync requirement stated (phase/amplitude window) | Must meet timing/coherence requirement (capability match) | YELLOW (schedule risk) |
| Package/thermal and supply domains | Thermal numbers + power by mode/fs + supply rails and typical currents | State ambient/board temperature targets and airflow assumptions | Thermal margin and rail margin across worst-case mode | YELLOW |
| Production test hooks & observability | Built-in tone/BIST fields + readable status registers + official EVM/reference design availability | Define required factory metrics (SFDR/IMD spots + record template) | Must support repeatable production screening | YELLOW (scale-up risk) |
Responses that do not provide band-limited curves with explicit conditions should be treated as non-comparable. A single “typical SFDR” number is not a valid response for mask-driven CS-DAC systems.
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FAQ: Current-Steering DAC (CS-DAC)
Short answers only. Each item is structured as: Symptom → Likely cause → One check → Next step, to prevent the main content from expanding sideways.
