123 Main Street, New York, NY 10001

Submit Your BOM

SpO₂ PPG Front-End (LED Drivers & Photodiode TIAs)

SpO₂ PPG Front-End (LED Drivers & Photodiode TIAs)

← Back to: Medical Imaging & Patient Monitoring

A reliable SpO₂ PPG front end is built by controlling timed LED slots, keeping the PD-TIA + ADC linear with enough headroom, and using LED-OFF ambient sampling plus clear quality flags so motion and lighting changes can be detected and gated instead of silently corrupting data.

This page shows how to design, validate, and debug that chain—from LED current integrity and saturation recovery to ambient subtraction, ADC timing, low-power partitioning, and production self-test—without drifting into system-level topics.

H2-1 · What this page covers (Scope + quick answer)

A SpO₂ PPG front end turns time-slot LED currents into synchronized photodiode samples that remain usable under ambient light and motion. It combines accurate LED pulses, PD-TIA dynamic range and fast saturation recovery, ambient blanking/subtraction windows, and ADC timing alignment, plus low-power MCU hooks for filtering, quality flags, and self-test diagnostics.

What this page gives you

  • Architecture map of LED timing → optical path → PD-TIA → ADC → MCU outputs, including where to place ambient blanking windows.
  • Engineering targets for LED current integrity, PD-TIA noise/dynamic range, saturation recovery, and ADC sampling alignment.
  • Practical debug flow (symptom → likely cause → first measurement) plus a validation checklist for bench and phantom tests.
Outcome 1: Selection checklist
LED driver type, compliance headroom, slot timing, TIA gain options, ADC choice, and power partition.
Outcome 2: Failure modes → symptoms
Saturation, flicker ripple, mistimed sampling, baseline wander, motion spikes, and channel crosstalk.
Outcome 3: Validation steps
Slot waveform capture, TIA noise floor, ambient subtraction check, ADC alignment, and diagnostic flags.

Scope Guard (for non-overlap)

Allowed (this page may go deep)
PPG slots, LED current pulses, photodiode current, PD-TIA noise/dynamic range, ambient blanking/subtraction, ADC sampling alignment, low-power MCU hooks, self-test & validation.
Banned (links only, no deep content)
ECG chain details, NIBP/IBP, capnography, telemetry/gateway protocols, system isolation PSU deep dive, full EMC compliance deep dive, and imaging chains (X-ray/CT/MRI/US/OCT).
PPG front-end boundary map for SpO2 (LED timing to synchronized samples) Block diagram showing LED driver and slot timing, optical path to photodiode, PD-TIA and ADC sampling alignment, MCU hooks, and outputs including raw PPG samples, ambient samples, and diagnostic flags. SpO₂ PPG Front-End Scope: Timing → Optics → PD-TIA → ADC → MCU Outputs LED Driver Current Pulse I_LED(t), peak & edge Slot Timing Red / IR / LED-off Settle → Sample window LED slots (labels kept minimal) Optical Path LEDs Red IR Off Tissue Absorb + scatter PD I_PD(t) Analog + Sampling PD-TIA Gain / noise / recovery ADC Aligned samples Low-Power MCU Hooks Outputs (what downstream algorithms actually need) Raw PPG Samples Red / IR codes + timestamps Ambient Samples LED-off window for subtraction Diagnostics Flags Saturation / outliers / SQI Boundary rule: this page ends at synchronized samples + front-end diagnostics (system security / gateway / isolation PSU are out of scope).
Figure F1 — Boundary map for SpO₂ PPG front ends: where timing, analog integrity, and sampled outputs must be nailed down.

H2-2 · PPG signal chain: from photons to samples

A PPG front end succeeds when time-slot LED pulses produce repeatable photodiode currents that can be converted into aligned ADC samples without wasting headroom on DC/ambient or collapsing under motion. This chapter defines the signal components, the block interfaces, and the four key “budgets” that keep the chain stable.

Signal components (what rides on I_PD)
  • DC: tissue + probe coupling + ambient offset (consumes headroom).
  • AC (target): pulsatile component (small amplitude, needs low noise).
  • Ambient flicker: 100/120 Hz and harmonics (creates low-freq ripple).
  • Motion artifact: coupling/pressure changes (can dwarf AC and saturate).
Block interfaces (what must be defined)
  • LED driver output: I_LED(t) (peak, pulse width, edges, compliance).
  • Photodiode output: I_PD(t) (DC + AC + interference).
  • TIA output: V_TIA(t) (gain, bandwidth, saturation recovery).
  • ADC output: codes + timestamp (sample phase alignment).
  • MCU output: PPG stream + flags (ambient, saturation, SQI).

Segmented chain table (inputs, targets, failures, first checks)

Block Input → Output Key targets Common failures Symptoms First check
LED driver Current setpoint → I_LED(t) Peak current accuracy, pulse repeatability, edge control, enough compliance headroom Droop from headroom limit, overshoot/ringing, channel crosstalk, thermal derating surprises PPG amplitude drift, slot-to-slot mismatch, unexpected ripple coupled into TIA Sense resistor waveform + compliance margin at peak current
Slot timing Schedule → sample strobe Settling window, sample window alignment, LED-off ambient window, deterministic latency Sampling too early (settling), no LED-off ambient capture, jittery strobe Baseline wander, alternating slot artifacts, unstable subtraction results Timing GPIO vs ADC sample instant (logic analyzer / scope)
Photodiode Optical flux → I_PD(t) Low leakage, stable capacitance, predictable response under ambient Excess capacitance limits bandwidth/settling, unexpected dark current offsets Slow recovery after bright ambient, extra noise, reduced usable gain PD node settling / step response with controlled light stimulus
PD-TIA I_PD(t) → V_TIA(t) Input-referred noise, stable gain, enough output swing, fast saturation recovery Saturation from DC/ambient, recovery too slow, instability from PD capacitance Flat-topped waveforms, long baseline “stuck” after motion/bright light, oscillation V_TIA headroom + recovery time after step; noise floor with LED off
ADC V_TIA(t) → codes Enough ENOB in-band, no clipping, repeatable sampling instant, manageable latency Aliasing of flicker/motion, mistimed sample point, quantization dominates Flicker ripple, inconsistent Red/IR ratio, noisy AC extraction Capture raw codes vs slot phase; verify anti-alias/filter settings
MCU hooks codes → streams + flags Low-power scheduling, subtraction path, basic filtering, quality flags (SQI), self-test counters Wrong subtraction order, overflow/clamp mistakes, missed sleep windows, no diagnostics “Good looking” but wrong ratio, intermittent dropouts, hard-to-debug field failures Log slot means, ambient, saturation counts; confirm duty-cycle schedule

The four budgets (keep these explicit during design reviews)

1) Dynamic range budget
  • Worst-case DC + ambient must not force TIA/ADC clipping.
  • Leave margin for motion spikes and skin-tone variability.
  • Prefer ways to keep DC from consuming ADC codes (architecture-specific).
2) Noise budget
  • Shot noise rises with optical current; TIA noise is constant-like.
  • Ensure in-band noise floor stays below AC extraction needs.
  • Do not “solve” noise purely with higher ADC bits if analog is unstable.
3) Bandwidth & sampling budget
  • Cover heart-rate band plus motion/settling behavior that leaks into samples.
  • Guard against lighting flicker and aliasing with explicit anti-alias assumptions.
  • Choose slot rate and filter windows so subtraction remains stable.
4) Timing alignment budget
  • Sampling must land after LED/TIA settling, not during edges.
  • Keep strobe jitter small relative to the sample window.
  • Ambient window must represent the same optical conditions (except LED).
PPG components and noise budget blocks (from I_PD to filtered samples) Diagram showing DC, AC, ambient flicker and motion artifact combining into photodiode current, converted by PD-TIA and ADC, with callouts for shot noise, TIA noise and ADC noise, and a final digital filtering and quality-flag block. Signal Components + Budgets: DC/AC/Ambient/Motion → Samples What combines at I_PD(t) DC offset AC (pulsatile) Ambient flicker Motion artifact Conversion path Photodiode I_PD(t) at node PD-TIA V_TIA(t) headroom ADC aligned sample Noise contributors Shot noise rises with current TIA noise gain & stability ADC noise ENOB in-band After sampling: subtraction + filtering + quality flags Ambient subtract LED-on minus LED-off Band-limited filtering anti-alias assumptions Quality flags (SQI) sat / outlier / dropouts Budgets to keep explicit: Dynamic range Noise Bandwidth Timing
Figure F2 — DC/AC/ambient/motion combine at the photodiode; the front end must protect dynamic range, noise floor, bandwidth, and timing alignment before any downstream computation.

H2-3 · Optical modulation plan (Red/IR slots & duty cycle)

Slot planning is the front end’s “contract” with downstream processing: samples must be taken after settling, inside a repeatable window, and with a matching LED-off ambient reference. Good slot discipline improves usable SNR and reduces saturation recovery events more reliably than simply increasing ADC resolution.

What a slot plan must guarantee
  • Stable sampling instant: avoid LED edges and analog recovery regions.
  • Paired reference: include an LED-off ambient sample under near-identical conditions.
  • Repeatability: same ordering and timing every cycle (deterministic latency).
  • Power realism: peak current and duty cycle must fit thermal and battery limits.
Slot order and width (design logic)
  1. Pick a sample window (where codes are trusted).
  2. Allocate settling time before that window (LED + PD-TIA).
  3. Set slot width ≥ settling + sample + margin.
  4. Insert LED-off ambient after a safe turn-off delay.

Minimal timeline example (one cycle)

  • Red ON → wait for settling → take Red sample in the stable region.
  • Red OFF → short guard delay → take Ambient sample (LED-off reference).
  • IR ON → wait for settling → take IR sample in the stable region.
  • Optional: another LED-off ambient sample if ambient flicker is strong or slot rate is low.
Hard rules (do not compromise)
  • Sample only in the stable plateau (not near edges).
  • Red and IR samples must use consistent relative timing inside their ON slots.
  • Ambient samples must be taken in a true LED-off window (after turn-off transients).
Soft rules (optimize based on constraints)
  • Use higher peak + lower duty only if headroom, EMI, and thermal limits remain controlled.
  • Keep slot rate compatible with MCU sleep windows and ADC buffering (avoid constant wakeups).

Duty cycle and power (front-end viewpoint)

  • Average power tracks peak current and duty cycle; peak current improves SNR but stresses headroom and EMI.
  • Dark skin / low perfusion / probe geometry often pushes either peak current, gain, or sampling strategy—keep changes within the slot discipline.
  • If saturation or recovery dominates, adjust timing and headroom first (sample later, add guard time, reduce peak, or change gain strategy).

Common slot mistakes (failure → symptom → first check)

Failure Typical symptom First check
Sampling too early (insufficient settling) Alternating slot artifacts; unstable amplitude cycle-to-cycle Move the sample point later; verify immediate stability improvement
Missing/incorrect LED-off ambient window Flicker ripple (100/120 Hz) and drift with room lighting changes Force strong ambient; compare “subtract vs no subtract” behavior
Slots too tight (recovery/crosstalk between slots) Red/IR bias shifts; baseline “stuck” after bright ambient or motion Add guard time or reduce peak; watch if bias shift disappears
Timing slots with ambient blanking (Red, LED-off ambient, IR) Timeline showing Red and IR LED pulses, settling and sample windows, and an LED-off ambient sample window, plus a small rules-of-thumb box for sampling discipline. Slot Timing Template: settle → sample (Red / Ambient / IR) One cycle (not to scale) RED ON settle sample LED OFF ambient sample IR ON settle sample time → What the windows protect • Settling window: avoids edge coupling and analog recovery • Sample window: aligned codes for Red/IR under repeatable conditions • Ambient window: LED-off reference for subtraction and flicker suppression Rules of thumb 1) Sample away from edges 2) Always capture LED-off 3) Keep timing deterministic The exact widths depend on driver edges, PD-TIA settling, and ADC sampling alignment; the structure should remain consistent.
Figure F3 — A disciplined slot template: sample on the plateau and always reserve an LED-off ambient reference window.

H2-4 · LED driver architecture & current integrity

In a PPG front end, the LED driver is not “just a light source.” It is a precision pulse generator whose headroom, edges, and diagnostics directly determine whether Red/IR samples remain comparable across cycles and across operating conditions.

Topology options (common in PPG)
  • Linear current sink/source: simple, low switching noise, but burns headroom.
  • Switching current regulator: better efficiency and headroom flexibility, higher layout/EMI care.
  • Multi-channel programmable current: matched Red/IR amplitude control and per-slot adjust.
  • Edge control features: controlled rise/fall to protect sampling windows.
Compliance headroom (why it matters)
  • Headroom shortfall causes pulse droop or missed peak current, biasing Red/IR samples.
  • Headroom varies with LED Vf, series resistance, battery, and temperature—repeatability must be defended.
  • If headroom is tight, fix it with supply/driver choices or slot strategy before “adding ADC bits.”

Headroom checklist (peak pulse condition)

  • LED string forward voltage at temperature + aging margin.
  • Driver drop (linear element or switch path) at peak current.
  • Sense resistor drop and any protection element drop in series.
  • Trace/connector resistance under pulse current (including return path).
  • Supply sag during pulses and across duty cycling.

Edge control (sampling protection)

  • Very fast edges can inject noise into the analog ground/reference, contaminating near-edge samples.
  • Very slow edges shrink the usable plateau and increase required settling time, forcing longer slots.
  • Design goal: controlled edges + sample away from edges with minimal loop area.

Crosstalk paths (why slots “bleed”)

  • Power/ground coupling: pulse current di/dt modulates analog ground or reference.
  • Optical leakage: stray reflections add an untracked offset (front-end must flag instability).
  • Timing overlap: insufficient guard time leaves recovery tails that bias the next slot.

Protections & diagnostics (must map to data validity)

  • LED open/short detect: if triggered, mark samples invalid (avoid “fake low” readings).
  • Thermal derating: if current is reduced, the system must treat calibration state as changed for that interval.
  • Current readback (debug/production): verify I_LED(t) is achieved per slot; log droop events as diagnostics.

Linear vs switching LED current drivers (PPG-centric tradeoffs)

Dimension Linear current sink/source Switching current regulator
Efficiency Lower; burns headroom during pulses Higher; better for battery-heavy use
Noise coupling risk Lower switching content; still edge/ground risks Higher; requires careful layout and filtering
Compliance flexibility Limited by supply; headroom cost is explicit Good; can maintain current over wider conditions
Layout complexity Simpler; fewer power components More complex; switch loop control is critical
Diagnostics friendliness Easy current sense; clear headroom limits Good if designed in; must separate sense from switching noise
Sampling risk Usually lower; easiest to keep sampling windows clean Can be higher; requires stronger timing discipline and edge/EMI control
LED driver options comparison: linear vs switching with shared control and diagnostics Two-column block diagram comparing a linear current sink and a switching current regulator driving LEDs, with a shared bottom block for slot timing, setpoint control, current readback, fault flags and thermal derating. LED Driver Architectures: Current Integrity + Readback Linear current sink Switching current regulator Supply Linear element headroom loss Sense LEDs Red / IR pulses I_LED(t) Strength: simpler layout and cleaner sampling windows Risk: efficiency loss and compliance limits at peak current Supply Switch stage loop + PWM L / C LEDs Red / IR pulses I_LED(t) Strength: better efficiency and headroom control across conditions Risk: switch loop/EMI can contaminate near-edge sampling if unmanaged Shared control & diagnostics (must exist in both options) Slot timing deterministic pulses Setpoint peak & duty Readback sense & droop Fault flags open/short/thermal Sampling protection: control edges, minimize pulse loop area, and keep sampling windows away from switching/edge disturbances.
Figure F4 — Compare linear and switching drivers using the same yardsticks: headroom, edge control, readback, and data-validity diagnostics.

H2-5 · Photodiode + TIA design (noise, bandwidth, saturation)

The PD-TIA stage must keep the signal path linear under strong ambient light while still extracting a small AC pulse component. A practical design balances PD capacitance, TIA feedback (Rf/Cf), and output headroom, then adds a DC cancellation method so ADC codes are not wasted on background DC.

Photodiode (PD) selection knobs: what changes, and what breaks

PD parameter Primary impact Typical symptom if pushed too far First mitigation
Area Signal current ↑, but junction C often ↑ TIA stability becomes harder; more ringing/settling time Reduce parasitics, tune Cf, keep slot sample away from edges
Capacitance (Cpd) Bandwidth and phase margin pressure Must add large Cf → AC pulse looks “rounded” Lower Rf, adjust Cf, shorten PD node trace, guard ring if needed
Dark current / leakage DC offset and low-frequency noise floor Baseline drift; “fake low” amplitude under warm conditions DC cancellation (servo/offset) and leakage-aware layout
Connection parasitics Extra C and coupling into the summing node Sensitivity to motion/EMI; unstable or noisy baseline Short node, shield/guard, controlled return path

TIA design order (prevents “big Rf, then panic”)

  1. Set output headroom: reserve linear swing margin for the worst ambient + LED reflections.
  2. Estimate worst DC photocurrent: strong room lighting and direct flashlight scenarios matter for saturation.
  3. Choose Rf upper bound: ensure DC does not push the output into clipping during LED-on or LED-off windows.
  4. Stabilize with Cf: target a clean settle-then-sample response inside the slot budget (avoid long tails).
  5. Validate bias/leakage: input bias and leakage must not dominate low-frequency behavior after DC cancellation.

Noise budget (practical view: who dominates, and when)

Noise contributor Dominates when Most effective lever (front-end)
Shot noise (photocurrent) Ambient is strong; DC photocurrent is large Improve blanking/subtraction, reduce unwanted light, manage headroom
Rf thermal noise Rf is very large to chase AC amplitude Use code-range wisely (DC cancel), optimize Rf/Cf, avoid over-amplifying DC
Amplifier input noise Cpd is high; stability requires heavy compensation Lower Cpd/parasitics, tune Cf, keep bandwidth aligned to slot needs
ADC / reference noise Analog path is clean; quantization/reference become visible Keep sampling windows clean; avoid wasting codes on DC; verify reference integrity

Saturation and recovery (the hidden cause of slot-to-slot corruption)

  • Clipping risk: worst-case ambient can drive the TIA output into rail limits; AC becomes unrecoverable during that interval.
  • Recovery time: even brief saturation can produce a long tail; the next slot’s sample window may be biased.
  • Engineering rule: recovery must complete before the planned settling window ends; otherwise timing or headroom must change.

DC removal strategies (front-end options to protect ADC code range)

DC removal is about keeping ADC dynamic range focused on the AC pulse component while preserving slot repeatability.
  • Analog high-pass / AC coupling: simple DC reduction; verify low-frequency behavior and baseline stability.
  • DC servo loop: slow integrator cancels DC at the summing node; must be “slow enough” not to eat the pulse component.
  • Programmable offset injection (DAC/trim): controllable centering under varying ambient; watch injected noise/coupling.

Quick check list (bring-up / review)

  • TIA bandwidth supports settle-then-sample within the slot (not “as wide as possible”).
  • Saturation margin remains under worst ambient + maximum LED reflections (include temperature margins).
  • Recovery time is shorter than the planned settling window; no long tail into the next slot.
  • DC cancellation is stable and slow enough; does not distort the target AC pulse component.
  • ADC code usage is centered and efficient; DC does not consume most of full-scale.
PD-TIA with DC cancellation loop and saturation risk Block diagram showing photodiode into a TIA with Rf/Cf, feeding an ADC. A DC servo / offset cancellation loop returns from the output to the summing node to remove DC and protect ADC code range, with a saturation risk marker. PD → TIA → ADC with DC Cancellation (Protect Code Range) PD Iphoto (DC + AC) Cpd / leakage sum TIA Amplifier input noise Rf Cf feedback saturation risk ADC codes (slot samples) full-scale must be used DC cancellation (slow) DC servo integrator Offset DAC / trim Goal center output inject cancel Design focus: keep linear headroom under ambient, then remove DC slowly so ADC codes track the AC pulse component.
Figure F5 — PD-TIA with a slow DC cancellation path that protects ADC code range and reduces saturation-driven recovery tails.

H2-6 · Ambient light rejection: blanking, subtraction, synchronous detection

Ambient rejection is a timing-and-data-path problem. A robust front end pairs each LED-on sample with a correctly timed LED-off ambient sample, subtracts them per slot, and adds guards for saturation and outliers. When flicker is strong, sampling cadence and filtering budgets must be checked so residual ripple stays controllable.

Ambient components (what must be removed)

  • Ambient DC: pushes the TIA/ADC toward saturation and wastes code range.
  • Flicker AC (often 100/120 Hz + harmonics): appears as ripple that can leak through imperfect subtraction.
  • Fast changes (motion, sudden light shifts): create outliers and transient clipping that must be flagged.

Sample-and-subtract method (slot-by-slot, actionable steps)

  1. LED ON sample: take the code in the stable plateau (away from LED edges and recovery tails).
  2. LED OFF ambient sample: capture a true LED-off reference after turn-off transients have settled.
  3. Subtract: compute (ON − OFF) per slot under the same gain and signal chain conditions.
  4. Guard: clamp/flag outliers and clipping events; avoid feeding corrupted samples downstream.
  5. Filter: apply a budgeted low-frequency suppression stage so residual flicker stays below the noise floor.

Flicker budget checks (prevents “subtraction still ripples”)

  • Timing alignment: ON and OFF samples must be close enough that ambient does not change drastically between them.
  • Cadence vs 100/120 Hz: ensure the sampling cadence and slot ordering do not amplify alias-like residuals.
  • Residual metric: track post-subtraction “ambient residual” to detect lighting changes or bad windows.
  • Saturation flags: treat saturation as invalid data, not as something filtering can fix later.

Synchronous detection (correlated sampling): when it helps, and what it demands

  • Benefit: extracts the modulated LED component more selectively under strong ambient/flicker conditions.
  • Demand: stricter timing determinism; jitter and phase drift can convert directly into amplitude error.
  • Boundary: keep the description at the front-end interface level (timing sensitivity), not full algorithm detail.
Ambient subtraction data path: ON sample, OFF sample, subtract, guard, filter Diagram showing LED ON sample and LED OFF ambient sample feeding a subtractor, then an outlier/clamp guard stage and a filter stage, with a flicker source block (100/120 Hz) affecting the ambient path and a residual metric output for diagnostics. Ambient Rejection Path: sample → subtract → guard → filter LED ON sample plateau window code_on LED OFF ambient true LED-off window code_off Flicker source 100/120 Hz + harmonics Subtract on − off ppg_raw Guard clamp / outlier ppg_guarded Filter budgeted LF suppression ppg_clean Residual diagnostic metric ambient_resid Key requirement: LED-off sampling must avoid turn-off transients; otherwise subtraction injects artifacts instead of removing them.
Figure F6 — A practical ambient rejection path: pair ON/OFF samples per slot, subtract, guard outliers/clipping, then apply a budgeted filter.

H2-7 · ADC choice & sampling timing (ENOB vs bandwidth vs jitter)

For slot-based PPG, the most valuable property is often repeatable sampling alignment (ON/OFF windows and settle-then-sample), not headline resolution. ADC choice should be made with timing determinism, effective bandwidth, and latency / group delay in mind, so subtraction and quality flags remain consistent across slots.

SAR vs ΣΔ for PPG (slot-friendly differences)

ADC family Why it fits PPG What must be watched Typical “gotcha” symptom
SAR Clear sampling instant; easy hardware trigger; low latency for per-slot decisions. Reference integrity, sampling transients, and keeping the sample point inside the plateau window. ON/OFF subtraction drifts when samples are taken too close to edges or recovery tails.
ΣΔ Strong in-band noise shaping for certain bandwidths; can look excellent in resolution metrics. Group delay / filter latency, effective bandwidth limits, and how “output rate” maps to slot processing. Slot boundaries blur: the output behaves “smeared” across time, complicating tight per-slot alignment.

Sampling rate and bandwidth budgeting (PPG-only view)

  • Physiologic band: ensure enough bandwidth to preserve pulse shape changes that are used as a quality proxy.
  • Motion / artifact band: do not over-constrain bandwidth so artifacts masquerade as “clean” but unusable data.
  • Flicker residual: slot cadence and ON/OFF spacing must keep 100/120 Hz residual controllable after subtraction and filtering.
  • Practical rule: define slot timing first (settle → sample → off-sample), then map to ADC output cadence (per-slot samples or short bursts).

Timing jitter: what it damages and how to harden the chain

Jitter turns into amplitude error when sampling occurs on steep edges or unsettled tails. The simplest mitigation is to place the sampling instant in the plateau window and keep triggering hardware-timed.
  • Prefer hardware trigger (timer → ADC trigger) over pure ISR “software sampling”.
  • Use DMA to move samples; reduce CPU active time and reduce timing variability.
  • Unify the timebase: slot timing, LED drive, and ADC trigger should share the same clock domain where possible.
  • Budget it: treat jitter and latency as reviewable items (jitter budget, latency budget), not as afterthoughts.

Decision tree (PPG slot system → ADC family → cadence hints)

  1. Is the design slot-based with ON/OFF subtraction?
    Yes → prioritize deterministic sampling instant and low latency → SAR is typically easier.
    No (continuous stream) → ΣΔ can be considered, but group delay and effective bandwidth must be checked.
  2. Do per-slot decisions need to react quickly? (quality flags, saturation handling, adaptive gain)
    Yes → keep conversion + delivery latency short; avoid long digital filter delays in the critical loop.
    No → more latency is acceptable; focus on stable cadence and consistent ON/OFF alignment.
  3. Is correlated sampling / synchronous extraction planned?
    Yes → jitter budget tight; timing must be hardware-driven and phase-consistent across slots.
    No → still keep sample points away from edges; subtraction quality dominates outcomes.
  4. Cadence hint: decide how many samples per slot (1-point plateau sample vs short multi-point average), then map to an effective output rate and a minimal filter budget.
ADC timing alignment for slot-based PPG sampling Block diagram showing MCU timer generating slot timing for the LED driver and ADC trigger. The sampling instant is placed inside a plateau window. Small budget boxes indicate jitter and latency constraints. Timing Alignment: Slot Timing → ADC Trigger → Sampling Instant MCU / Timer slot scheduler trigger_out LED driver pulse slots AFE / TIA settle then sample ADC sample instant codes_out Slot timeline LED ON settle sample sampling instant OFF sample jitter budget latency budget sample must stay inside plateau window Place the sample in the plateau and hard-trigger it; this reduces jitter sensitivity and improves ON/OFF subtraction repeatability.
Figure F7 — Slot timing drives both LED pulses and ADC trigger so the sampling instant stays inside a stable window with explicit jitter/latency budgets.

H2-8 · Low-power MCU partition: what stays analog vs digital

The highest-value split is simple: keep the sampling conditions clean and repeatable (timing windows, flags for saturation), then let the MCU perform minimal necessary digital steps (subtraction, guarding, quality metrics, packaging) using duty-cycled bursts. Average power is controlled by duty cycle, not by one component’s peak current alone.

Partition rules (keeps data usable while saving power)

Analog / near-front-end must guarantee
  • Deterministic slot timing and settle-then-sample windows.
  • Valid LED-OFF ambient sampling window (no turn-off transient contamination).
  • Saturation / overload flags so invalid samples are not “filtered into truth”.
Digital / MCU should handle (without overreach)
  • Per-slot subtraction and guarding (clamp/outlier removal) using consistent flags.
  • Lightweight quality metrics (residual ripple, saturation counters, noise proxy).
  • Timestamping, packet formatting, and event-driven reporting (no protocol stack deep dive here).

Low-power techniques (PPG-friendly and timing-safe)

  • Duty-cycled bursts: wake → sample burst → process → optional transmit → return to sleep.
  • DMA-first capture: ADC writes to memory with minimal CPU involvement; reduces both jitter and active time.
  • Event-driven reporting: normal mode uses low-rate summaries; anomalies trigger higher-rate uploads.
  • Staged enabling: start timebase/ADC → enable LED slots → run processing last; avoid wasted ON time.
  • Diagnostic flags: store saturation and residual metrics alongside data so recovery actions are evidence-based.

Average power budget table (fill with measured numbers)

Subsystem Active current Sleep current Duty cycle Average (estimate) Notes
LED (avg) Ipeak per slot ≈ 0 slot_on / period Iavg ≈ Ipeak·duty Usually the biggest lever
AFE / TIA Iactive Isleep burst duty Iavg Keep settle time short
ADC Iconv Istandby samples/period Iavg DMA reduces CPU time
MCU Iactive Isleep active time / period Iavg Prefer burst + DMA
Link / I/O Iactive Isleep event-driven Iavg Report anomalies faster

Watchdog and self-recovery (front-end stability only)

  • Triggers: DMA stall, slot timeout, repeated saturation flags, abnormal residual metric spikes.
  • Actions: reset sampling state, re-center offset/DC cancel, reduce LED peak temporarily, restart the burst schedule.
  • Log items: reset reason, saturation counter, ambient_resid statistics, timing error counter.
Power states and duty cycling for low-power PPG front ends State machine showing Sleep to Sample Burst to Process to Transmit/Store and back to Sleep. Swimlanes indicate when LED, AFE/ADC, and MCU are on or off to illustrate duty-cycle control of average power. Duty-Cycled Operation: Sleep ↔ Burst Sample ↔ Process ↔ Report State machine Sleep deep idle Sample burst slot sequence Process subtract + guard Transmit event-driven return to sleep after work is done Who is ON in each state LED AFE / ADC MCU Sleep Burst Process Transmit OFF ON OFF OFF LOW ON ON short LOW SLEEP WAKE ACTIVE TX duty cycle avg power recovery Average power is dominated by how long each block is ON. Burst + DMA + event-driven reporting keeps timing stable while saving power.
Figure F8 — A duty-cycled front-end schedule: short sampling bursts, minimal processing, optional transmit, then back to sleep with clear ON/OFF ownership.

H2-9 · Motion artifact & signal-quality metrics (front-end viewpoint)

Motion issues usually break PPG by pushing the DC level (contact/optical path shifts) and then amplifying residual ripple after subtraction. A robust front-end should provide dynamic-range margin, fast saturation recovery, and per-slot quality hooks (flags + residual metrics) so unreliable slots can be rejected or down-weighted downstream.

Where motion artifacts enter (coupling paths the front-end must tolerate)

  • Contact pressure changes: DC level shifts, sudden baseline steps, gain usage collapse.
  • Optical geometry changes: coupling loss and angle changes, ON/OFF residual grows, AC/DC ratio moves.
  • Added interference: lighting ripple or EMI spikes, burst outliers and periodic residuals appear.

What the front-end must provide (data + flags, not full algorithms)

Recommended per-slot hooks (export as counters, flags, or lightweight metrics):
Hook / field Definition (front-end) Why it helps
sat_flag ADC/TIA saturated or near-rail within the slot/burst. Bad data is not “filtered into truth”; reject or down-weight.
clip_count Number of clipped samples in a burst. Motion spikes become measurable evidence for gating.
ambient_resid Residual after ON/OFF subtraction (per slot). Detects geometry change and flicker leakage.
edge_sample_flag Sampling instant landed in edge/settling region. Exposes timing drift that amplifies jitter sensitivity.
slot_energy Lightweight magnitude/energy proxy for the slot waveform. Helps detect bursts dominated by artifacts without deep DSP.
dc_level_est (optional) Estimated DC baseline or offset code (front-end observable). Shows DC “push” that causes saturation or code-width waste.

Troubleshooting table (symptom → likely cause → front-end action)

Symptom (what is seen) Likely cause (front-end level) Front-end action + exported hooks
Waveform suddenly rails or turns flat DC baseline jumped (pressure/geometry), no headroom left Raise headroom (gain range), mark sat_flag, count clip_count, trigger burst reject
ON/OFF subtraction becomes unstable OFF sample contaminated by edge/recovery; timing drift Enforce settle windows, export edge_sample_flag, track ambient_resid
Burst shows sharp spikes / impulses Motion/EMI spikes, cable micro-movement, interference Clamp outliers, count clip_count, compute slot_energy, allow burst reject
Periodic residual ripple persists Lighting flicker leakage or geometry shift increasing residual Improve OFF sampling window; export ambient_resid trend for gating
One color channel degrades first (Red/IR) Channel headroom mismatch, aging, or slot alignment issue Per-channel flags, per-slot metrics; use dc_level_est / saturation rate to decide gain/current adjustments
After overload, several slots look wrong TIA/ADC recovery tail contaminates following sampling windows Short “cool-down” and mark burst invalid; track saturation rate + recovery counters
Artifact injection points and front-end mitigation hooks for PPG Diagram showing LED to optical path to PD to TIA to ADC to MCU, with arrows injecting pressure, geometry, and EMI/flicker artifacts. A hook column lists saturation flag, SQI, clamping, and residual metrics exported by the front-end. Artifact Injection → Front-End Hooks (Flags + Residual Metrics) LED driver slot pulses Optical path tissue + probe PD photo current TIA gain + headroom ADC codes pressure geometry EMI/flicker Front-end hooks exported per slot sat_flag clip_count ambient_resid edge_sample_flag clamp burst_reject slot_energy dc_level_est The goal is observability: export flags and residual metrics so motion-dominated slots can be gated without relying on deep algorithms at the front end.
Figure F9 — Motion and interference inject into the optical path and analog chain; front-end hooks (flags + residuals) make robust gating possible.

H2-10 · Calibration, self-test & aging drift management

Production readiness depends on repeatability: consistent LED current delivery, consistent analog gain/offset behavior, and consistent ambient reference sampling. A practical front-end plan combines factory calibration, in-field self-test, and drift observability so aging and temperature do not silently degrade headroom or subtraction quality.

Production calibration flow (6–8 steps)

  1. Dark baseline: capture ADC/TIA offset and noise floor with LEDs off.
  2. Ambient reference: record OFF-window behavior under a controlled ambient condition.
  3. Red steps: sweep a few current codes, record response and headroom margin.
  4. IR steps: repeat for IR, confirm channel-to-channel consistency.
  5. Gain verify: validate TIA gain ranges (ratio + saturation point).
  6. Subtraction verify: confirm ON/OFF subtraction residual is within guard limits.
  7. Store coefficients: write calibration values + version + CRC.
  8. Final verify: quick re-check to catch fixture issues and assembly variance.

Must-store calibration parameters (minimum set)

Category Parameters to store Used for
LED / drive current_code_map (per channel), channel trim, compliance_margin flag, LED temp reference consistent optical excitation and headroom planning
AFE / TIA gain_ratio per range, offset_code, saturation_threshold code, recovery baseline counter stable gain switching and predictable saturation behavior
Timing slot_width, sample_offset, off_sample_offset, timing_signature repeatable settle/sample windows and subtraction integrity
Integrity cal_version, date_code, CRC, last_pass_stamp traceability and safe updates of coefficients

In-field self-test (detect hardware failures early)

  • LED faults: open/short, over-temp derating, insufficient compliance headroom.
  • PD/TIA faults: PD disconnect, stuck output, abnormal saturation rate, recovery tail never clears.
  • Timing faults: repeated edge_sample_flag, slot timeout, DMA stall or missing trigger events.
  • Actions: flag degraded mode, re-init sampling chain, log reason codes and key counters for service.

Aging drift management (observability + boundary principles)

  • Observe drift via trends: rising ambient_resid, increasing sat_flag rate, falling slot_energy at the same drive code.
  • Correct at the chain first: keep the analog path in its linear region (headroom, gain range, current trim) before any ratio-level compensation.
  • Temperature boundary: use temperature as a context signal (log + guard thresholds); avoid hiding problems by over-correcting outputs.
  • Serviceability: store drift counters and last-cal stamp so field diagnosis is evidence-based.
Production calibration flow for a PPG front end Flow diagram showing dark baseline, ambient reference, red steps, IR steps, gain verify, subtraction verify, store coefficients, and final check. Output block indicates calibration data stored with CRC and version. Production Calibration Flow (PPG Front-End) → Cal Data Store Station sequence Dark baseline Ambient reference Red steps IR steps Gain verify Subtract verify Store cal Final Calibration data store (output) cal_coeff gain_trim offset timing_offsets cal_version date_code CRC verify_gate Store only what keeps the analog chain repeatable: drive mapping, gain/offset behavior, timing offsets, and integrity fields for traceability.
Figure F10 — A production flow that calibrates repeatability (not clinical outcomes) and stores a minimal, traceable coefficient set with integrity checks.

H2-11 · Validation & debug checklist (bench → phantom → clinical-ready signals)

This section provides an executable path to validate a PPG front end and isolate failures fast. The order matters: confirm timing, then confirm headroom & recovery, then verify ambient subtraction, then prove the noise floor, and finally confirm signal-quality hooks (flags/metrics) catch bad slots.

Debug mantra: Timing → Saturation/Recovery → Ambient subtraction → Noise floor → Hooks/SQI

Checklist (copy/paste friendly)

Stage Item How to measure Pass criteria (front-end) Evidence to log
Bench LED current pulse integrity Sense resistor or monitor pin; capture rise/fall and flat-top region; verify channel-to-channel repeatability. Sample point lands on a stable plateau; pulse width and peak are consistent across bursts; no unexpected ringing. Scope screenshot; LED drive code; supply voltage; temperature.
Bench Slot timing & sampling alignment Logic analyzer on timing pins/MCU GPIO; confirm Red/IR/OFF sequence, settle windows, and ADC sampling instants. Sampling avoids edges/recovery tails; OFF window is clean; timing does not drift over time. Slot trace; edge_sample_flag rate; firmware timing config dump.
Bench TIA saturation margin & recovery Force bright condition (increase LED current / ambient); observe rail behavior and time-to-recover into valid range. Saturation is rare in normal settings; if forced, recovery is fast and does not contaminate multiple slots. sat_flag, clip_count, recovery counter; affected slot indices.
Bench ADC noise floor (dark + OFF) With LEDs off: capture dark baseline; with OFF windows active: capture OFF samples over many bursts. Dark and OFF distributions are stable/repeatable; no unexplained drift; no code-width wasted by DC offset. RMS/percentiles; offset code; temperature; supply rails.
Phantom Controlled absorption / scattering Use a finger simulator or a repeatable optical fixture; step through low/medium/high transmission settings. No saturation in expected ranges; subtraction residual remains bounded; channel-to-channel behavior is consistent. slot_energy trend; sat_flag rate; ambient_resid distribution.
Phantom Ambient disturbance (flicker + strong light) Inject controlled ambient changes; verify OFF sampling captures it and ON/OFF subtraction suppresses it. ambient_resid remains stable; no systematic leakage indicating timing or recovery contamination. ambient_resid histogram; OFF window stats; edge_sample_flag rate.
Phantom Motion disturbance injection Apply repeatable pressure/geometry modulation; confirm hooks identify affected bursts/slots. Bad segments are detected and flagged (not silently averaged); clamp/burst_reject behaves deterministically. clip_count spikes; burst_reject count; SQI score per slot; timestamps.

Pass/Fail record (template)

Date Build / FW Sensor / Probe Bench (Timing / Sat / Noise) Phantom (Ambient / Motion) Outcome Root cause Fix action
YYYY-MM-DD HW rev / FW ver PN / lot P/F notes P/F notes PASS / FAIL — —
YYYY-MM-DD HW rev / FW ver PN / lot P/F notes P/F notes PASS / FAIL — —

Reference part numbers (examples for validation setups)

  • Integrated PPG AFEs (timing/diagnostics baselines): TI AFE4490 (pulse oximeter AFE with timing + LED + diagnostics), TI AFE4404 (3-LED optical AFE), ADI MAX86140 / MAX86141 (optical AFE with ambient light cancellation).
  • Photodiode TIA reference amplifier: TI OPA381 (photodiode transimpedance amplifier example family).
  • SpO₂ simulator / phantom tools: Rigel PULS-R Finger Simulator (Part No. 399A910); Fluke Biomedical ProSim SPOT Light (SpO₂ tester family); Fluke Biomedical ProSim SpO₂ Test Module (Part No. 3985658).
Debug decision flow for PPG front-end validation Decision flow for debugging PPG front-end issues: verify slot timing, then saturation and recovery, then ambient subtraction, then noise floor, then artifact hooks/SQI. Each decision points to a concrete action and evidence field. Figure F11 — Debug Decision Flow (Timing → Saturation → Ambient → Noise → Hooks) Start: collect traces slot + flags + stats Timing OK? evidence: edge_sample_flag Saturation / slow recovery? evidence: sat_flag, clip_count Ambient subtraction OK? evidence: ambient_resid Noise floor OK? evidence: dark/off RMS Actions (do these in order) Fix timing first move sample off edges Restore headroom gain/current/compliance Re-validate OFF window clean ambient sample Prove noise floor dark/off repeatable Confirm hooks/SQI behavior clamp + burst_reject + per-slot flags PASS: clinical-ready signals stable timing + headroom + subtraction + noise + hooks Always gate bad data with evidence (flags + residual metrics). Debug becomes deterministic when the same sequence is followed every time.
Figure F11 — A deterministic debug flow that prevents “random tuning”: fix timing first, then headroom/recovery, then ambient subtraction, then noise floor, then hooks/SQI.

Request a Quote

Accepted Formats

pdf, csv, xls, xlsx, zip

Attachment

Drag & drop files here or use the button below.

H2-12 · FAQs ×12 (with answers) + FAQ JSON-LD

These FAQs focus on practical front-end decisions: timing slots, LED current integrity, PD+TIA headroom and recovery, ambient rejection, ADC sampling trade-offs, low-power partitioning, and validation hooks for motion and drift.

1) When should timing and slot alignment be fixed before upgrading the ADC resolution?
If samples land on LED edges, settling tails, or saturation recovery, higher ENOB will not help. First confirm the slot timeline and move sampling into a stable plateau for each Red/IR/Off window. Track an edge-sample flag and repeatability across bursts. Only after timing is stable should ADC noise floor be optimized.
2) How should Red, IR, and LED-OFF slots be ordered to keep ambient subtraction stable?
An OFF sample must represent the same optical state as the ON sample, minus LED light. Place OFF windows close to their corresponding ON windows, but not inside edge settling or recovery tails. Keep OFF timing consistent across colors. Validate by checking that the post-subtraction residual stays bounded under bright ambient changes and flicker.
3) What are the symptoms of insufficient LED driver compliance headroom, and how is it confirmed?
Low compliance headroom causes current pulses to droop, distort, or mismatch across channels, which looks like unstable amplitude even with the same drive code. Confirm by measuring the LED current waveform and checking for a flat, repeatable plateau. Correlate drive code to a slot-energy proxy and watch for nonlinearity or early clipping.
4) Linear current sink or switching current regulator for LEDs: which is safer for clean PPG sampling?
Linear drivers are usually simpler to synchronize and tend to produce cleaner pulses, but waste power and generate heat at higher currents. Switching drivers improve efficiency but can inject ripple and EMI that leak into TIA and subtraction. If switching is used, align switching behavior away from sampling instants and verify residual metrics do not grow.
5) How do photodiode area, capacitance, and dark current affect TIA noise, bandwidth, and recovery?
Larger area often raises junction capacitance, which reduces TIA bandwidth margin and stresses stability, especially with high feedback resistance. Dark current and ambient DC push the TIA output toward rails, shrinking headroom and slowing recovery after overload. Choose PD size for usable signal without excessive capacitance, and verify stability and saturation behavior with step tests.
6) Ambient light keeps saturating the TIA or ADC. What front-end actions are most effective?
Subtraction cannot recover information that never stayed linear. First restore headroom by reducing gain, adjusting offsets or DC servo behavior, and limiting LED current where appropriate. Then validate that OFF sampling is clean and aligned. Finally confirm the subtraction residual stays bounded under bright changes. Log saturation flags and recovery counters to keep the fix evidence-based.
7) Why does 100/120 Hz flicker remain after LED-OFF subtraction, and what should be checked first?
Flicker residual usually means OFF is not sampling the same interference that contaminates ON, or timing is landing in edges or recovery tails. Check the exact sampling instants for ON and OFF, verify settle windows, and confirm recovery does not bleed into OFF. Then inspect the residual distribution across many bursts rather than one capture.
8) For PPG, when is SAR a better ADC choice than sigma-delta, and when is sigma-delta justified?
SAR is often preferred when precise slot synchronization, low latency, and deterministic sampling instants matter. Sigma-delta can provide high resolution but introduces group delay and bandwidth trade-offs that complicate tight slot timing and fast recovery workflows. Choose based on whether the sampling window must be tightly aligned to LED pulses and whether latency impacts the subtraction and gating flow.
9) What does sampling jitter damage in a PPG front end, and when does jitter budgeting become critical?
Jitter is most damaging when sampling is effectively synchronous or windowed tightly, because timing noise becomes amplitude noise after subtraction and filtering. It becomes critical when settle windows are short, when OFF subtraction relies on tight alignment, or when correlated sampling is used. Track drift via an edge-sample flag and residual metrics, and widen stable windows when possible.
10) In low-power designs, what should remain analog and what should move to the MCU digital side?
Keep analog responsible for clean capture: stable LED pulses, TIA linearity, and consistent ON and OFF sampling that enables reliable subtraction. Use the MCU for burst scheduling, lightweight filtering, quality scoring, and packet framing. Power is minimized by duty cycling, DMA buffers, and event-driven wakeups, but never by sacrificing stable timing and headroom control.
11) What minimum signal-quality hooks should be exported so motion-corrupted slots can be gated reliably?
Export evidence, not guesses: saturation flag, clipped-sample count, post-subtraction residual, edge-sample flag, and a simple slot-energy proxy. These hooks allow deterministic rejection or down-weighting when motion spikes, contact pressure shifts, or ambient changes dominate. Add clamp and burst-reject counters so debug can reproduce the same failure path instead of relying on subjective waveform inspection.
12) What is the minimum calibration and self-test set to keep production units consistent over temperature and aging?
Store a small, traceable set: LED drive mapping per channel, gain-range ratios, offset code, timing offsets for ON and OFF sampling, and a CRC with versioning. Self-test should detect LED open or short, PD disconnect, abnormal saturation rate, and timing slips. Drift is managed by trending residual and saturation statistics, not by hiding issues with output-level compensation.
icnavigator

ICNavigator helps engineers find verified ICs, alternatives, and fast quotes.

Explore
Categories
  • Power Management
  • MCU
  • Automotive ICs
  • Sensors
  • Interface & Transceivers
  • Analog Front-End
Get in Touch
  • Email: hello@icnavigator.com
  • WeChat/WhatsApp: +86-xxxx

© 2025 ICNavigator. All rights reserved.