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Digital Receiver & Channelizer for FPGA Ingress

Digital Receiver & Channelizer for FPGA Ingress

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A digital receiver/channelizer turns a wideband sampled stream into multiple narrowband, time-aligned channels by combining frequency translation, decimation, and filtering with fixed, auditable latency. The practical goal is repeatable correctness: predictable isolation and spur behavior, deterministic trigger alignment, and traceable health evidence via time tags, markers, and drop/overflow counters.

H2-1 · What this page solves (scope & boundary)

This page is a practical guide for turning an ADC sample stream into aligned, trigger-synchronous, deterministic sub-band channels that an FPGA can ingest and process reliably. It starts after the ADC (digital domain) and ends at FPGA-ready multi-channel streams + metadata.

Boundary (reader version): Allowed here = DDC/channelizer chains, sync triggers, deterministic latency, clock-tree implications for alignment, FPGA ingress framing/buffering, and verification. Not covered here = RF/LO/PA/LNA design, radar waveform generation, EW direction-finding algorithms, or full protocol/standards tutorials.

What “Channelizer output” means in practice

  • N sub-band/baseband streams (I/Q or real) with defined bandwidth, sample rate, and channel ID.
  • Deterministic latency: a repeatable trigger-to-sample mapping across boots/re-arms and configuration reloads.
  • Metadata sideband to make downstream processing debuggable: time tag/marker, gain/scale, overflow & drop counters, sequence number.

How this page hands off to sibling pages (without overlap)

  • If the bottleneck is RF front-end, LO synthesis, or wideband Tx/Rx hardware, use the Radar Transceiver page.
  • If the core question is timebase sources (OCXO/CSAC) or network time distribution, use the GPSDO / Distributed Timing pages.
  • If the problem is system BIT/BIST and lifetime health records, use the BIT/BIST & Health Monitoring page.
Figure F1. Scope of this page: wideband ADC samples → digital receiver ingress → DDC/channelizer core → N aligned sub-band streams into FPGA blocks
Wideband ADC stream to FPGA via DDC and channelizer Block diagram showing digital-only path: ADC samples enter framing and buffering, then DDC/channelizer generates N narrowband channels with metadata, plus synchronized trigger and clock-tree distribution to maintain alignment. Digital Receiver & Channelizer (Digital-Domain Only) Wideband ADC Samples frames · lanes · words Digital Receiver Ingress Framing · CDC · Elastic FIFO Drop counters · Sequence ID DDC / Channelizer Core NCO · Mix · Decimate · Filter FFT/PFB or Bank-of-DDC Deterministic pipeline N Outputs Ch1..ChN (I/Q) Time tag · Marker Scale · Counters FPGA Processing Blocks DSP Detect Log downstream downstream records Sync Trigger / Marker Alignment Point Clock Tree (impact on alignment) Ref / Timebase Distribution ADC FPGA Only the digital chain is shown: ADC samples → channel streams + sync markers → FPGA. RF/LO/PA stages are intentionally excluded.

H2-2 · One-minute definition (extractable answer block)

Extractable answer block (45–55 words)

A digital receiver and channelizer converts a wideband ADC stream into multiple narrowband FPGA-ready channels. A DDC translates frequency, decimates sample rate, and filters to shape bandwidth. A channelizer (FFT/PFB or DDC bank) outputs aligned sub-bands with markers/timestamps, enabling deterministic latency and synchronized triggering for coherent processing.

DDC in one line: three mandatory operations

  • Frequency translation (NCO + complex mixing) so the target band lands at baseband (or a chosen IF).
  • Decimation (often multi-stage) to reduce throughput while controlling alias folding.
  • Filtering & shaping to set passband ripple, stopband rejection, and group delay behavior.

Channelizer: the “many-channel contract” (what downstream expects)

  • Channel identity & rate: each output stream declares channel ID, bandwidth, and output sample rate.
  • Alignment hooks: a marker/time tag that makes trigger-to-sample mapping repeatable (deterministic).
  • Debuggability: counters/flags for overflow, dropped blocks, and sequence discontinuities.
Figure F2. DDC basics: NCO → complex mixer → CIC decimation → FIR compensation/shaping → I/Q output + marker
DDC basic blocks A clean DDC pipeline: NCO provides phase increment, complex mixer shifts frequency, CIC performs decimation, FIR stages compensate droop and shape the band, producing I/Q output with an alignment marker for downstream synchronization. DDC Core Blocks (Digital Down-Conversion) ADC Stream real or complex NCO phase_inc sin/cos Complex Mixer freq translate to baseband CIC Decimate ×R coarse rate drop CFIR compensation droop / image PFIR shaping pass/stop specs I/Q Output Stream scaled samples · channel ID marker/time tag · counters sin/cos MARKER Practical takeaway: DDC = translate + decimate + filter. Channelizer output becomes usable only when alignment markers and deterministic latency are defined.

H2-3 · System I/O contract: what goes in, what must come out

A channelizer cannot be evaluated—or debugged—without an explicit input/output contract. This section defines the minimum set of engineering fields that make the design measurable, repeatable, and FPGA-ingestable. (Digital domain only: no RF chain, waveform design, or direction-finding algorithms.)

Contract principle: Every output stream must be accompanied by enough metadata to answer two questions at any time: (1) “Where is this data in time?” and (2) “Is this data complete and correctly scaled?”

Inputs (must be stated up front)

  • ADC sample rate (Fs): sets folding boundaries and constrains feasible decimation factorization.
  • Target monitored spectrum: center/edges of each desired sub-band (and expected drift), defining NCO coverage.
  • Required dynamic range: headroom policy, scaling strategy, and saturation tolerance (spur risk control).
  • Max simultaneous channels (Nch): drives architecture choice (FFT/PFB vs bank-of-DDCs) and FPGA throughput.
  • Quality hints (ENOB/SNR, brief): only as a guardrail for realistic spur floor and phase-noise sensitivity (no ADC tutorial here).

Outputs (must be measurable and acceptance-ready)

  • Per-channel bandwidth (BWch) and output rate (Fsout): declared for every stream.
  • Channel isolation target: adjacent-channel leakage / stopband suppression as a numeric requirement.
  • Coherence requirement: allowed phase mismatch (or EVM bound) for multi-channel comparisons.
  • Latency budget: allowable total latency plus deterministic latency requirement (repeatable trigger-to-sample mapping).
  • Loss behavior: what happens on backpressure (drop blocks vs flag-and-hold), and how it is reported (never silent).

Minimum viable metadata (MVMD) for debuggability

  • time_tag (or sample_index): locates each block in time; enables alignment and replay.
  • trigger_marker: marks trigger events and alignment boundaries (frame start / sync pulse / capture gate).
  • channel_id: ensures every block is attributable after aggregation or packetization.
  • gain_scale: declares numeric meaning after shifts, rounding, or block scaling.
  • seq_no + drop_cnt + overflow_flags: proves continuity and exposes loss instantly.

Acceptance checks derived from the contract

  • Correctness: frequency translation and decimation match declared channel plan (tone lands where expected).
  • Isolation: adjacent-channel leakage meets target with defined guard band.
  • Determinism: trigger-to-sample offset repeats across re-arms and reloads within an agreed tolerance.
  • Integrity: sequence continuity holds; drops/overflows are flagged and counted, not hidden.
Figure F3. Data and metadata travel together: channel streams remain maintainable only when time/trigger identity and integrity counters are preserved end-to-end.
Data plus metadata sideband into FPGA Diagram showing a wideband data stream passing through ingress and channelizer into FPGA, with a parallel metadata bus carrying time tags, trigger markers, channel IDs, scaling info, and integrity counters. Data Stream + Metadata Sideband (FPGA Ingress Contract) Wideband Data sample blocks framed words Ingress CDC · FIFO · framing seq + drop counting DDC / Channelizer split into Ch1..ChN fixed alignment point FPGA parser per-ch FIFO health flags Metadata Sideband time_tag trigger_marker channel_id gain_scale seq_no drop_cnt flags Engineering rule: never allow silent data loss. Drops must increment counters and preserve time/trigger alignment markers.

H2-4 · DDC chain design: frequency plan → decimation plan → filter plan

A DDC becomes “designable and reviewable” when it follows a fixed three-step flow. The order matters: frequency placement determines what will fold; decimation determines what must be rejected; filtering finalizes ripple, stopband, and group delay to meet the contract.

Three-step flow: (1) decide where the band lands after translation, (2) choose multi-stage decimation that preserves alias safety, (3) size filters to meet isolation and latency constraints with predictable resource cost.

Step 1 — Frequency plan (placement and folding checks)

  • Define the target band edges (including expected drift) and select the translation target (baseband or a chosen digital IF).
  • Map images/interferers in the translated domain (where they will sit relative to the desired band).
  • Pre-check folding across future decimation stages: verify that likely interferers will not fold into the passband after the rate drops.
  • Leave margin near Nyquist: avoid placing the band so close to boundaries that a feasible transition band becomes impossible.

Step 2 — Decimation plan (factorization that controls alias risk)

  • Choose target Fsout from the channel contract (bandwidth + guard band + downstream throughput budget).
  • Factorize the total rate change into stages (R = R1×R2×R3) to balance resource cost and alias suppression.
  • Use CIC for coarse rate drop where efficient, then use FIR stages for compensation and final shaping.
  • At each stage, re-evaluate Nyquist limits and confirm that any folding products remain inside stopbands (not inside the desired band).

Pitfall #1 (CIC droop): Uncompensated CIC passband droop produces “tilted” amplitude response across the band. The symptom is inconsistent gain vs frequency that calibration tables cannot stabilize. Fix: include a compensation FIR stage (or integrate droop correction into the shaping FIR).

Pitfall #2 (wrong decimation ratios): A decimation split that looks “efficient” can allow interferers to fold into the passband after a stage boundary. The symptom is spurs that appear/disappear when ratios change. Fix: repeat stage-by-stage folding checks and adjust the factorization or add suppression before the fold point.

Step 3 — Filter plan (specs driven by isolation and determinism)

  • Passband ripple: determines amplitude consistency and calibration burden.
  • Stopband attenuation: directly sets channel isolation and adjacent leakage floor.
  • Transition band: drives filter order and FPGA cost; must remain feasible given Fs at that stage.
  • Group delay: must be stable and known to preserve deterministic latency and trigger alignment policies.

Design review checklist (quick, measurable)

  • Translated band placement verified; images/interferers mapped in the translated domain.
  • Decimation factorization fixed (R1×R2×R3) with Nyquist/folding check at every stage boundary.
  • CIC droop compensation decision documented (where correction occurs).
  • Filter specs recorded (ripple/attenuation/transition/group delay) and tied to channel isolation and latency budget.
  • Deterministic latency budget captured as a number (to be enforced in synchronization chapter).
Figure F4. Multi-stage decimation ladder: coarse CIC rate drop, then FIR compensation and shaping, with Fs shown at each stage to force folding checks.
Multi-stage decimation ladder A stepped ladder diagram showing rate reduction stages: CIC times R1, FIR times R2, FIR times R3. Each step annotates sample rate changes Fs0 to Fs3 and labels the role of each stage. Multi-Stage Decimation Ladder (Rate Plan) Input Stream Fs0 wideband CIC × R1 coarse decimation Fs1 = Fs0 / R1 Check droop FIR × R2 compensation Fs2 = Fs1 / R2 Check folding FIR × R3 final shaping Fs3 = Fs2 / R3 meets BW + isolation Output target Fs_out (Fs3) + BW_ch + guard band + deterministic latency budget Review rule: after every decimation stage, re-check Nyquist limits and confirm that folding products remain outside the desired band.

H2-5 · Channelizer architectures (FFT channelizer vs PFB vs many-DDC)

Architecture choice should follow the I/O contract: channel count and bandwidth plan, isolation/leakage limits, FPGA resource budget, and whether deterministic trigger alignment is required. This section provides an engineering map to pick the right channelizer family and avoid predictable failure modes.

Decision mindset: Choose the simplest architecture that meets isolation and deterministic latency. “More advanced” is not automatically “more correct” under FPGA constraints.

Comparison dimensions (what actually breaks in practice)

  • Channel plan flexibility: fixed equal-width bins vs variable center frequencies and bandwidths.
  • Isolation & leakage: scalloping loss, bin leakage, sidelobes, adjacent-channel rejection, and guard-band cost.
  • Resource & throughput: DSP slices, BRAM/FIFO depth, and timing closure under target fabric clocks.
  • Latency & determinism: fixed pipeline stages, re-arm/reload repeatability, and trigger-to-sample mapping stability.

Architecture notes (what each output “really is”)

FFT channelizer: outputs frequency bins (equal-width). Works well for many channels with moderate isolation needs, but amplitude can vary when tones fall between bins (scalloping), and leakage depends on windowing and guard-band policy.

PFB (polyphase filter bank): a “filtered FFT” that suppresses sidelobes and improves channel isolation. Higher filter cost and latency are traded for cleaner sub-bands and more predictable adjacent leakage.

Many-DDC: a bank of independent NCO/mixer/decimator/filter chains. Best when channels are sparse, re-tuned often, or have different bandwidths. Resource cost grows roughly with the number of simultaneous channels.

“When to choose what” (quick decision list)

  • Prefer FFT channelizer when channels are many, equal-width, and isolation is moderate with a defined window + guard band.
  • Prefer PFB when adjacent leakage/isolation is the top requirement and predictable sidelobe control is worth the extra latency and taps.
  • Prefer Many-DDC when channels are sparse or frequently re-tuned, bandwidths vary per channel, or exact center placement matters.
  • Hybrid is common: a coarse channelizer stage feeding a small number of per-channel DDC refinements (keep the contract clear).
Figure F5. Three channelizer families at a glance: key modules only (no math), plus quick badges for flexibility, isolation, latency, and resources.
FFT vs PFB vs Many-DDC channelizer architectures Three side-by-side block diagrams comparing FFT channelizer, PFB channelizer, and a bank of DDCs. Each column shows major modules and quick badges for flexibility, isolation, latency, and resource cost. Channelizer Architecture Map (FFT vs PFB vs Many-DDC) FFT Channelizer PFB Channelizer Many-DDC Bank Frame / Buffer Window (optional) FFT Bin Select / Pack Bin Streams → FPGA Flex: MED · Isolation: MED · Latency: LOW/MED · Cost: LOW Frame / Buffer Polyphase FIR Bank sidelobe control FFT Bin Streams (cleaner) Channels → FPGA Flex: MED · Isolation: HIGH · Latency: MED/HIGH · Cost: MED/HIGH Splitter / Router NCO + Mixer × N free center freq Decimate + Filter × N per-channel specs Pack + Metadata Ch Streams → FPGA Flex: HIGH · Isolation: HIGH/MED · Latency: MED · Cost: scales with N Rule of thumb: PFB buys isolation by spending taps and latency; Many-DDC buys flexibility by spending per-channel resources; FFT is efficient for equal-width bins.

H2-6 · Synchronization: triggers, alignment, and deterministic latency

“Synchronization” is only useful when it is defined precisely. This section separates four sync layers—phase, frame, timestamp, and deterministic latency—and provides a practical recipe for getting repeatable trigger-to-sample behavior through the channelizer pipeline.

What sync means (four layers that must not be mixed)

  • Phase-coherent sampling: channels share a stable phase reference for meaningful phase comparisons.
  • Frame alignment: blocks/frames begin at the same boundary across channels and sessions.
  • Timestamp consistency: time tags refer to the same epoch/scale and remain monotonic.
  • Deterministic latency: trigger-to-output offset is fixed and repeatable after reset/re-arm/reload.

Trigger sources (what changes is jitter and observability)

  • External trigger: direct and testable, but must be conditioned and synchronized before it becomes a marker.
  • PPS / time pulse: system alignment anchor; must define which sample edge is the reference boundary.
  • Frame pulse: aligns blocks; must protect against drift across reconfiguration and buffering changes.
  • FPGA internal trigger: highly repeatable if based on a single domain counter; must be time-tagged explicitly.

Alignment mechanism (align early vs align late)

Align at input: lock the trigger marker to a chosen sample boundary before the channelizer. This makes downstream latency easier to keep deterministic, but CDC mistakes can create ±1 sample jitter if not synchronized cleanly.

Align at output: run the pipeline freely, then re-align streams using time tags/markers. This tolerates some upstream variability but usually costs buffering and increases latency complexity.

Deterministic latency recipe (how to make it provable)

  • Fix pipeline stages: constant stage count and constant buffering policy for a given configuration.
  • Define the alignment point: where the marker is “captured” (input boundary or a defined internal stage).
  • Control reset/re-arm order: clear FIFOs and stage registers in a documented sequence, then arm on a known boundary.
  • Publish the offset: expose trigger_to_output_offset as a number (or encode as metadata) for acceptance testing.

Pitfall #1 (CDC ±1 sample jitter): A trigger crossing into the sample clock domain without a proper synchronizer can land on adjacent edges. Symptom: phase comparisons “jump” between arms. Fix: synchronize, re-time, then generate a single-domain marker.

Pitfall #2 (latency drift after reconfig): Changing buffering or pipeline depth without freezing the alignment point breaks determinism. Symptom: relative phase/time alignment fails after reload. Fix: lock the pipeline, or explicitly report the new offset as metadata.

Acceptance tests (fast, repeatable, and revealing)

  • Repeatability: re-arm N times and measure trigger-to-sample offset distribution (must be single-value or bounded as specified).
  • Reconfig loop: change configuration and restore; verify the offset is unchanged or correctly reported and compensated.
  • Cross-channel alignment: inject a common marker/signal and verify inter-channel phase/time alignment meets the contract.
Figure F6. Trigger enters → conditioned & synchronized → alignment marker captured → fixed pipeline latency → time-tagged output streams.
Synchronization path with deterministic latency Diagram showing trigger sources entering a synchronizer/conditioning stage, producing an alignment marker captured at a defined point, then passing through a fixed-latency pipeline to time-tagged channel outputs, highlighting CDC jitter risks and offset reporting. Trigger Alignment & Deterministic Latency (Practical Sync Path) Trigger Sources External trigger PPS / time pulse Frame pulse Sync / Conditioning synchronizer · edge align single-domain marker Alignment Point capture marker at sample boundary Fixed Pipeline constant stages DDC / Channelizer Pack + Metadata Time-tagged Outputs Ch1..ChN streams + marker + time_tag time_tag marker offset reported CDC risk: ±1 sample jitter if not synchronized Deterministic latency Fix the alignment point + freeze pipeline stages + publish trigger_to_output_offset Acceptance: re-arm repeatability, reconfig stability, and cross-channel alignment must match the contract.

H2-7 · Clock tree strategy (what matters for DDC/channelizer correctness)

This section focuses only on clock-tree choices that directly affect digital channelization correctness: repeatable trigger alignment, stable latency, and predictable baseband integrity. It avoids PLL theory and keeps the discussion in engineering criteria and observable symptoms.

Three clocks define outcomes: the ADC sample clock sets the ceiling for phase/spectral fidelity, the FPGA fabric clock controls timing closure and fixed pipeline behavior, and the trigger/marker clock determines alignment repeatability.

Clock-domain relationships (what must be declared upfront)

  • Fully synchronous: sample, fabric, and marker generation share a common reference and produce markers inside the sample domain.
  • Mixed synchronous: sample clock is coherent, but triggers arrive asynchronously and must be re-timed to a sample boundary.
  • Asynchronous: sample and trigger are unrelated; timestamps can still be consistent, but deterministic sample alignment becomes costly.

How jitter shows up after sampling (symptoms, not theory)

  • Raised noise skirt around tones in the baseband, most visible when narrow DDC bandwidth is used.
  • Phase inconsistency across channels or across re-arm events, breaking coherent comparison or subtraction.
  • “Leakage that never improves” even with better filters, when the limit is clock cleanliness rather than stopband design.

Multi-device sync (coherence vs maintainability)

Coherence-first: one reference → jitter cleaning → fanout → all ADCs/FPGA domains; markers derived from the same reference. This maximizes inter-device phase consistency but increases distribution complexity.

Maintainability-first: each board cleans locally while sharing a reference or time marker. This scales better, but the contract must state which sync layer is guaranteed (timestamp/frame vs phase coherence).

Engineering checklist (fast to audit, easy to verify)

  • Sample clock path: keep paths matched and observable (lock/health flags, measurable test points).
  • Marker path: create markers in the sample domain or re-time them to a defined sample boundary.
  • Fabric clock path: protect deterministic latency by freezing buffering policy and pipeline stage count per configuration.
  • Health reporting: publish loss-of-lock, missing-marker counters, and alignment error flags as part of system status.
Figure F7. Reference → jitter cleaning → fanout → ADC/FPGA/trigger domains, with markers aligned to the sample boundary.
Clock fanout and sync marker distribution for digital channelization Block diagram showing a reference clock feeding a jitter cleaner and fanout to ADC sample clock, FPGA fabric clock, and a sync marker distribution path. Marker alignment to sample boundary is highlighted. Clock Tree for Correct Channelization (Ref → Clean → Fanout) Reference Clock stable source / GPSDO Jitter Cleaner clean phase noise · lock status Clock Fanout / Distribution matched paths · monitoring ADC Sample Clock SNR / phase ceiling FPGA Fabric Clock timing closure / latency Sync Marker / Trigger PPS · frame pulse · align Key rule Markers should be generated or re-timed to the sample clock domain boundary to avoid ±1 sample ambiguity. Keep it auditable: lock/health flags, missing-marker counters, and alignment-error flags should be observable.

H2-8 · FPGA ingress: framing, buffering, and backpressure-proof streaming

A correct DDC/channelizer chain can still fail system requirements if ingress streaming is not robust. This section defines a practical data contract (blocks + metadata), shows how to buffer burstiness safely, and makes overload behavior controlled, observable, and recoverable.

Ingress contract (what each channel must carry)

  • Fixed-length blocks: each channel emits blocks with a constant block_len (samples per block).
  • Identity: chan_id and a monotonically increasing seq_no for continuity checks.
  • Time alignment: time_tag at block start, plus an optional marker with intra-block offset.
  • Integrity & diagnostics: optional CRC, plus drop_cnt, overflow_flags, and FIFO watermark reporting.

Non-negotiable rule: silent data loss is unacceptable. Any loss must be surfaced by counters and flags so that a downstream consumer can reconstruct exactly when and how continuity broke.

Buffering (elastic buffers make burstiness safe)

  • Per-channel elastic FIFO absorbs arbitration jitter and bursty arrivals without cross-channel interference.
  • Watermark policy: define low / mid / high thresholds and report the high-watermark for diagnosis.
  • Burst vs sustained throughput: a FIFO buys time against bursts, but sustained overload will still overflow.

Backpressure policy (choose how overload fails)

  • Mode A — DROP + FLAG: drop whole blocks and increment drop_cnt; preserve seq_no semantics so discontinuity is explicit.
  • Mode B — RATE-REDUCE: increase decimation or reduce output rate and publish the active rate state in metadata.
  • Mode C — STALL: apply backpressure upstream only when upstream can pause safely without turning the problem into random overflow.

Counters that make field debugging possible

  • seq_no gap detection: immediate proof of loss or reorder.
  • drop_cnt: quantifies discontinuity; supports “how often” and “when” analysis.
  • CRC / integrity flags: distinguishes transport corruption from overload loss.
  • FIFO high-watermark: identifies chronic near-overflow and arbitration imbalance.
  • overflow_flags: marks the exact interval where buffering limits were exceeded.
Figure F8. Per-channel FIFOs + scheduler/arbiter + unified stream, with explicit loss/overload policies and diagnostic counters.
FPGA ingress framing, buffering, and backpressure-proof streaming Diagram showing multiple channel streams feeding per-channel FIFOs, watermark counters, an arbiter/scheduler, and a unified output stream. Backpressure policy modes and diagnostic sideband are highlighted. FPGA Ingress: Fixed Blocks + Per-Channel FIFOs + Controlled Overload Channel Outputs fixed-length blocks Ch1 Ch2 Ch3 ChN Per-Channel FIFOs elastic buffering + isolation FIFO x N watermark low/mid/high high-watermark report Arbiter / Scheduler fairness · pacing Unified Stream blocks + metadata Backpressure Policy DROP+FLAG RATE-REDUCE STALL Always publish: seq_no, drop_cnt, overflow_flags, and FIFO high-watermark. Diagnostics sideband: time_tag · marker · seq_no · CRC · drop_cnt · overflow_flags · watermark Goal: overload behavior is controlled (policy), observable (counters), and recoverable (explicit discontinuity).

H2-9 · Performance knobs: dynamic range, spurs, and channel isolation

Performance problems become solvable only when they map to controllable knobs and measurable outcomes. This section ties common symptoms (spur lines, raised skirts, poor isolation) to specific digital causes and practical verification tests, without drifting into RF or general DSP theory.

Key mindset: filters and decimation shape spectra, but they cannot “repair” saturation, overflow, or inconsistent scaling. First guarantee headroom and repeatable arithmetic behavior, then optimize isolation.

Dynamic range knobs (headroom first, fidelity second)

  • Headroom rules: set per-stage limits so no block hits overflow during worst-case input amplitude and burst conditions.
  • Saturation behavior: prefer explicit saturation with flags over wrap-around that creates unpredictable spur forests.
  • Scaling points: choose where to down-shift (or normalize) so that CIC growth, FFT/PFB accumulation, and FIR taps do not clip.
  • Block scaling metadata: if block-floating scaling is used, publish the exponent/scale so downstream can interpret amplitude consistently.

Spur sources (symptom → likely cause → quick test)

  • NCO quantization / phase truncation: discrete spurs that move predictably when the tuning frequency is swept. Test: sweep NCO center and confirm spur movement law.
  • Rounding vs truncation: spur strength that changes sharply with input amplitude or scale state. Test: hold frequency constant and step amplitude; watch spur “stair-step” behavior.
  • CIC/FIR coefficient quantization: passband ripple or leakage that tracks stopband/side-lobe limits. Test: run a passband sweep (or multitone) and compare ripple/leakage before/after coefficient changes.
  • Overflow / saturation: unstable, non-repeatable spur patterns and raised floors that appear under burst events. Test: replay the same vector repeatedly; non-repeatability strongly implicates overflow or scaling state transitions.

Channel isolation knobs (side-lobes + guard band + measurement)

  • Side-lobe control: window/PFB/FIR stopband settings determine leakage floors and scalloping sensitivity.
  • Guard band: reserve transition bins (or transition bandwidth) so adjacent-channel energy does not fold into the passband.
  • Edge-case testing: place a tone near the passband edge and measure adjacent leakage; this exposes true isolation limits.
  • Visualization outputs: track output spectrum, adjacent-channel leakage, and passband ripple as the primary acceptance plots.

Practical order of operations: (1) eliminate overflow and scaling ambiguity, (2) confirm NCO/rounding spur behavior is stable, then (3) tune isolation via side-lobes and guard band with edge-of-band tests.

Figure F9. A spur taxonomy map that links observable spur patterns to digital root causes and the right knob to adjust.
Spur taxonomy map for a digital channelizer Central output spur block with four cause branches: NCO quantization, rounding/truncation, coefficient quantization, and overflow/saturation. Each branch includes a short test hint and a knob hint. Spur Taxonomy Map (Cause → Knob → Test) Output Spurs lines · skirts · leakage repeatability matters NCO Quantization phase truncation test: freq sweep Rounding / Trunc bit-growth control test: amplitude step Coeff Quant CIC droop · FIR ripple test: passband sweep Overflow / Saturation headroom rules test: repeatability Knobs → Tests → Metrics sweep · amplitude step · passband scan · replay vector → spur lines · leakage · ripple Tune in order: eliminate overflow → stabilize arithmetic → then optimize isolation with guard bands and side-lobes.

H2-10 · Calibration & digital correction workflow (bring-up to production)

A channelizer that looks correct in a lab demo can still fail in production unless calibration and version control are built in. This section defines a bring-up loop using known tones, establishes channel-to-channel alignment targets, and shows how to lock, identify, and roll back coefficient profiles with a production-friendly self-test signature.

Bring-up: prove frequency translate + decimation + latency offset

  • Inject a known tone (or a small multitone set) at a controlled frequency plan.
  • Verify translation direction and center placement by checking the baseband tone location.
  • Verify decimation by confirming output sample rate and expected bandwidth.
  • Measure a stable latency offset from trigger/marker to block start; record it as the reference alignment number.

Calibration targets: gain/phase alignment + passband flattening

  • Gain alignment: match channel amplitudes so coherent comparison does not bias results.
  • Phase alignment: enforce stable channel-to-channel phase offsets for coherent systems and repeatable triggering.
  • Passband flattening: compensate CIC droop or residual ripple using a correction table or compensator coefficients.

Deliverable format: corrections should be stored as a named coefficient profile with explicit IDs, not as hidden “tweaks.” The active profile must be visible to downstream consumers and to production logs.

Versioning and rollback (make it maintainable)

  • Profile ID: the active configuration/coeff set identifier reported in metadata and logs.
  • Coeff version: a monotonic version for filters and correction tables, enabling traceability.
  • Rollback rule: if self-test signature fails or alignment drifts beyond limits, revert to the last known-good profile.
  • Contract stability: output framing and metadata fields must remain stable across profiles to protect downstream tools.

Production self-test: short vector + signature/CRC

  • Short test vector: a compact tone/multitone pattern that exercises frequency plan, scaling, and isolation quickly.
  • Signature: compute a small set of checks (key-bin energy, phase offsets, ripple bounds) and/or CRC.
  • Decision: PASS locks the profile; FAIL flags the unit and emits the diagnostic context (Profile ID, counters, offsets).
Figure F10. Calibration loop: inject → measure → update → lock a profile, plus a production self-test signature.
Calibration and digital correction workflow for a channelizer Left-to-right loop showing inject test tones, capture outputs, measure metrics, update coefficients, lock a profile ID, and iterate. A production self-test branch computes a signature or CRC for pass/fail. Calibration Workflow (Bring-up → Lock Profile → Production Self-Test) Inject tone / multitone Capture channel outputs Measure freq · gain · phase Update coeff / tables Lock Profile ID Iterate until metrics meet limits (alignment · ripple · leakage) Production Self-Test Short Vector Signature or CRC PASS FAIL Keep it traceable: Profile ID + coeff version + rollback rule + self-test signature enable production and field confidence.

H2-11 · Verification checklist (lab tests that prove it’s done)

This checklist defines “done” for a digital receiver/channelizer starting after sampling (digital domain). Each test is written as Stimulus → Observable → Pass criterion so results are repeatable, traceable, and auditable in logs (time tags, markers, sequence numbers, and counters).

Evidence rule: every pass/fail must be explainable using at least one of: (1) spectrum/plots, (2) metadata (time_tag/marker/seq_no), and (3) counters (drop_cnt/overflow_flags). Silent failure modes are treated as failures.

1) Frequency correctness (translation error + bin alignment)

  • Stimulus: inject a single tone at three positions: passband center, near passband edge, and near the intended guard band.
  • Observable: peak bin index (or measured frequency), plus consistent time_tag/marker location for the capture window.
  • Pass criterion: |f_meas − f_expected| ≤ X Hz (or ≤ Y bins) and the peak bin does not drift across N repeats.

Failure signature: sign errors or axis mistakes often show as mirrored placement or edge tones that land on the wrong side of baseband.

2) Decimation correctness (Fs change + alias checks)

  • Stimulus: two-tone test: Tone-A inside passband, Tone-B outside passband at a location that should be rejected (near folding boundaries).
  • Observable: output rate (Fs_out) derived from block timing + block_len, and residual energy of Tone-B in output spectrum.
  • Pass criterion: Fs_out matches configuration (or ≤ X ppm), and alias residue of Tone-B ≤ −A dBc at the output.

Guardrail: validate overflow_flags remain clear during this test; clipping can imitate “alias/leakage” and hides the real issue.

3) Isolation (adjacent leakage + stopband attenuation)

  • Stimulus: place a tone near the passband edge (“edge tone”), plus an optional second tone centered in a neighbor channel.
  • Observable: adjacent leakage ratio (ACLR-like measure), and measured stopband floor (or stopband attenuation) from the output spectrum.
  • Pass criterion: adjacent leakage ≤ −C dBc and stopband attenuation ≥ D dB (per channelizer configuration).

Repeatability clause: results must be stable across repeats; non-repeatable leakage often indicates scaling state changes or overflow.

4) Synchronization & deterministic latency (trigger consistency across cold boot / reconfig)

  • Stimulus: apply a repeating external trigger / PPS / frame pulse; run N events, then repeat after cold boot and after reconfiguration.
  • Observable: marker offset within blocks, time_tag alignment to block boundary, and channel-to-channel alignment error in samples.
  • Pass criterion: marker jitter is 0 sample (or ≤1 sample by spec), and pipeline latency does not drift between runs (Δlatency within limit).

Typical failure: ±1 sample ambiguity often points to a trigger crossing into the sample domain without a defined re-timing boundary.

5) Stability (long-run counters + controlled overload behavior)

  • Stimulus: continuous run for T hours at representative channel count and output rate; repeat with a stress condition (higher throughput or burstier triggers).
  • Observable: drop_cnt, overflow_flags, FIFO high-watermark, seq_no continuity, and profile/version IDs in logs.
  • Pass criterion: normal mode: drop_cnt==0 and overflow_flags==0; stress mode: any drops must be explicitly flagged and time-located, never silent.

Acceptance focus: “fails safely and visibly” is acceptable under stress; “fails silently” is not.

Figure F11. Test matrix board: test item → observable → pass criterion (plus typical tooling).
Verification test matrix board for a digital receiver/channelizer A matrix listing five test items with observables and pass criteria: frequency correctness, decimation correctness, isolation, sync/latency, and stability. A tooling column lists typical lab fixtures. Verification Test Matrix (Digital Channelizer) Test item Observable Pass criterion Tool / fixture Frequency correct peak bin · f_meas marker stable |Δf| ≤ X Hz bin drift = 0 tone source FFT capture Decimation correct Fs_out · alias floor overflow clear Fs match ≤ X ppm alias ≤ −A dBc 2-tone vector rate logger Isolation adj leak · stopband edge tone test leak ≤ −C dBc stopband ≥ D dB spectrum view guard sweep Sync & latency marker offset Δlat across boots jitter ≤ 0..1 samp Δlat within limit PPS/trigger time tag log Stability drop_cnt · overflow seq_no continuity normal: counters=0 stress: flagged only long-run logger counter export Define X/A/C/D and sample-jitter limits from the system contract; keep results repeatable across cold boot and reconfig.

Example part numbers (tools & fixtures)

These are common reference items used to run the checklist. Equivalent models are acceptable if specifications match (frequency stability, trigger accuracy, bandwidth, and logging capability).

A) Lab instruments (Example P/N)

  • GPSDO / 10 MHz + 1PPS reference: Microchip TimeProvider 8040C (8040C series as a reference class).
  • Frequency counter: Keysight 53230A (general-purpose frequency/interval verification).
  • Oscilloscope: Keysight InfiniiVision MSOX3000T series (example: MSOX3104T) for trigger/marker timing sanity checks.
  • Signal generator (optional for end-to-end tone injection): Keysight N5182B (MXG class) or equivalent.
  • Spectrum/Signal analyzer (optional for external observation): Keysight N9020B (MXA class) or equivalent.

B) Clock/trigger fixtures & reference components (Example P/N)

  • Clock system / jitter cleaner class: Analog Devices AD9545; Texas Instruments LMK04828.
  • Clock fanout buffer class: Analog Devices ADCLK948; TI LMK1C110x family.
  • Logic level/trigger conditioning (example family): TI SN74LVC series (buffer/level translate as needed).
  • FPGA bring-up platform (example boards): AMD Xilinx KCU105, VCU118 (used as repeatable capture + logging hosts).

Procurement-friendly mapping: prioritize (1) stable 10 MHz + 1PPS reference, (2) repeatable trigger injection, and (3) reliable logging of counters and time tags. These three capabilities cover the majority of acceptance risks.

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H2-12 · FAQs (Digital Receiver & Channelizer)

These FAQs focus on the post-ADC digital chain: DDC/channelizer architectures, synchronization, deterministic latency, isolation, scaling, and production-ready self-test evidence (time_tag, marker, seq_no, drop_cnt).

Why do DDCs often use “CIC + FIR” instead of one large FIR?
CIC stages provide very efficient large-rate decimation using only adders, which is ideal for the first “coarse” drop in sample rate. A smaller FIR then cleans up the passband, compensates CIC droop, and sets the final stopband/transition shape. Verify with a passband sweep (ripple/droop) and an alias test tone outside band.
Why can decimation make “random-looking spurs” show up more easily?
Decimation changes where quantization noise and arithmetic artifacts fold in frequency, and it can expose scaling-state problems. Overflows, saturation, or truncation that were “masked” at high rate may become visible as discrete lines after rate changes. Check repeatability by replaying the same vector; inspect overflow_flags, headroom rules, and rounding vs truncation choices.
How does channel leakage differ between an FFT channelizer and a PFB channelizer?
An FFT-only channelizer is sensitive to bin leakage and scalloping; tones near bin edges leak into neighbors based on the window shape. A PFB adds prototype filtering before the FFT, typically lowering side-lobes and improving isolation at the cost of more resources and latency. Measure with an edge-tone test and report adjacent leakage (ACLR-like) plus stopband floor.
In coherent multi-channel processing, how can fixed deterministic latency be proven?
Use a shared trigger and record marker offsets and time_tag alignment at the channelizer output, then repeat across many events. Repeat again after cold boot and after reconfiguration to confirm the pipeline latency does not drift. Pass criteria should be sample-level: marker jitter of 0–1 sample and stable Δlatency within the system limit across runs.
When a trigger crosses clock domains, how is the common ±1 sample jitter diagnosed?
±1 sample jitter usually means the trigger is not re-timed at a defined boundary in the sample clock domain. Log the marker insertion point and compare block offsets across repeated identical triggers; the ambiguity shows as two adjacent offsets. Move the alignment point earlier (input-side) or insert a deterministic re-timing step, then re-run the same event set to confirm stability.
How does NCO word length affect spurs and resource usage?
NCO phase truncation and limited accumulator width can create predictable spurs that move with tuning frequency. Increasing word length reduces truncation artifacts but costs logic/DSP and may increase power and routing pressure. A practical method is a frequency sweep: confirm spur movement is stable and below the spur mask while selecting the smallest width that meets isolation/SNR targets.
Why is poor passband flatness often misdiagnosed as “the ADC is not good enough”?
Passband tilt and ripple often come from digital stages: CIC droop, FIR coefficient quantization, or an overly aggressive transition band. The symptom looks like reduced “dynamic range,” but it is frequency-dependent amplitude error, not random noise. Run a swept-tone passband measurement, then apply droop compensation or a correction table; validate improvements without changing the ADC or sampling clock.
How should guard bands be chosen to avoid adjacent folding or leakage?
Guard band width should cover the filter transition region plus margin for worst-case side-lobes and tuning uncertainty. Define it from measurable limits: adjacent leakage target (−C dBc) and stopband attenuation (≥D dB). Validate using an edge-tone placed near the channel boundary and measure neighbor-channel energy across repeated runs; adjust transition bandwidth or prototype filter as needed.
If FPGA output bandwidth is insufficient, what should be changed first: channels, decimation, or format?
Start with the system I/O contract: preserve required bandwidth and metadata first, then reduce load. The safest first lever is often channel count or duty (disable unused channels), because it keeps per-channel fidelity and timing semantics unchanged. Next adjust decimation where guard band/isolation still meets limits. Format changes (bit width/packing) should be last and must keep time_tag/seq_no/drop_cnt to retain diagnosability.
How should coefficient quantization and rounding be chosen to avoid overflow without hurting SNR?
Separate two decisions: headroom budgeting (to prevent overflow) and arithmetic noise control (to protect SNR). Set explicit saturation/overflow flags and scale at known points where bit-growth occurs (CIC, FFT/PFB accumulation, FIR sum). Prefer rounding over truncation when noise matters, and verify with repeatability tests plus spur masks. Confirm overflow_flags remain clear in nominal operation and any drops are logged, not silent.
In multi-board synchronization, how can it be determined quickly whether the clock tree or the alignment point is at fault?
Use A/B isolation: keep the same alignment logic and change only the reference/clock distribution, then keep the same clock and change only the alignment insertion point. Clock-tree issues tend to appear as phase drift or frequency offset over time, while alignment-point issues show as fixed offset errors or ±1 sample ambiguity. Compare marker jitter, time_tag consistency, and stable Δlatency across cold boot and reconfig to localize the root cause.
How can an “online self-test vector” be built to catch channelizer faults quickly in the field?
Use a short tone or multitone vector that exercises translation, decimation boundaries, and isolation (including an edge-tone case). Compute a compact signature: key-bin energy ratios, expected marker offset, and an integrity CRC over selected blocks. Log Profile ID and coefficient version with the signature so failures are traceable and rollback is possible. A pass should also require seq_no continuity and drop_cnt==0 under nominal conditions.
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