Zero-Cross & Phase Detection (Comparators & Schmitt Triggers)
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This page shows how to build zero-cross and phase-detection edges you can trust by controlling hysteresis, delay, and noise so false triggers and phase error stay within a measurable budget. It turns real waveforms into repeatable timestamps (Δt → φ), with practical front-end conditioning, validation methods, and selection checks.
What this page solves (zero-cross & phase edges you can trust)
Zero-cross and phase detection are edge-quality problems: noise, delay, and hysteresis decide whether the digital edge is stable enough for timing, metering, and control.
The deliverable is a trustworthy edge (not just “crossing 0V”)
- Edge stability: no multi-toggling near the crossing (no double-count / chatter).
- Time certainty: edge timestamp jitter fits the timing budget (ns–µs depending on the use case).
- Phase correctness: systematic delay and drift do not bias the phase estimate beyond the allowed error (degrees).
Three error channels that must be budgeted and verified
1) Noise → edge jitter
Near a crossing, small slope (dv/dt) turns small voltage noise into large time jitter. A “quiet” edge is often a slope problem.
2) Delay → phase bias
Comparator delay is not a constant; it changes with overdrive, common-mode, temperature, and output loading. That variation becomes a systematic phase shift unless measured and guarded.
3) Hysteresis → false-trigger guardband
Hysteresis blocks chatter and ringing, but it also moves the effective switching point. The design goal is: enough VHYS to stop multi-toggles, not so much that phase error grows unbounded.
Metrics to lock before hardware (so “good” is measurable)
- Phase error (°): define max bias + max drift across temperature and amplitude.
- Edge jitter: define RMS (for statistical performance) and peak-to-peak (for worst-case) at the capture pin.
- False trigger rate: define as events per time or per cycles (example target framing: < 1 extra edge / 106 half-cycles in the expected EMI environment).
System view: signal chain + the three error tags
The rest of the page expands each tag into concrete design knobs (filtering, hysteresis, overdrive, capture) and a verification plan (jitter histogram and false-trigger statistics).
Zero-cross vs phase: definitions, edge choice, and what “accuracy” means
A phase detector is a time measurement system: two edges become timestamps, timestamps become Δt, and Δt becomes phase. “Accuracy” must be defined as an error chain from volts to time to degrees.
Definitions (keep the language consistent)
Zero-cross edge
A digital transition generated when the input crosses a reference threshold (often 0V or an equivalent shifted threshold).
Phase measurement
Two channels produce edges; a timer captures tV and tI; the difference Δt maps to phase.
Edge choice rules (avoid the most common engineering mistakes)
For AC metering (50/60 Hz)
- Prefer normalized timing: use Δt/T (reduces sensitivity to frequency drift).
- Prefer stable slope: edges at low dv/dt amplify jitter; filtering may help but adds phase shift.
- Use both polarities only if the chain is symmetric; otherwise a consistent single polarity reduces bias ambiguity.
For sync timing / phase compare triggers
- Prefer one edge direction (e.g., rising only) to keep digital logic deterministic.
- Always add a hold-off window if ringing near crossing can retrigger.
- Output matters: open-drain rise time depends on pull-up and capacitance; push-pull often timestamps cleaner.
For distorted / notched waveforms
- Do not assume the zero crossing is unique; notches and harmonics can create multiple candidate crossings.
- Consider a fixed-threshold crossing (or a window) when the 0V region is unstable.
- Validate with statistics: edge timing histograms reveal when waveform shape dominates jitter.
Accuracy mapping: mV → ns → degrees (the only definition that scales)
- Threshold error (mV) becomes time error (Δt) through the crossing slope. Small dv/dt magnifies Δt.
- Noise becomes timestamp jitter. Hysteresis reduces multi-toggling but does not remove jitter if slope is still small.
- Delay variation becomes phase bias. Delay changes with overdrive and temperature, so the “phase zero” must be guarded or calibrated.
- Phase conversion: for mains, φ ≈ 360°·Δt/T (T = 20 ms @ 50 Hz, 16.67 ms @ 60 Hz). The capture resolution and ISR latency must be below the intended Δt budget.
Diagram: two waves → two timestamps → Δt → phase
A clean phase measurement starts by making tV and tI repeatable: reduce chatter (VHYS + hold-off), keep delay stable (overdrive-aware), and verify with timestamp histograms.
Front-end sensing: dividers, current sense, and safety boundaries
A stable zero-cross edge starts at the interface. The front-end must deliver a predictable crossing slope, a bounded threshold shift, and a safe fault path before any comparator settings matter.
Interface choices (voltage vs current) and what they do to the crossing
Voltage sense (Vac)
- Divider + series limit sets source impedance seen by the comparator.
- RC can reduce HF trash, but it also reduces dv/dt near the crossing and increases time jitter sensitivity.
- Clamps/TVS protect against surge/ESD, but leakage and capacitance can reshape the crossing region.
Current sense (I for phase / timing)
- Shunt: strong signal, but switching noise and ground bounce can pollute the zero region if routing is careless.
- CT: clean isolation from ground noise, but magnetizing current and burden choices can distort the crossing timing.
- Resistor networks: convenient biasing/limiting, but high impedance magnifies bias/leakage into threshold drift.
The silent killer: source impedance turns tiny currents into threshold shift
Why high-R dividers drift
Input bias current, clamp leakage, and board contamination behave like small error currents. With high source resistance, they create a real DC shift:
Vshift ≈ Ierror × Rsource
How it shows up in phase systems
- Not random jitter: it is a systematic timing bias that can move with temperature/humidity.
- Worse near shallow crossings: small dv/dt converts small Vshift into noticeable Δt.
- Debug hint: if timing changes with humidity/handling, suspect leakage × high-R first.
Safety boundary (performance comes after survivability)
- Mains/high-voltage sensing must first satisfy isolation and clearance/creepage constraints.
- Keep the fault path explicit: clamp currents should return through a controlled path, not through the sensitive reference/ground of the comparator.
- Isolation chain details (component choices, CMTI, barriers) belong to the dedicated isolated comparator chain page.
Diagram: divider + clamps + RC into the comparator input
Keep Rsource intentional: it sets both the protection current limit and the sensitivity to bias/leakage-driven threshold drift.
Conditioning for stable crossing: filtering, limiters, and blanking windows
Stable crossings come from controlled bandwidth, bounded input excursions, and a time window that blocks ringing from turning into extra edges. The goal is fewer false edges without exceeding the phase-delay budget.
Symptom → knob mapping (fast triage)
Multi-toggling near crossing
Increase VHYS and/or add a hold-off window so the system accepts only one edge per half-cycle.
Spike-driven false edges (EMI/ESD)
Limit peak input excursions with series resistance and clamps; then filter residual HF energy.
Phase bias too large
Re-check filter phase delay and delay variation vs overdrive. Reducing noise is useful only if delay stays predictable.
Filtering: lower HF noise, but account for phase delay (do not guess)
- Pick the target noise band: switching edges and EFT bursts require different filtering than harmonic distortion.
- Expect phase delay: any low-pass/band-pass introduces timing shift around the crossing; treat it as a budget item (Δtfilter).
- Validate with timestamps: measure the edge timing before/after filtering and confirm the shift stays within the allowed phase error.
Limiters and blanking: protect the input and enforce one edge per event
Limiters / clamps
Keep the signal within a predictable range during surge/ESD. Series resistance sets clamp current and reduces ringing energy.
Blanking / hold-off window
After the first valid edge, ignore the input for a short window long enough to cover ringing.
Too short → double-count; too long → missed events and control lag.
Diagram: noisy crossing causes multiple edges; hold-off enforces one clean edge
Treat blanking as a timing budget item: it should cover ringing but stay shorter than the system’s allowed detection and control latency.
Comparator vs Schmitt trigger: when each wins for zero-cross
Device choice is an edge-quality trade. Schmitt gates excel at noisy slow ramps, while comparators win when threshold and hysteresis must be computed and controlled for phase accuracy.
Quick decision (1 minute)
Schmitt trigger wins when
- Slow ramps and long/noisy lines cause chatter near the crossing.
- Fixed thresholds are acceptable (absolute accuracy is not the KPI).
- Simple, low-power digitization is preferred over threshold programmability.
Comparator wins when
- Threshold control is required (Vref, offset crossing, windows).
- Hysteresis must be computed from noise and phase-error budgets.
- Phase accuracy requires predictable delay and an explicit error budget.
Output type changes timestamp quality (OD vs push-pull)
Open-drain / open-collector
- Rise time is external: Rpull-up × Cload defines the rising edge slope.
- Great for wired-OR and cross-voltage domains, but slow rises can increase capture jitter.
- Design action: treat pull-up strength and load capacitance as timing budget items.
Push-pull
- Steeper edges and stronger drive often improve timestamp repeatability.
- No pull-up required, simplifying edge-shape control for timer capture.
- Best fit when edge timing/jitter is the primary KPI.
Threshold control vs fixed thresholds (what changes the phase result)
- Schmitt gate: robust against slow/noisy crossings, but VTH+ / VTH− are typically fixed and can move with VDD and temperature.
- Comparator + external hysteresis: explicit Vref and VHYS allow deterministic windowing and phase alignment, at the cost of more careful front-end budgeting.
- Rule of thumb: if “phase in degrees” is a KPI, use a comparator path so VHYS and Vref can be engineered and verified.
Diagram: Schmitt gate vs comparator + external hysteresis
If edge timing is captured by a timer, prioritize predictable thresholds and edge slopes; output structure (OD vs push-pull) directly affects timestamp repeatability.
Designing hysteresis: compute VTH+ / VTH− and avoid threshold drift
Hysteresis must be engineered: large enough to block noise-driven multi-toggles, but not so large that it creates unacceptable phase bias. Threshold drift is dominated by bias/leakage currents multiplied by source impedance.
Set VHYS from two budgets (noise immunity and phase error)
Noise immunity floor
- Estimate the peak noise around the crossing: noise(pk).
- Choose a guard factor k to cover ringing/unknowns.
- Set a minimum: VHYS ≥ k · noise(pk).
Phase bias ceiling
- Hysteresis shifts the effective switching point and can delay the edge.
- Verify that the induced timing shift stays within the allowed Δt and φ budgets.
- If the budget is tight, improve slope/noise first (front-end/filtering) before increasing VHYS.
Compute VTH+ / VTH−: use real VOH/VOL and the resistor ratios
External hysteresis is defined by how the input node is pulled by Vin, Vref, and the output state (VOH or VOL) through resistor ratios. Use actual output swing values (especially with open-drain pull-ups), not ideal rails.
Parameter checklist for calculation
- VOH / VOL (real output swing under load)
- Vref (and its noise/TC if it is a precision threshold)
- Rin, Rref, Rfb (ratio defines VTH+ / VTH−)
- Rsource (front-end Thevenin resistance into the node)
Engineering workflow
- Pick VHYS from noise(pk) and the phase budget.
- Choose the network form (Rin/Rref + Rfb) and compute VTH+ and VTH−.
- Back-solve Rfb to hit the target VHYS.
- Re-check drift (bias/leakage × Rsource) before committing.
Avoid threshold drift: bias/leakage × source impedance dominates
What moves thresholds in the field
- Input bias current and input protection leakage (temperature dependent).
- Board leakage from humidity/contamination at high-impedance nodes.
- Rsource from dividers/series resistors/filters that magnifies small currents into Vth shift.
Drift rule
Vshift ≈ Ierror × Rsource
Reduce Rsource, control leakage paths, and validate across temperature/humidity if phase bias must stay tight.
Diagram: hysteresis transfer + feedback network (VTH+ / VTH− / VHYS)
Treat VTH+ and VTH− as measured quantities: include output swing (VOH/VOL), leakage paths, and source impedance in the threshold budget before locking VHYS.
Timing error budget: overdrive, propagation delay, and edge jitter → phase error
Convert every uncertainty into time error first, then map time error into phase error. The most common failures come from small overdrive, shallow crossing slope, and delay variation that is not constant across conditions.
Budget map (what counts as timing error)
Noise → time jitter
Input noise and internal noise become timing jitter through the crossing slope (dv/dt). Lower dv/dt near the crossing increases jitter sensitivity.
Delay variation
Propagation delay changes with overdrive, supply, temperature, and input common-mode. Small overdrive often causes larger and less stable delay.
Filter phase shift
Analog conditioning that reduces noise can also add time shift around the crossing. Treat filter delay as part of the phase budget, not a free improvement.
Overdrive controls propagation delay (and its stability)
- Near a true crossing, overdrive is small by definition, so delay can inflate and vary more than datasheet “typical” values suggest.
- Delay vs overdrive matters more than a single delay number. Use the curve/conditions to understand the worst-case edge timing.
- Engineering action: improve crossing slope and reduce noise so the edge crosses decisively; then verify delay variation across temperature and supply.
Edge jitter: noise divided by slope (dv/dt)
Improve slope
- Avoid excessive filtering that flattens the crossing region.
- Reduce unintentional source impedance that slows the edge.
- Prevent clamp behavior from “pinching” the waveform near the threshold.
Reduce noise
- Use filtering and shielding to suppress HF pickup and switching bursts.
- Keep comparator reference and return paths quiet and local.
- Use hysteresis and blanking to prevent extra toggles, then verify phase bias stays within budget.
Map time error (ns/µs) to phase error (°)
50/60 Hz mains phase
- Period: 20 ms @ 50 Hz, 16.67 ms @ 60 Hz.
- Use φ ≈ 360° · Δt / T to translate a timing budget into degrees.
- Focus on systematic bias (delay shift) and repeatability (jitter) separately.
Higher-frequency phase detection
- Prefer Δt/T normalization to reduce sensitivity to frequency drift.
- Timer resolution and input synchronization often dominate the floor.
- Windowing and edge selection can reduce false captures without changing the physics of dv/dt.
Diagram: conceptual timing budget waterfall (Δt → φ)
Use a single timing budget language: separate random jitter from systematic delay shift, then map total Δt into phase error using the operating period.
Phase detection topologies: dual zero-cross, pulse-width, and time-interval capture
Phase detection is implemented by turning edges into timestamps. Choose the topology that matches the signal conditions, timer limits, and required robustness against chatter and frequency drift.
Topology menu (what to build)
Dual zero-cross timestamps (Vzc & Izc)
- Capture tV and tI, compute Δt = tI − tV.
- Best when both channels provide clean edges with controlled hysteresis/blanking.
- Failure mode: chatter or slow edges produce inconsistent timestamps.
Pulse-width phase (edge-to-edge duty)
- Convert phase into a measurable pulse width between selected edges.
- Simple measurement path, but sensitive to waveform symmetry and edge conditioning.
- Best when edges are already stable and timing is referenced to the same period.
Time-interval capture (windowed)
- Use a window to accept only the intended edge in each half-cycle.
- Pairs naturally with debouncing/blanking to reject extra toggles.
- Most scalable path when robustness is more important than minimal hardware.
Normalize by period: use Δt/T to reduce sensitivity to frequency drift
- When frequency changes, the same phase angle corresponds to a different absolute Δt.
- Using Δt/T keeps the phase estimate stable across cycle-to-cycle period drift.
- Measure T from the same capture stream so normalization shares the same timing reference.
Timer capture checklist (what must be true)
- Resolution: timer tick must be comfortably smaller than the target jitter.
- Input sync: asynchronous edges need a defined synchronization path to avoid extra uncertainty.
- Deglitch: hardware filtering or a blanking window to reject chatter/double edges.
- Edge selection: capture only rising or falling edges consistently per channel.
- Latency safety: ensure capture storage/ISR cannot drop edges under worst-case rate.
Common traps (why Δt looks random)
- Slow rise edges (e.g., open-drain with weak pull-up) increase capture jitter and move timestamps.
- Multiple toggles near crossing poison Δt unless hysteresis and hold-off are enforced.
- Small overdrive inflates delay variation; improving slope/noise often helps more than increasing speed grade.
Diagram: MCU timer capture flow (tV, tI, Δt) with deglitch/blanking
Ensure deglitch/blanking happens before timestamps are accepted; otherwise extra toggles will dominate Δt and hide the true phase relationship.
Distorted waveforms: harmonics, dead zones, and when zero-cross is not the best reference
Zero-cross assumes a single, steep crossing. Harmonics, notches, and flat regions change dv/dt and can create multiple candidate crossings, which inflates jitter and causes phase bias or double-counting.
What distortion breaks in practice
Harmonics near the crossing
- dv/dt varies cycle-to-cycle, so the same noise level produces different time jitter.
- Systematic phase bias can appear because the effective crossing point shifts with waveform shape.
Notches and flat regions (dead zones)
- Multiple candidate crossings appear around 0 V, enabling double-trigger or random edge selection.
- Small overdrive and shallow slope amplify delay variation and jitter sensitivity.
When zero-cross should not be the reference
- More than one plausible crossing exists within the expected timing window.
- dv/dt collapses near the crossing due to clamping, notch, or load-induced flattening.
- False triggers cluster around the crossing even after hysteresis and blanking are applied.
Engineering strategies (no heavy algorithms)
Use fixed-threshold crossing (±Vth)
Select a threshold where the waveform is steep and single-valued. This creates a stable reference edge even if 0 V is ambiguous.
Band-limit before edge detection
Remove switching bursts and high-frequency pickup that create extra crossings. Treat filter phase shift as part of the timing budget.
Choose a more stable reference edge
Use one edge per half-cycle with a window/blanking rule. If one half-cycle is cleaner, measure only that half-cycle consistently.
Quick field checklist (fast diagnosis)
- Is there a notch/flat region around 0 V? → prioritize fixed-threshold crossing.
- Does dv/dt near the crossing vary strongly over time? → prioritize band-limiting and windowing.
- Do extra edges appear mainly on one half-cycle? → capture only the cleaner half-cycle.
- Is the measured phase bias stable after switching references? → stable bias is calibratable; unstable bias indicates noise/overdrive issues.
Diagram: distorted-waveform zero-cross traps (multiple crossings) vs threshold crossing
When the waveform is multi-valued near 0 V, switching to a fixed threshold where the slope is steep can stabilize edge timing and eliminate double-counting.
Verification: how to measure false triggers, jitter, and phase error on the bench
Verification makes edge timing repeatable and transferable to production. Measure false triggers, timestamp jitter, and phase error with a defined bench setup and a consistent statistics schema.
KPI definitions (what to report)
False trigger rate
Report N_false / N_cycles (convert to ppm or events/min if needed). Use a fixed expected edge count per cycle.
Jitter
Report RMS plus p95/p99 from a timestamp distribution. Separate random jitter from systematic phase bias.
Phase error
Use a known reference phase shift, then report bias (mean) and repeatability (std) for φ error under stated conditions.
Bench setup: make conditions explicit and repeatable
- Use a controlled source (or isolated mains interface) and define amplitude, frequency, and noise injection conditions.
- Capture both the analog waveform and the digital edge output to correlate false triggers with waveform features.
- Record configuration parameters (threshold, hysteresis, blanking, filter settings, timer tick) alongside the statistics.
False trigger measurement (clean counting rule)
- Define the expected number of valid edges per cycle: N_expected.
- Count cycles N_cycles and observed edges N_edges over a fixed observation window.
- Compute N_false = N_edges − (N_expected · N_cycles), then report false_rate = N_false / N_cycles.
- Keep windowing/blanking rules fixed during the count; otherwise results are not comparable.
Jitter measurement (scope vs MCU histogram)
Oscilloscope
- Measure time interval statistics of the edge relative to a reference marker.
- Quickly reveals whether noise bursts or ringing cause multi-toggles.
MCU timestamps
- Capture t[k] and build a histogram of Δt[k] or edge-to-edge timing.
- Report RMS and p95/p99, plus bin width and sample count for traceability.
Phase error measurement and minimal data schema
Known phase reference
- Apply a known φ_ref (source offset or a simple phase-shift network).
- Compute φ_err = φ_meas − φ_ref and report bias (mean) and std.
- Repeat across amplitude, frequency, and noise conditions used in the timing budget.
Minimal schema (must log)
f, Vamp, VDD, Temp, Vth, VHYS, blanking_us, filter_cfg, timer_tick, N_cycles, N_false, false_rate_ppm, jitter_rms, jitter_p95, phase_bias_deg, phase_std_deg
Diagram: bench verification rack (source → DUT → scope/logic → stats)
Log conditions and statistics together so results can be reproduced across benches and reused for production screening.
Engineering checklist: layout, grounding, EMC, and protection
Reliable zero-cross and phase edges depend on short return paths, symmetric sensing, and controlled clamp current loops. Use the checklist below as a design review and production readiness gate.
A) Input loop (symmetry, short loops, device order)
Do
- Route comparator inputs as geometrically symmetric traces (length, vias, reference plane).
- Keep the sensing loop small: series-R + RC close to the comparator input pins.
- Use a fixed protection order: input → limit-R → clamp/TVS → RC → comparator.
Don’t
- Do not place clamps so their return current crosses the input/reference area.
- Do not let input paths cross plane splits or long detours that force return current to loop around.
- Do not hide large source impedance in long traces; it converts bias/leakage into threshold shift.
B) Ground and reference (ground bounce and return-path control)
- Keep comparator reference and its return path local so the threshold does not move with digital edge currents.
- Prevent digital return current from flowing under comparator inputs, hysteresis networks, or reference nodes.
- Use a defined tie strategy (single-point or controlled bridge) so high current paths stay away from sensitive nodes.
C) EMI and protection (RC, series-R, shielding, clamp loops)
RC and series-R
Use RC/series-R to suppress bursts and limit input current. Treat added delay and phase shift as part of the timing budget.
TVS / clamp return path
Protection is defined by the current loop. Clamp current must return through a short loop that avoids comparator inputs and reference nodes.
Shielding and cable entry
Terminate shields and surge paths near the entry so cable-borne energy does not propagate across the board and corrupt the crossing region.
D) Production readiness (threshold drift and leakage screening)
- Screen for threshold drift caused by bias × source-R, clamp leakage, and board contamination (humidity/flux residues).
- Use a controlled ramp or DAC sweep to verify VTH+/VTH− stays within the expected window across temperature and supply corners.
- Verify open-drain pull-up domains (if used) so rise-time variation does not become capture jitter variation across units.
Review checklist (copy-and-check)
- Comparator inputs routed symmetrically (length/vias/plane).
- RC and series-R placed next to comparator pins.
- Clamp/TVS current loop is short and does not cross input/reference.
- No plane splits under the input loop or reference path.
- Digital return paths do not run under the crossing network.
- Reference node decoupling is local and return is defined.
- Shield/cable entry returns are handled at the entry region.
- Test pads exist for VTH+/VTH− sweep and edge capture debug.
- Pull-up domain and rise-time are controlled (open-drain cases).
- Leakage/contamination sensitivity is screened (humidity / residues).
Diagram: layout Do/Don’t (return-path and clamp-loop control)
Keep clamp loops short and away from comparator inputs and reference nodes. Avoid plane splits and digital return paths crossing the crossing network.
Application recipes: sync-rectification, AC metering, and phase compare
These recipes focus on building trustworthy edges and timestamps. Each recipe provides a signal chain, key knobs, failure modes, and bench hooks without expanding into full power or metrology algorithms.
Recipe index (outputs and primary knobs)
Sync-rectification trigger
Output: clean gate/enable edge with blanking. Knobs: VHYS, blanking, output type.
AC metering timestamps
Output: tV, tI, Δt/T, φ. Knobs: edge selection, windowing, timing budget.
Phase compare decision
Output: |φ| < φ_limit verdict. Knobs: window, missing-edge detect, stable reference edge.
Recipe 1) Sync-rectification trigger (edge you can trust)
Signal chain
Sense → limit/clamp → comparator/Schmitt → blanking/hold-off → gate/enable edge
Key knobs
- VHYS to suppress chatter near commutation.
- Blanking window to ignore switching bursts.
- Push-pull outputs for crisp capture; open-drain needs controlled pull-up.
Bench hooks
Report false trigger rate per cycle, edge jitter (RMS/p99), and bias shift under load and switching-frequency sweeps.
Recipe 2) AC metering timestamps (tV, tI, Δt/T → φ)
Signal chain
Vzc & Izc → windowed capture → tV, tI, Δt, T → Δt/T and φ
Key knobs
- Use Δt/T normalization to reduce frequency-drift sensitivity.
- Choose a stable edge (single edge or single half-cycle) when distortion is asymmetric.
- Account for filter delay as a phase-budget term, not an afterthought.
Bench hooks
Verify phase bias and repeatability using a known φ reference (source offset or a simple phase-shift network).
Recipe 3) Phase compare decision (|φ| < φ_limit)
Signal chain
Edge A & Edge B → deglitch/window → capture → Δt/T → compare to φ_limit
Key knobs
- Windowing to accept only the intended edge region per half-cycle.
- Missing-edge detection to avoid stale phase decisions.
- Use fixed-threshold crossing when 0 V is ambiguous due to notches or dead zones.
Bench hooks
Sweep amplitude and injected noise to confirm the decision boundary stays stable and does not flip due to chatter or distortion.
Diagram: three application lanes (recipes) in one view
Keep the lanes consistent: edges are conditioned first, timestamps are captured second, and decisions are made last using windowing and defined limits.
IC selection logic: key specs → risk mapping → ask template
Select parts by edge integrity outcomes (false triggers, jitter, and phase bias), not by a generic comparator family list. Use the workflow below to translate requirements into datasheet fields, then into risks, and finally into supplier questions and starting-point part numbers.
A) Step 0 — classify the job (so the right specs dominate)
50/60 Hz zero-cross
Prioritize false triggers, threshold stability, and windowing/blanking robustness. Absolute delay is less critical than delay variation and chatter immunity.
Phase measurement (Δt/T → φ)
Prioritize time jitter and delay consistency across overdrive, temperature, and supply. Treat rise-time (OD pull-up) as part of capture jitter.
Small overdrive / distorted crossings
Propagation delay vs overdrive and input bias/leakage dominate. Consider fixed-threshold crossing and stronger hysteresis/windowing to avoid multi-cross selection.
B) Key specs (only the fields that move edge timing and correctness)
Propagation delay vs overdrive
Small overdrive usually increases delay and variability. Delay variation becomes phase bias and apparent jitter.
Input offset & drift
Offset sets absolute threshold error; drift turns into temperature-dependent phase bias (especially for fixed-threshold crossing).
Input bias current / leakage (vs temp)
Bias/leakage × source impedance becomes threshold shift. This is a major production drift driver under humidity/contamination.
Hysteresis (built-in or external)
Too small causes chatter and double-counting; too large shifts timing systematically. Size it from noise pk and the allowed phase error.
Output type & edge rate (OD vs push-pull)
Open-drain rise-time depends on pull-up and input capacitance; it can dominate capture jitter. Push-pull reduces rise-time variability.
VICR and near-rail behavior
Crossing near rails can show crossover behavior or unexpected threshold movement. Ensure the crossing region stays within a well-behaved VICR range.
Input clamp/ESD behavior
Clamp dynamics and allowable current matter when pairing with external protection. The clamp current loop must not corrupt the threshold reference.
C) Risk mapping (spec → failure mode → symptom → mitigation)
Delay depends strongly on overdrive
- Symptom: measured φ bias changes with amplitude or filtering.
- Mitigation: increase effective overdrive, move to a stable threshold crossing, or choose a part with flatter delay vs overdrive.
Bias/leakage × source-R shifts threshold
- Symptom: threshold drifts after warm-up, humidity, or contamination; false triggers increase.
- Mitigation: reduce source impedance, select lower leakage parts, and add production screening via VTH sweep.
Open-drain pull-up not defined
- Symptom: jitter distribution widens across boards or VDD domains due to rise-time variation.
- Mitigation: lock pull-up R, define the pull-up rail, control input capacitance, or switch to push-pull.
Hysteresis too small (chatter)
- Symptom: double edges around the crossing; intermittent double-count.
- Mitigation: set VHYS from measured noise pk and add blanking/window rules; verify with false trigger statistics.
Near-rail VICR anomalies
- Symptom: unstable crossings near 0 V or near supply rails; behavior changes with supply ripple.
- Mitigation: shift the crossing region into a well-behaved VICR range; avoid operation at crossover points.
D) Ask template (supplier/FAE questions that prevent wrong assumptions)
Copy/paste request
- Please provide propagation delay (max and distribution) at multiple overdrive points and temperatures (not only typical).
- Please provide input bias/leakage max vs temperature and the test conditions (humidity/contamination sensitivity if available).
- Please confirm hysteresis min/typ/max and its temperature dependence (or recommended external hysteresis network range).
- For open-drain outputs, provide recommended pull-up range and rise-time examples versus CL and Rpull-up.
- Please clarify VICR behavior near rails and any crossover regions that can affect thresholds under overdrive.
- Please clarify input clamp behavior and allowable clamp current when paired with external protection components.
- Please suggest a production-friendly threshold verification method (VTH+/VTH− sweep) and a jitter/false-trigger reporting method.
E) Reference examples (specific part numbers; starting points only)
These part numbers are provided to speed up datasheet lookup and bench verification. Final selection must be driven by the spec-and-risk workflow above, including worst-case conditions and the same pull-up/cable environment used in the target system.
Low-power / wake-up / 50–60 Hz crossings
TI TLV3691, TLV3692 · TI TLV3701, TLV3702 · Microchip MCP6541, MCP6542 · ADI/Linear LTC1540
Dual / window / wired-OR friendly (OD style)
TI LM393, LM2903 · TI LMV331, LMV393 · TI TLV1701, TLV1702
High-speed edges (phase compare and narrow windows)
TI TLV3501 · TI LMH7220 · ADI ADCMP600, ADCMP601
Schmitt-trigger buffers (slow ramps and noisy lines)
TI SN74LVC1G17, SN74LVC2G17 · TI SN74AUP1G17 · Nexperia/onsemi 74HC14, 74LVC14A
Diagram: selection flow (requirements → risks → part buckets)
Use part buckets only as lookup shortcuts. Lock the operating conditions (overdrive, pull-up, CL, and temperature) and validate false triggers, jitter, and phase bias with the same measurement schema used in verification.
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FAQs: zero-cross and phase edges you can trust
These FAQs close common long-tail issues without expanding the main text: false triggers, edge jitter, phase bias, pull-up effects, hysteresis sizing, and bench/production verification.
Why does the zero-cross output double-count or toggle multiple times near the crossing?
Symptom: Two or more edges appear around one expected crossing; phase timestamps jump sporadically.
Likely cause: Noise + low dv/dt near crossing, insufficient hysteresis, or ringing that re-crosses the threshold.
Check: Count edges per cycle (N_edges / N_cycles) and zoom the crossing region to confirm re-crossing/ringing.
Fix: Increase VHYS, add a short blanking/hold-off window, then adjust RC only after hysteresis/windowing is stable.
Guardband: Set VHYS above measured noise peak at the input (include worst-case EMI) and ensure blanking covers the ringing window.
With slow ramps, why does power increase—transition-region shoot-through or external leakage?
Symptom: Supply current rises during slow crossings; behavior worsens with humidity or contamination.
Likely cause: CMOS/Schmitt inputs linger in the transition region (internal shoot-through), or board leakage biases the input near threshold.
Check: Compare current with a fast-edge stimulus versus slow ramp; repeat after cleaning or under humidity soak to reveal leakage sensitivity.
Fix: Use a comparator with defined hysteresis/windowing, reduce source impedance, and add a buffer if the source cannot drive the input cleanly.
Guardband: Validate across temperature and a “worst” ramp rate; leakage-driven shifts must stay below the hysteresis window margin.
How should an open-drain pull-up be chosen to save power without adding capture jitter?
Symptom: Rise-time varies across boards; timestamp jitter increases as wiring/capacitance changes.
Likely cause: Open-drain rise-time is set by Rpull-up × CL; slow edges increase time uncertainty at the input threshold of the timer/receiver.
Check: Measure rise-time at the receiving pin (not only at the comparator pin) and compare jitter histograms versus different pull-ups and cable/CL.
Fix: Define the pull-up rail and Rpull-up, minimize CL, or switch to push-pull output if edge-rate variability dominates the jitter budget.
Guardband: Ensure rise-time is fast compared to the deglitch/window rule and timer synchronization path; lock R and CL for production repeatability.
RC filtering reduced false triggers, but phase bias increased—how should the trade-off be handled?
Symptom: Cleaner edges but a consistent phase offset appears after adding more filtering.
Likely cause: Filtering reduces noise yet introduces group delay/phase shift that becomes systematic phase bias.
Check: Measure phase bias before/after filtering using a known reference phase; quantify the added delay and its variation over temperature.
Fix: Treat filter delay as a budget term; prefer hysteresis + blanking for chatter control before making the filter heavier.
Guardband: Keep delay variation (not only average delay) within the allowed phase error across overdrive, temperature, and supply ripple.
Why does measured phase drift with input amplitude even when the frequency is stable?
Symptom: φ changes when amplitude changes; Δt mean shifts and Δt spread widens at low amplitude.
Likely cause: Propagation delay and delay variation depend on overdrive; small overdrive increases delay and sensitivity to noise.
Check: Sweep amplitude and record Δt mean and p99 spread per amplitude bin; correlate drift with overdrive region.
Fix: Increase effective overdrive, choose a more stable threshold crossing, or pick a comparator with flatter delay vs overdrive.
Guardband: Specify a minimum overdrive at the comparator input under worst-case attenuation and distortion.
Distorted waveforms (harmonics/notches): when is “0 V crossing” no longer a stable reference?
Symptom: Multiple candidate crossings occur, or jitter spikes near a notch/flat region; phase becomes inconsistent.
Likely cause: Harmonics and dead zones change dv/dt near crossing; notches can create ambiguous or repeated crossings.
Check: Overlay many cycles and mark all threshold intersections; identify whether a single crossing is consistently dominant.
Fix: Use fixed-threshold crossing, band-limit the signal, select a more stable edge/half-cycle, and enforce windowed capture.
Guardband: The chosen reference edge must remain unique within the capture window across load and distortion extremes.
How can input bias/leakage move the threshold, and which two conditions should be checked first?
Symptom: Threshold shifts after warm-up or humidity exposure; false triggers increase without an obvious noise change.
Likely cause: Input bias/leakage current times source impedance shifts the effective threshold (Bias × R → Vth shift).
Check: First check source impedance at the comparator pin and leakage vs temperature/humidity (board residues and clamp leakage included).
Fix: Reduce divider/source resistance, add buffering, choose lower leakage parts, and include a threshold sweep in production tests.
Guardband: Worst-case Bias×R shift must stay comfortably inside the hysteresis window margin across temperature and contamination extremes.
Why does a Schmitt trigger look “most stable” but still miss phase-accuracy targets?
Symptom: Clean digital edges but a consistent phase bias or temperature drift remains.
Likely cause: Schmitt thresholds are fixed (and can vary/drift) so timing is not independently controllable; hysteresis can introduce systematic timing offset.
Check: Measure threshold behavior across temperature and supply; compare phase bias versus a comparator with programmable hysteresis.
Fix: Use a comparator plus external hysteresis/threshold control when phase bias and drift must be minimized and characterized.
Guardband: Threshold variation and drift must stay within the phase error budget; do not assume “stable edges” imply “accurate phase.”
How should blanking/hold-off be set to avoid second crossings from ringing?
Symptom: A clean first edge is followed by one or more extra edges shortly after.
Likely cause: Input ringing or switching bursts re-cross the threshold after the intended event.
Check: Measure the ringing duration and frequency content around the crossing; verify extra edges align with the ringing envelope.
Fix: Set blanking slightly longer than the measured ringing window; combine with adequate hysteresis to prevent small re-crossings.
Guardband: Blanking must cover worst-case ringing across temperature, supply, and load states—validate with edge-count statistics per cycle.
Timer capture jitter is high—how to separate analog edge issues from digital synchronization issues?
Symptom: Jitter histogram is wide or has multi-modal clusters; changes with firmware settings or pin routing.
Likely cause: Slow/variable input edges, open-drain pull-up variability, digital input synchronizers, or ground-bounce on the capture pin.
Check: Probe both comparator output and MCU pin simultaneously; compare jitter at each point and toggle sync/deglitch options to see which dominates.
Fix: Improve edge rate (push-pull or defined pull-up), enable appropriate deglitch/windowing, and fix return paths/grounding near the capture pin.
Guardband: The measured jitter at the MCU pin must meet the phase error budget with margin under worst-case CL and switching noise.
How can false triggers, jitter, and phase error be measured in a repeatable bench and production-friendly way?
Symptom: Results differ between engineers or setups; “works on the bench” but fails in the field.
Likely cause: Missing a consistent measurement schema (stimulus, pull-up, CL, window rules, and reporting metrics).
Check: Use a fixed schema: false trigger rate = N_false/N_cycles, jitter = RMS and p99 from timestamps, phase = φ_bias and σφ from Δt/T.
Fix: Lock stimulus conditions (amplitude, distortion, EMI injection, pull-up/CL) and record firmware windowing rules with every dataset.
Guardband: Require margin at p99 jitter and worst-case phase bias across temperature and supply extremes, not only typical.
Which datasheet specs most often look good but fail on the board for zero-cross/phase capture?
Symptom: Bench edges look fine under one condition, but drift or jitter appears under real wiring, temperature, or EMI.
Likely cause: “Typical-only” delay, unspecified overdrive points, undefined OD pull-up and CL, or near-rail VICR behavior not represented in the lab setup.
Check: Re-run tests at minimum overdrive, worst-case temperature, worst-case CL, and the real pull-up rail and resistor used in the system.
Fix: Demand max/distribution data versus overdrive and temperature, define pull-up/CL explicitly, and avoid operating near VICR crossover regions.
Guardband: Use worst-case conditions as the acceptance gate: p99 jitter, φ_bias, and N_false/N_cycles must pass with margin.
