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High-Z / Electrochemistry INAs for pH & Ion Sensors

High-Z / Electrochemistry INAs for pH & Ion Sensors

← Back to:Instrumentation Amplifiers (INA)

High-Z electrochem INA design is won or lost at the input: the front end must not steal charge or create leakage-driven offsets. Start by setting a total leakage/bias budget, then enforce it with driven guarding, humidity-proof layout/cleaning, and protection that is placed and verified so it never becomes the dominant error source.

Center idea: why High-Z INAs are different

In High-Z electrochem front ends, accuracy is not limited by gain—it is limited by unwanted current. With 10 MΩ to 1 GΩ sources, picoamp-level bias and leakage turn into large voltage errors and long recovery tails.

What “High-Z INA” really means

The front end must not steal charge, must not leak through protection or PCB surfaces, and must keep the sensitive node clean so the protection network does not become the dominant error source.

The 3 enemies (design must budget and control them)

1) Input bias current (Ib)
Any sustained input current becomes an error voltage through the sensor source resistance and also shapes settling after overload or plug/unplug events.
2) Leakage (components + PCB + connectors)
TVS/ESD devices, clamps, flux residue, humidity films, and connector insulation can create leakage paths that dwarf the INA’s own Ib.
3) Surface contamination (the silent resistor network)
Residues and moisture create time-varying high-resistance paths. The reading drifts with humidity, handling, and cable motion even when the sensor is stable.

Success criteria (pass/fail, not opinions)

  • Stable zero: within the defined time window, the output drift stays inside the system error budget (use a project-specific limit).
  • Touch/humidity immunity: cable touch, motion, and humidity steps do not cause persistent shifts; transients settle back within a defined time and tolerance.
  • Protection without regret: after adding ESD/OVP protection, leakage and recovery behavior still meet budget across temperature and humidity corners.
High-Z electrochem error dominance map Block diagram showing pH/ISE sensor, a sensitive high-impedance node, INA input bias and leakage paths from ESD/TVS, PCB surface, and connector/cable, and how total leakage creates output error through source resistance. pH / ISE Sensor Rsource: 10M–1GΩ High-Z Node INA (FET/CMOS) pA-class Ib target Output / ADC Interface Verr ≈ Itotal × Rsource Ib ESD / TVS PCB Surface Connector / Cable Leakage paths add up → Itotal Possible dominant contributors (no numbers; budget decides) Ib ESD/TVS PCB Connector/Cable

Sensor/source model that sets the rules (pH / ISE)

A pH/ISE probe behaves like a high-resistance source with electrode capacitance and slow polarization dynamics. That combination makes the input node extremely sensitive to charge injection, leakage, and sampling transients.

Engineering model (useful, not academic)

  • Very high source resistance: typically tens of MΩ up to GΩ class (depends on probe chemistry, temperature, aging, and electrolyte condition).
  • Electrode capacitance and cable capacitance: pF–nF class equivalents are common; they form long time constants with the source resistance.
  • Slow dynamics: after overload, unplug/plug, or protection conduction, the node may recover slowly and look like “drift.”

Why “false drift” happens (cause → effect chain)

1) Charge injection occurs
ESD/TVS leakage, clamp conduction, probing, or ADC sampling transients inject or remove charge at the High-Z node.
2) The node cannot “heal” quickly
The time constant is dominated by Rsource × (Celectrode + Cin + parasitics), so recovery can be slow and temperature/humidity dependent.
3) The output looks like sensor drift
The INA amplifies the node voltage, so small injected charge or leakage becomes a visible output shift with a long tail.

Practical checks (separate sensor issues from front-end issues)

  • Humidity step test: change humidity (or breath/cover exposure) and observe whether the baseline shifts or shows long-tail recovery (front-end leakage signature).
  • Cable motion test: gently move the cable and check for correlated steps/bursts (triboelectric/handling + High-Z sensitivity signature).
  • Overload/recovery test: briefly force a known node disturbance and measure recovery time; excessive tails often indicate Rsource×C dominance plus leakage paths.
pH/ISE electrode equivalent model and error injection points Simplified Thevenin model with large source resistance, electrode capacitance, INA input capacitance, and leakage paths representing humidity/contamination and ESD/TVS leakage, with arrows for input bias and leakage currents. Electrode Source Velectrode Rsource (very high) High-Z Node INA Input Cin + bias Celectrode Cin Humidity / Contamination PCB surface leakage ESD / TVS Network Device leakage Ileak Ileak Ib High Rsource + (Celectrode + Cin) turns small currents into large error and long recovery.

Architecture choices for picoamp inputs (what matters)

For High-Z electrochem channels, the winning architecture is the one that controls total unwanted current and charge injection at the sensitive node. Numbers like “low offset” only help after the input current behavior is predictable across temperature and humidity.

What matters vs what does not

Primary: input current behavior
Max input bias across temperature, current noise into high Rsource, and how the input node recovers after clamp events decide baseline error and “false drift.”
Secondary: overload/recovery and injection
Input switching, modulation, protection conduction, and sampling disturbances can inject charge. With long time constants, small injection becomes long tails.
Do not over-weight: a single “offset” line
Typical offset looks attractive, but High-Z accuracy is usually dominated by leakage and bias current behavior under real wiring, humidity films, and protection leakage.

Three practical paths (A/B/C) and how to choose

Path A
FET/CMOS-input INA
  • Best at: lowest Ib potential; simplest error model when guarding and cleanliness are controlled.
  • Watch-outs: external leakage (TVS/PCB/connector) can dominate and hide the benefit of a low-Ib input stage.
  • Choose when: High-Z node can be guarded/kept clean and the system is sensitive to humidity and handling drift.
  • Validation: humidity step + cable motion + overload recovery; confirm the baseline shift stays inside budget.
Path B
Zero-drift / chopper INA
  • Best at: extremely low drift and strong low-frequency stability when ripple artifacts are managed.
  • Watch-outs: chopping ripple and input switching can create visible low-frequency artifacts with large time constants.
  • Choose when: drift dominates and the system can filter/average ripple without breaking recovery time requirements.
  • Validation: measure ripple/steps at the output, plus overload recovery after clamp conduction and plug/unplug.
Path C
High-Z buffer + differential ADC
  • Best at: isolating the High-Z node with a buffer, keeping the front end simple and predictable.
  • Watch-outs: ADC sampling kickback and settling can dominate unless the buffer/RC interface is designed for it.
  • Choose when: differential sampling is already required and the system can allocate design effort to the ADC interface.
  • Validation: verify step settling under worst ADC sampling rate and input range; ensure no charge is pushed back into the High-Z node.

Note: ADC drive and anti-alias details belong to the “ADC drive & filtering” section; this page only sets the decision rule and validation targets.

Architecture selection tree for picoamp High-Z inputs Decision tree that starts from a high-impedance electrochem source and branches into three practical paths: FET/CMOS-input INA, zero-drift/chopper INA, and high-Z buffer plus differential ADC, highlighting what to verify for each. High-Z Electrochem Source Rsource: 10M–1GΩ Dominant Risk? Leakage · Drift · Interface Path A FET / CMOS INA Best: Low Ib Risk: Leakage Needs: Guard Verify: Humidity Path B Zero-drift INA Best: Low drift Risk: Ripple Risk: Recovery Verify: Steps Path C Buffer + Diff ADC Best: Simple Risk: Kickback Needs: Riso/RC Verify: Settling Choose the path that controls Itotal and injection; then validate humidity, motion, and recovery.

Bias current & leakage → error budgeting (non-negotiable math)

In High-Z systems, voltage error is the consequence of unwanted current flowing through a large source resistance. Budget the total leakage first, then allocate it to the INA, protection network, PCB surface, and connectors.

The equation that drives everything

Verror ≈ Itotal_leak × Rsource
When Rsource is extremely high, picoamp-class current terms convert into visible voltage shifts and long recovery tails.

Itotal_leak is not one thing (allocate and control)

INA input current (Ib)
Use worst-case across temperature; verify that the bias return path does not force extra leakage at the sensitive node.
Protection leakage (TVS/ESD/clamps)
Place high-leak parts away from the High-Z node; prefer staged protection and parts with verified leakage over temperature and humidity.
PCB surface leakage (humidity/contamination)
Guard rings and driven guards reduce the voltage across leakage films; cleaning, bake, and process controls prevent time-varying resistive networks.
Connector / cable leakage
Insulation quality, sealing, and handling strongly affect leakage; cable motion and moisture can create repeatable “steps” that mimic drift.

Magnitude check (illustration, not a spec)

A picoamp-class leakage current through a 100 MΩ source can create an offset on the order of 0.1 V. If the source resistance rises by one decade, the error rises by one decade as well.

Temperature and humidity corners often increase leakage dramatically; budgets must include environmental and process corners, not only “room-dry” behavior.

Budget workflow (from requirement → allocation → verification)

  1. Define allowable Verror from the system accuracy target (include sensor tolerance and calibration strategy).
  2. Compute Itotal_leak limit: Itotal_leak ≤ Verror / Rsource (use worst-case Rsource).
  3. Allocate the leakage budget to four buckets (INA, protection, PCB surface, connector/cable) and keep guardband for production spread.
  4. Verify with humidity steps, cable motion, and overload recovery tests; pass when baseline and tails remain within the budget.
Leakage budget bucket diagram for High-Z electrochem channels Bucket diagram showing total allowable error as a bucket and four leakage contributors as drain pipes: INA bias, protection leakage, PCB surface leakage, and connector/cable leakage, each with control levers like guarding and cleaning. Total allowable error Verror budget Mapped from: I total × Rsource Ib Protect PCB Cable Leakage contributors Allocate + guardband INA bias (Ib) FET Temp Protection leakage Staged Low-L PCB surface leakage Guard Clean Connector / cable Seal Cable allocate Budget Itotal first, then design protection/layout/process to keep every drain inside the allocation.

Noise, 1/f, and “slow dynamics” with high source impedance

With very high source impedance, input current noise multiplied by Rsource becomes input-referred voltage noise, and 1/f behavior often sets the true low-frequency resolution. A good-looking nV/√Hz line alone does not predict stable readings.

The mapping that matters (from noise specs to reading resolution)

Voltage noise (en)
Appears directly at the input. It dominates when Rsource is moderate and the front end is well-guarded.
Current noise (in) × Rsource
Converts into an equivalent input voltage noise that scales with source resistance. This term becomes the reality check for 10 MΩ–1 GΩ sources.
Low-frequency resolution: 1/f + slow drift
Below a few Hz, 1/f noise and slow dynamics can look similar. The reading can “wander” even when wideband density is low.

Why “narrower bandwidth” is not always “more stable”

  • Noise goes down, tails get longer: heavy filtering/averaging reduces wideband noise but can keep step disturbances (handling, clamp events) inside the measurement window longer.
  • Drift separation gets harder: in a very low-frequency window, 1/f and slow drift both appear as slow change; filtering alone does not identify the root cause.
  • Design target: optimize effective resolution at the system update rate, not the smallest possible analog bandwidth.

Validation hooks (measure what users see)

Windowed noise test
Compute RMS/peak-to-peak per measurement update window to obtain “reading jitter” instead of an abstract density number.
Step-and-recover
Apply a controlled disturbance and verify recovery stays outside the measurement window (no long tails contaminating updates).
Slow corner correlation
Compare baseline wander with temperature/humidity changes to separate 1/f-limited behavior from environment-driven leakage drift.
Noise to reading resolution mapping for High-Z electrochem inputs Two-part diagram: top shows qualitative noise density shapes including 1/f rise and current-noise times source resistance; bottom shows measurement windows (DC drift, 0.1–10 Hz, and update-rate window) and what dominates in each region. Noise density (shape only) frequency → noise ↑ 1/f region white region en in×Rsource Measurement windows DC / drift 0.1–10 Hz update window Low-freq: 1/f + drift dominate Wideband: density terms dominate Effective resolution depends on the chosen window

Input protection that doesn’t sabotage leakage (ESD/OVP done right)

High-Z protection is a leakage problem first. Use staged protection, keep high-leak parts away from the sensitive node, and treat every component connected to the input as part of the leakage budget—especially across hot and humid corners.

3-layer strategy (staging + placement + budget)

Layer 1: connector-side diversion (far from node)
Divert ESD/surge energy before it enters the sensitive area. Keep the high-energy path short and away from the High-Z trace.
Layer 2: on-board current limiting + RC (middle layer)
Series resistance limits fault current and reduces injection. RC can improve robustness, but R and C must be included in noise and leakage budgets.
Layer 3: pin-side clamps (closest, most cautious)
Use only if required. Any clamp near the High-Z node must have verified leakage across temperature and humidity, and must pass recovery tests after conduction.

A “low-leak” label is not enough (must be tested)

  • Corner behavior: leakage can change drastically under heat and humidity; treat it as a system parameter, not a datasheet footnote.
  • After-stress effects: ESD/EFT events can leave long recovery tails if any protection element conducts into a high time-constant node.
  • Pass criteria: baseline shift and recovery tails remain inside the leakage budget defined in the error allocation step.
Staged input protection placement for High-Z electrochem inputs Block diagram showing three protection layers: connector-side diversion (TVS/arrester), board-side series resistor and EMI capacitor, and optional pin-side clamp near the INA input with guard ring around the High-Z node. Red warning markers indicate leakage budget impact for any component touching the input. Connector Cable Layer 1 Diversion TVS / Arrester to chassis/ground Leakage Layer 2 Limit + RC Series R EMI C Leakage INA Input Area High-Z node Guard ring Clamp (optional) Layer 3 Leakage divert Any component connected to the input consumes leakage budget — verify in hot/humid corners.

PCB layout, guarding, cleaning, and humidity control (where designs fail)

In High-Z electrochem front ends, the most common failure mode is not the amplifier—it is surface leakage and humidity films turning picoamp currents into visible offsets. Guarding works by reducing the voltage across the leakage path, shrinking leakage current and the resulting error.

Guarding principle (why it works)

Leakage is driven by ΔV across the film
Moisture and residues form a resistive path. The leakage current increases with the voltage difference between the sensitive node and surrounding copper.
Driven guard reduces ΔV → reduces Ileak
A guard ring driven near the sensitive node potential collapses the electric field across the leakage film, keeping the leakage current and its drift smaller.
Key takeaway
Guarding is an error-control technique: it prevents the board from becoming the dominant “leakage device” in the measurement chain.

Layout actions (Do / Don’t checklist)

Do
  • Enclose the High-Z pad and trace with a guard ring; keep the sensitive trace short and direct.
  • Use driven guard when the node is not near ground; route the guard drive as a short, stable path.
  • Minimize vias on High-Z nodes; keep solder mask openings controlled to reduce residue traps.
  • Keep “dirty zones” and connectors away from the sensitive area; create a clear keep-out region.
Don’t
  • Do not route High-Z traces across plane splits, slots, or gaps.
  • Do not place High-Z nodes near finger-access areas or board edges where humidity films form easily.
  • Do not rely on coating to “fix” a poor guard/layout; some coatings can introduce moisture-related unpredictability.
  • Do not allow silkscreen/adhesives near the sensitive zone; residues and porous materials often absorb moisture.

Cleaning, bake, and conformal coating (when it helps, when it backfires)

Cleaning
Removes flux and ionic residues that create time-varying leakage paths. Verification requires humidity step tests before and after the process.
Bake
Drives out absorbed moisture to stabilize short-term behavior, but improvements can fade after re-exposure; re-test under controlled humidity.
Conformal coating
Can stabilize surface resistance, but edge effects, pinholes, and moisture uptake of some materials can create new leakage patterns. Guarding and cleanliness remain mandatory.

Validation hooks (pass/fail by behavior)

Humidity step
Step humidity and observe baseline shift and recovery tail. Pass when changes remain inside the allocated leakage budget.
Finger proximity
Bring a hand near the sensitive zone. Guard/layout should prevent step-like shifts and persistent drift.
Cleanliness A/B
Compare before/after cleaning or coating to confirm root cause. Stable results must hold across temperature and humidity corners.
Guard ring and driven guard top-view layout for High-Z nodes Top-view PCB diagram showing a central High-Z pad with a short sensitive trace, surrounded by a blue guard ring driven by a guard driver. Dashed leakage paths represent moisture/residue films. Red warnings mark forbidden items like plane gaps, dirty zones, and finger-touch regions. Sensitive zone High-Z pad Sensitive trace Guard ring Guard driver Driven guard Leak film Gap Dirty zone Finger zone Via Guard reduces ΔV across leakage films; cleanliness and humidity control keep leakage predictable.

Cable/connector triboelectric & motion artifacts (touching the cable changes the reading)

With high-impedance sources, cable motion can inject charge through dielectric friction and parasitic coupling. The result is often a step-like voltage change followed by a long recovery tail, not a simple “white noise” increase.

Why motion creates errors in High-Z systems

Triboelectric charge
Bending and rubbing the cable dielectric generates charge. With no low-impedance discharge path, the charge converts into a measurable voltage.
Parasitic coupling
Motion changes parasitic capacitances and leakage films, creating step injection into the input node and slow settling.
Micro-motion at connectors
Small mechanical motion can shift contact potentials and leakage paths, producing repeatable “touch artifacts” that look like drift.

Engineering countermeasures (within this page scope)

  • Use low-tribo cable and keep the cable mechanically quiet (strain relief, clamps, fixed routing).
  • Provide a controlled shield reference to reduce coupling into the inner conductor (focus: minimize injection, not EMC theory).
  • Choose connectors with better insulation and sealing; prevent moisture films that form a variable leakage path into the High-Z node.
  • Validate by repeatable motion/touch patterns; pass when motion no longer creates step-like shifts that exceed the leakage budget window.
Cable motion to charge injection paths in High-Z electrochem inputs Block diagram showing a hand bending a cable, triboelectric charge generation in the dielectric, coupling and leakage paths to the shield and inner conductor, connector micro-motion, and injection into a High-Z input node on the PCB. Countermeasure tags are placed along the corresponding paths. Hand Bend / touch Cable Inner Dielectric Shield Tribo Q Cap coupling Leak film Connector Micro-motion Motion PCB input High-Z node Guard Injection Strain relief Low-tribo cable Shield ref Seal connector Motion artifacts are step injection + long tails; fix mechanics and materials before adding heavy filtering.

Output interface: driving ADC/filters without reintroducing error

A High-Z input does not guarantee a stable system. Once an ADC is attached, sampling switches can pull charge from the INA output, creating sampling-synchronous steps and long recovery tails. The interface must confine kickback energy on the ADC side using isolation and a local charge reservoir.

What goes wrong (sampling is a pulse load)

ADC input is not static
Many ADCs present a sampling capacitor and a switch. Each sampling edge draws charge, producing step-like disturbances at the driver output.
Kickback becomes “reading error”
Sampling-synchronous spikes and settling tails can alias into the measurement window, looking like drift or instability even when the input leakage is controlled.
Goal of the interface
Keep sampling charge exchange local to the ADC side, while the INA sees a smoother, more predictable load.

Practical interface tools (isolation + local reservoir)

Riso + Cf (default workhorse)
A small series resistor isolates the INA output from sampling edges, while a capacitor near the ADC provides a local charge reservoir and reduces kickback amplitude.
Watch-outs: too much R slows settling; too much C creates long tails after disturbances.
Buffer stage (when the INA should not fight pulse loads)
A dedicated buffer can absorb sampling transients and stabilize the interface, but its offset/drift/noise must not undo the error budget achieved at the High-Z input.
Anti-alias filter (set by update window, not “as low as possible”)
For slow sensors, the filter must avoid turning disturbances into long recovery tails that bleed into the measurement window. Choose corners and damping based on step-and-settle behavior.

Validation hooks (measure the artifacts, not just RMS noise)

Sampling-synchronous spikes
Probe the INA output and ADC input node for spikes aligned to sampling events. Kickback should shrink after adding Riso/Cf near the ADC.
Step-and-settle in the update window
Apply a controlled step and confirm the output settles before the next reported update. Pass when recovery tails do not contaminate consecutive readings.
Riso/Cf sweep
Sweep isolation and reservoir values to find the tradeoff: less kickback vs faster recovery. Choose the combination that stays inside the measurement window budget.
INA output interface to ADC with kickback isolation and local reservoir Block diagram showing INA feeding an optional buffer, then a series isolation resistor and a capacitor near the ADC input. A sampling switch and capacitor at the ADC input generate kickback arrows back toward the driver. Labels highlight isolation and charge reservoir roles. INA Output Interface options Direct Buffer Buffer Riso Isolation Cf Reservoir ADC Input SW C Kickback Isolate Local charge Interface target: suppress sampling-synchronous spikes and keep settling tails outside the update window.

Application patterns (pH/ISE/ORP/conductivity) — practical front-end recipes

These patterns provide front-end skeletons and failure-focused tips for electrochem measurements. Each recipe stays within the High-Z chain: leakage control, guarding, protection, cable artifacts, and ADC interfacing—without expanding into full excitation or system tutorials.

Pattern A — pH / ISE (extreme High-Z, environment-sensitive)

Front-end recipe
Electrode → low-leak protection → guard input → High-Z INA → Riso/Cf → ADC
What usually fails
  • Surface leakage and humidity films dominate the baseline and drift.
  • Cable motion injects charge and creates step-like jumps with long tails.
  • ADC kickback aliases into readings when the output interface is not isolated.
Pass criteria
Humidity and touch tests do not create persistent baseline shifts; recovery tails stay outside the update window; sampling-synchronous spikes are suppressed at the ADC node.

Pattern B — ORP (less extreme, still leakage-limited)

Front-end recipe
Probe → low-leak protection → High-Z INA → interface isolation → ADC/DAQ
What usually fails
  • “Low-leak” protection parts drift under hot/humid corners and become a hidden offset source.
  • Connector sealing and board cleanliness decide repeatability more than amplifier specs.
Pass criteria
Baseline remains stable across humidity and handling; no repeatable “touch steps” appear; protection recovery after stress stays inside the measurement window.

Pattern C — Conductivity (measurement interface, excitation handled elsewhere)

Front-end recipe
Cell → protection + leakage control → AFE sense path → interface isolation → ADC
Scope boundary
Excitation source selection, frequency planning, and synchronous demodulation are handled elsewhere. This pattern focuses on leakage, protection, and ADC interfacing of the sense path.
Pass criteria
Sense-path baseline stays stable across humidity and stress; protection does not introduce long recovery tails; ADC interface shows no sampling-synchronous artifacts.
Electrochem front-end pattern library: pH/ISE, ORP, conductivity Three stacked mini block diagrams. Top: pH/ISE shows guard and leakage sensitivity. Middle: ORP emphasizes low-leak protection and sealing. Bottom: conductivity shows a sense path with a note that excitation is handled elsewhere. Each pattern ends at an ADC/DAQ interface. pH / ISE Electrode Low-leak Protection Guard INA ADC Leakage ORP Probe Low-leak Protection INA Interface DAQ Seal / clean Conductivity Cell Protection Leak control AFE sense ADC Excite elsewhere

Self-test, calibration, and production readiness for high-Z channels

High-impedance electrochem channels fail in production when the design cannot measure, bin, and localize leakage and charge-injection effects. Build test hooks that characterize total input leakage (IC + protection + PCB + connector/cable) and provide repeatable failure fingerprints across temperature and humidity.

A) Production-ready test hooks (design-in, not bolt-on)

Use three complementary hooks so every unit can be screened for leakage, open/short, and humidity sensitivity without touching the high-Z node directly.

Hook 1 — Known micro-current / micro-voltage injection (via giga-ohm network)
  • Measures: total leakage / bias signature at the input node (system-level).
  • How to run: switch in Rinj (100 MΩ–1 GΩ class), apply a small step, wait a defined settle window, capture ΔVout.
  • Log: Itotal_est, step linearity, recovery tail (τ).
  • Pass criteria: Itotal_est < I_budget and τ < τ_budget (budgets come from system error + update-rate targets).
Hook 2 — Open / short / leakage fault detection (fast triage)
  • Open electrode: output drifts toward a bias point; noise shape changes; recovery tail inflates.
  • Short / contamination bridge: output clamps; injection response collapses (low apparent impedance).
  • Leakage-dominated: drift slope strongly correlates with RH/touch; injection response depends on humidity state.
  • Pass criteria: all fault flags clear under a scripted stimulus set (idle, injection, cable tap, RH step).
Hook 3 — Temperature / humidity stress screen (lightweight, high value)
  • Run: one RH step (or controlled soak) + one temperature point (hot is most revealing), then re-run Hook 1.
  • Log: drift slope (dV/dt), step response delta, Itotal_est shift vs baseline.
  • Pass criteria: |ΔItotal_est| and |Δ(dV/dt)| remain within defined guardbands.

B) The minimum math that makes the test actionable

Use a production formula that converts a measured output step into an estimated total leakage/bias term. Keep it simple and consistent across fixtures.

V_error ≈ I_total_leak × R_source
I_total_leak includes: IC Ib + clamp leakage + PCB surface leakage + connector/cable leakage
I_total_est ≈ ΔVout / (G × Rinj) (after settle window)

Treat I_total_est as a system parameter to bin and trend. It will capture “hidden” leakage that component-only checks miss.

C) Minimal production data schema (what to log, what to bin)

Log only what enables triage and feedback. Keep each field measurable and comparable across stations.

Field Meaning Why it matters
SN / Lot Unit identity Enables lot correlation and drift tracking
Temp / RH Stress context Leakage is strongly environment-dependent
Offset_25C Baseline output error Separates “static offset” from “leakage drift”
Gain_25C Channel gain factor Makes injection math consistent
Itotal_est Estimated total leakage/bias Primary binning metric for high-Z validity
Drift_slope dV/dt under defined condition Highlights humidity / contamination sensitivity
Recovery_tau Return-to-steady time constant Separates slow polarization vs charge injection artifacts

Binning example (typical order): fault flags → Itotal_est → Drift_slope → Recovery_tau.

D) Diagram: injection + readback + binning loop (fixture-aware)

Keep the high-Z node protected by driven guard and measure it indirectly through a controlled injection network and a scripted readback flow.

Production injection and readback loop for high-impedance channels Block diagram showing triax connector, guarded input node, INA, ADC, MCU, and an injection network used to estimate total leakage and bin units. Connector BNC / TRX Cable High-Z input node pad + via-free trace Driven guard humidity / residue connector leakage INA/Buffer high-Z front ADC readback MCU binning Metrics Itotal / drift / τ Injection network Rinj + Relay/SW Vcal step inject readback Key idea Measure leakage indirectly
Reference examples (starting points only; verify leakage vs temperature/humidity)
Electrometer / ultra-low bias front end: ADA4530-1, LMP7721
Low-leakage switching: ADG1209, Coto 2200-2301 (reed relay)
GΩ injection resistors: CRHV1206AF1G00FMFT, HMC1206KT1G00, HVC1206Z1007JET
Low-leak clamp diode (only if required): BAV199
Fixture-class triax interface: Amphenol RF 031-2676-1 + Belden 9222
Humidity control option: HumiSeal 1B73 (process matters as much as the material)
Connector-side crowbar (keep far from node): Bourns 2038-110-SM-RPLF, Littelfuse CG75

Engineering checklist + common failure signatures (high-Z troubleshooting)

Use this section as a pre-release audit and a field triage tool. Every item is phrased as a check with a concrete verification method and a pass criterion placeholder. The fastest wins in high-Z designs come from guard, cleanliness, and fixture-aware testing.

A) Checklist (5 categories)

1) Input node & routing
  • Check: high-Z trace is short and via-free. Verify: layout review. Pass: length < L_budget; vias = 0 in high-Z segment.
  • Check: guard ring fully surrounds pad/trace. Verify: top view + continuity. Pass: no gaps adjacent to high-Z copper.
  • Check: no plane splits / slots under the node region. Verify: stackup + return path view. Pass: continuous dielectric + copper under guard region.
  • Check: solder mask strategy prevents residue bridges. Verify:Pass:
  • Check: keep-out from “touch zones” (connector handling area). Verify:Pass:
  • Check: guard is driven (not static ground). Verify:Pass:
2) Protection components
  • Check: connector-side surge/ESD shunt is placed away from the high-Z node. Verify:Pass:
  • Check:Verify:Pass:
  • Check:Verify:Pass:
  • Check:Verify:Pass:
  • Check:Verify:Pass:
  • Check:Verify:Pass:
3) Cleaning, bake, and conformal coating
  • Check:Verify:Pass:
  • Check:Verify:Pass:
  • Check:Verify:Pass:
  • Check:Verify:Pass:
  • Check:Verify:Pass:
  • Check:Verify:Pass:
4) Connector, cable, and mechanical handling
  • Check:Verify:Pass:
  • Check:Verify:Pass:
  • Check:Verify:Pass:
  • Check:Verify:Pass:
  • Check:Verify:Pass:
  • Check:Verify:Pass:
5) Test methods (repeatable reproduction + pass criteria)
  • Check:Verify:Pass:
  • Check:Verify:Pass:
  • Check:Verify:Pass:
  • Check:Verify:Pass:
  • Check:Verify:Pass:
  • Check:Verify:Pass:

B) Common failure signatures → fastest next checks

Use symptom-driven triage. Each row lists 1–2 measurable checks and the fastest corrective actions.

Symptom Quick check Likely cause Fix + pass criteria
Cable touch/move changes reading Cable tap test; compare shield termination variants Triboelectric charge injection; shield/strain relief issues Switch to lower-noise cable + strain relief; define pass: tap response ≤ step_budget
Rainy/high-RH drift increases RH step + drift_slope log; IR measurement around guard PCB surface leakage from residue/absorption; connector IR collapse Re-clean + bake; guard drive verification; pass: drift_slope ≤ D_budget
Slow drift for first 5–15 minutes after power-up Record recovery_tau; compare before/after injection step Charge absorption / polarization; leakage settling; contamination film drying Stabilize environment + cleaning; pass: τ within τ_budget under defined warm-up
Output saturates with open electrode Open/short script; injection response amplitude Missing bias path / clamp behavior; cable/connector leakage Add controlled bias/return path away from node; pass: open detection flag + bounded output
ESD/plug event → recovery becomes very slow Run injection step pre/post event; log ΔItotal_est Protection leakage shift; contamination triggered by event; clamp return injection Move crowbar to connector; re-budget leakage; pass: |ΔItotal_est| ≤ guardband
Unit-to-unit spread looks random Trend by lot and by process step; compare golden unit Process variability (cleaning, coating, handling); fixture drift Lock process + control fixture; pass: Cp/Cpk meets target on Itotal_est and drift_slope

C) Diagram: symptom → diagnostic path → fix

Follow a short branching path instead of guessing. Start with RH correlation and motion correlation to separate leakage-dominated failures from cable-charge artifacts.

High-Z failure signature diagnostic flow Flow chart mapping common symptoms to quick checks and likely root causes: leakage dominated, triboelectric dominated, or protection dominated. Drift Step jump Saturation Slow recovery RH related? RH step / IR test Motion related? Cable tap / flex After ESD/plug? ΔItotal pre/post Leakage dominated clean / guard / IR Triboelectric cable / shield / strain Protection dominated move shunt / re-budget Start with RH and motion correlation; then isolate protection leakage changes.

D) Reference parts kit (starting points; validate under your stress corners)

These examples speed up datasheet lookup and fixture planning. Selection must be driven by the leakage budget and verified under temperature and humidity.

Electrometer / ultra-low bias front end
ADA4530-1 · LMP7721
Low-leakage switching (test mode / injection routing)
ADG1209 (analog mux) · Coto 2200-2301 (reed relay)
GΩ resistors for injection / bias networks
CRHV1206AF1G00FMFT · HMC1206KT1G00 · HVC1206Z1007JET
Low-leak clamp diode (use only if required; measure leakage vs RH)
BAV199
Connector-side crowbar (keep far from the sensitive node)
Bourns 2038-110-SM-RPLF · Littelfuse CG75
Triax fixture interface (guarded cabling)
Amphenol RF 031-2676-1 · Belden 9222
Conformal coating example (process-dependent)
HumiSeal 1B73
Practical rule: every component connected to the high-Z node owns a leakage line item.
Validate leakage with temperature and humidity sweeps; do not rely on “typical” room-condition leakage numbers.

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FAQs (High-Z / Electrochemistry INA)

These FAQs only cover this page’s scope: Ib/leakage, guarding, input protection, humidity, cable touch/motion, slow recovery, ADC interface, and production test. Answers are short, actionable, and use measurable pass criteria placeholders.

Why does the pH reading drift when humidity changes?
Likely cause: PCB/connector surface leakage dominates as RH changes, creating an offset through the high source resistance.
Quick check: Run an RH step (or controlled soak) and log drift slope; measure insulation resistance around the high-Z area.
Fix: Re-clean + bake; ensure driven guard follows the input node; tighten keep-out and coating boundaries near high-Z copper.
Pass criteria: After RH step, drift slope < X mV/min and |ΔItotal_est| < Y pA (budgets set by system error/update-rate).
Touching or moving the cable changes the reading—what to check first?
Likely cause: Triboelectric charge injection and shield/strain-relief coupling into a high-impedance node.
Quick check: Perform a repeatable cable tap/flex test; A/B compare shield termination and cable types under identical conditions.
Fix: Use lower-noise cable + robust strain relief; standardize shield termination; keep the high-Z node physically away from handling zones.
Pass criteria: Defined tap/flex produces step < X mV (or < X ADC codes) and repeatability stays within ±Y.
Why does adding a TVS/ESD diode create a large offset?
Likely cause: Clamp leakage (often worse at hot/RH) creates a DC error across the sensor/source resistance.
Quick check: A/B test with clamp removed/bypassed; repeat at hot and under RH stress to see if the offset tracks environment.
Fix: Move “strong” shunt elements to the connector side; minimize parts tied to the sensitive node; re-budget leakage for every added device.
Pass criteria: With protection installed, Itotal_est < I_budget at hot/RH corners and offset shift < X mV.
How much input bias current is “too much” for a 100 MΩ / 1 GΩ source?
Likely cause: The real limit is the allowed DC error budget: V_error ≈ I_total × R_source, not “typical” datasheet Ib.
Quick check: Define V_budget; compute I_budget = V_budget / R_source; compare against measured Itotal_est under stress corners.
Fix: Split I_budget across IC + clamps + PCB + connector/cable; prioritize reducing RH-sensitive leakage first.
Pass criteria: Itotal_est < V_budget/R_source at hot/RH corners, with margin ≥ M% for aging/process spread.
Why is recovery painfully slow after an overload or unplug/plug event?
Likely cause: Charge absorption/polarization and uncontrolled discharge paths; some protection devices also shift leakage state after events.
Quick check: Log Recovery_tau before/after the event; run a small injection step and compare the tail length (same settle window).
Fix: Provide a controlled return-to-steady mechanism that does not break leakage budget; keep aggressive shunts away from the sensitive node.
Pass criteria: Post-event Recovery_tau < X s and drift returns below Y mV/min within Z minutes.
Guard ring is present but drift remains—what are the top layout mistakes?
Likely cause: Guard is not driven, not continuous, or the high-Z segment still has vias/residue/slots that create a voltage across leakage paths.
Quick check: Scope guard vs input common-mode; inspect for vias/flux residue/keep-out violations; confirm no plane splits under the node region.
Fix: Convert to driven guard; keep high-Z copper short and via-free; enforce cleaning/bake and handling controls for the high-Z region.
Pass criteria: Guard follows within X mV and RH-step drift slope improves by ≥ Y% (or falls below Z mV/min).
Why does conformal coating sometimes make leakage worse?
Likely cause: Coating absorbs moisture or traps contamination, forming a humid film that bridges high-Z surfaces.
Quick check: A/B test coated vs uncoated boards under RH soak; inspect coating edges for bubbles/voids and residue underneath.
Fix: Use coating only when stress tests prove improvement; optimize pre-clean + bake; control coating boundary to avoid bridging near the node.
Pass criteria: Under RH soak, drift slope and Itotal_est improve vs baseline by ≥ X% and IR stays ≥ Y.
Why does the output look noisy even though the sensor is “slow”?
Likely cause: Current noise × high source impedance becomes voltage noise; 1/f noise and low-frequency disturbances dominate the reading window.
Quick check: Compare noise in a defined 0.1–10 Hz window vs the update-rate window; check correlation with RH and cable motion to rule out artifacts.
Fix: Set bandwidth from the required update rate; avoid over-filtering that inflates recovery time; address leakage/motion artifacts before tuning filters.
Pass criteria: In the defined bandwidth, noise < X mV RMS (or X LSB) while Recovery_tau < Y s.
ADC sampling causes steps/glitches—how to isolate the INA output?
Likely cause: ADC sampling kickback injects charge into the output network, creating steps and a settle tail that looks like “sensor motion.”
Quick check: Scope the output at the sampling edge; A/B test with/without Riso/Cf; change sampling rate and observe step scaling.
Fix: Add output isolation (Riso) and a small local capacitor (Cf) or buffer; confine kickback current loop to the ADC side.
Pass criteria: Sampling spike < X mV and post-sample settling < Y ms to Z LSB (or Z%).
How to detect an open electrode reliably in production?
Likely cause: Open circuits change the effective bias/leakage signature and inflate recovery tails, even if the output “looks plausible.”
Quick check: Run an open/short/leakage script with a controlled injection step; compare response amplitude and Recovery_tau fingerprints.
Fix: Design in a giga-ohm injection network + test mode switching; classify using a combination of Itotal_est, drift slope, and τ.
Pass criteria: Open-detect hit rate ≥ X% with false positive ≤ Y%, and the unit receives a clear failure label.
Why does zero-drift/chopper INA show ripple-like artifacts with high-Z sources?
Likely cause: Chopper ripple and internal switching artifacts become visible when the source impedance is extremely high and recovery is slow.
Quick check: Check if ripple scales with chopping frequency and sampling phase; compare against a FET-input path under identical loading.
Fix: Select an architecture optimized for high-Z; tune output filtering/sampling timing without touching the sensitive node; avoid “extra” node-tied parts.
Pass criteria: Ripple < X mVpp at the defined bandwidth and settles below Y LSB within Z ms after sampling.
How to separate true sensor drift from front-end leakage drift?
Likely cause: Front-end leakage drift correlates with RH/touch and changes Itotal_est; true sensor drift typically correlates with chemistry/temperature, not handling.
Quick check: Run RH step and cable tap tests; extract Itotal_est via injection and check correlation with environment/handling.
Fix: Stabilize the front end first (clean + bake + driven guard + protection placement); only then evaluate sensor drift and calibration stability.
Pass criteria: Under RH/touch perturbations, |ΔItotal_est| < X and drift no longer correlates with RH/touch (correlation < Y).
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