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RFI/EMI-Hardened Input for INAs: RC + ESD/Clamp Strategies

RFI/EMI-Hardened Input for INAs: RC + ESD/Clamp Strategies

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This page shows how to harden INA inputs against RFI/EMI with RC + staged clamps while keeping settling, distortion, and phase behavior predictable. Use a clear coupling model, symmetry-first layout, and repeatable RF tests to set pass/fail limits for both lab validation and production.

Scope & Success Criteria

This section locks the page boundary and defines pass/fail metrics so every RC + clamp choice can be verified in the lab and protected from “works on paper” surprises.

In scope Input-side RFI/EMI hardening
  • Input coupling paths (cable/connector/PCB) and symptom signatures (drift, glitches, AM-like noise).
  • RC networks (differential / common-mode / π) that suppress RF while keeping in-band phase and settling predictable.
  • ESD/TVS/clamp strategies (staged protection) and their leakage/capacitance/nonlinearity tradeoffs.
  • Verification hooks: RF injection sanity, spur/FFT checks, step recovery, post-ESD drift re-test.
Out of scope (named only, not expanded)
  • ADC drive, anti-alias filter design, and output stability regions (covered by the ADC/AAF and output-drive pages).
  • Full-system EMC strategy (enclosure, harness, compliance test planning) beyond the input network boundary.
  • Application-level error budgets (load cell/RTD/ECG) except as constraints that drive input protection choices.

The 3 observable symptom classes (field-facing)

A) Offset / baseline drift
Typical trigger: RF near the cable/connector or finger touch. Signature: DC shift tracks RF strength or cable position (often slow, repeatable). Fast check: move the RF source or cable and observe DC shift correlation.
B) Glitch / false trigger events
Typical trigger: switching edges, EFT-like bursts, nearby radios. Signature: narrow spikes that flip comparators/filters or create outliers. Fast check: capture with a short-ground probe; compare with/without input series R damping.
C) AM-like noise / “phantom signal”
Typical trigger: strong RF carriers or common-mode disturbances. Signature: a low-frequency envelope or discrete spurs appear, even with a quiet sensor. Fast check: check FFT for stable spurs; change shielding/return path and watch spur movement.

Success criteria “4-pack” (must pass together)

1) RF injection sanity
  • Observe: RF-induced DC shift, spur(s), noise-rise.
  • Pass criteria: DC shift < X LSB (or X µV); spur < X dBc; noise-rise < X dB.
X derives from allowed output error, ADC resolution, and in-band noise budget (do not use “typical”).
2) In-band distortion controlled
  • Observe: THD/IMD under normal signal levels and expected source impedance.
  • Pass criteria: THD < X dBc; IMD3 < X dBc; amplitude error < X%.
Clamp junction capacitance and voltage-dependent behavior often dominate distortion when the input sees RF.
3) Phase / group delay predictable
  • Observe: in-band phase deviation and group-delay ripple from the chosen RC topology.
  • Pass criteria: phase error < X°; group-delay ripple < X% (or < X µs).
“Predictable” means the measured response matches the target model within guardband, across tolerance and temperature.
4) ESD / surge survivability
  • Observe: post-event offset drift, leakage increase, latch-up behavior, recovery time.
  • Pass criteria: after ESD class X, performance shift < X (offset/leakage/noise) and no functional lock-up.
A “pass” must include re-test after stress (latent leakage growth is common).

Acceptance metrics table (thresholds as placeholders)

Fill the X values from system error budgets (ADC LSB, allowable drift, band of interest, and worst-case sensor/source impedance). Keep guardband for tolerance and temperature.

Metric Why it matters Test setup Observable Pass criteria Failure pattern
RF-induced DC shift Looks like drift/offset; breaks stability and calibration. Near-field or cable-coupled RF injection. µV / LSB / ppm < X Slow baseline move tied to RF level/cable position.
Spur amplitude Creates “phantom tones” and corrupts FFT-based measurement. FFT with stable windowing and bandwidth control. dBc < X Discrete peaks at repeatable frequencies.
In-band THD/IMD Nonlinear clamps and C(V) effects translate RF to distortion. Single tone + dual tone sweep (band of interest). dBc < X Distortion worsens with RF proximity and amplitude.
Phase / group delay error Breaks timing alignment and predictable dynamics. Frequency response measurement (magnitude + phase). ° / µs < X Channel-to-channel mismatch or ripple near cutoff.
ESD class + post-stress drift Passing the zap is not enough; drift/leakage can grow. IEC test + re-test: offset/leakage/noise after stress. Class / µV / nA Class ≥ X and shift < X Works initially, then baseline drift increases (latent damage).
Threat → Symptom → Countermeasure → Test (RFI/EMI-hardened input) Four-column overview mapping RF threats to observable symptoms, countermeasures, and verification tests for instrumentation amplifier inputs. Threat Symptom Countermeasure Test RF field Cable antenna CM transient DC shift Glitches AM-like noise Symmetric RC Ccm shunt Staged clamp RF injection FFT spur check Recovery + ESD

Failure Signatures

Use these signatures to separate RFI coupling from ordinary noise, saturation, grounding mistakes, or measurement artifacts. The goal is a fast, repeatable diagnosis that points to the correct countermeasure (RC symmetry, common-mode shunt, or clamp staging).

3-step triage (15-minute diagnostic)

  1. Confirm correlation: change RF proximity or cable position. If output moves predictably, prioritize rectification or coupling-path fixes.
  2. Check common-mode sensitivity: change return/shield reference (temporary Ccm to chassis/ground). If behavior flips strongly, prioritize CM shunt and symmetry.
  3. Check clamp involvement: observe overdrive recovery after a large disturbance. If baseline takes time to return, prioritize staged clamps + series R and leakage control.

Symptom → fastest check → likely cause → next action

Observed symptom Fast check If true → likely cause Next action
DC baseline shifts with RF proximity Move RF source or cable by a few cm; watch DC shift correlation. Rectification via nonlinear junctions (ESD/clamp/input structures) or asymmetric coupling. Prioritize symmetry + clamp staging (then verify RF-induced DC shift < X).
Output shows narrow spikes / outliers Capture with short ground spring; compare with a small series R (temporary). Fast CM injection or EFT-like bursts; ringing plus threshold crossing; insufficient damping. Prioritize input series R + controlled C placement (then verify glitch rate = 0).
AM-like noise or stable spurs appear Check FFT; repeat with different shielding/return reference. Mixing/rectification; CM → DM conversion due to asymmetry; clamp C(V) effects. Prioritize CM shunt + symmetry; verify spur < X dBc and noise-rise < X dB.
After a strong event, baseline recovers slowly Apply one large disturbance; measure recovery time to stable offset. Clamp conduction + recovery; leakage growth; charge storage and slow discharge paths. Prioritize staged clamps + leakage budgeting; verify recovery < X ms and post-event drift < X.

Measurement traps (common misdiagnoses)

  • Long probe ground lead acts as an antenna and creates artificial spikes or exaggerated RF sensitivity.
  • Uncontrolled FFT settings (bandwidth/window/averaging) can turn narrow spurs into “noise rise” or hide real tones.
  • Unstable injection coupling makes improvements look random; keep injection geometry repeatable before judging RC changes.
Failure signatures: drift, glitches, AM-like noise Three waveform cards illustrating common RFI/EMI failure signatures seen at precision INA inputs: baseline drift, glitch bursts, and AM-like envelope noise with spurs. A) Baseline drift B) Glitch bursts C) AM-like noise time DC shifts with RF level time Narrow spikes / outliers time Envelope / spurs appear Check correlation Probe correctly FFT for spurs

Coupling Paths Model

RFI problems become measurable errors only when energy finds a repeatable path into the input network and then gets converted into DC shift, glitches, or in-band spurs. A minimal model keeps only the elements needed to explain where the RF enters, where asymmetry converts CM to DM, and where nonlinear junctions rectify/mix.

Three coupling paths (energy entry)

Path A — Cable antenna coupling
  • Entry: cable/connector parasitics (Ccable to environment/shield).
  • Typical result: HF common-mode rises first, then asymmetry turns CM into DM error.
  • Field cue: strong dependence on cable length, routing, and RF proximity.
Path B — Common-mode return path
  • Entry: where CM currents return (Ccm to chassis/ground, shield termination).
  • Typical result: CM is large, DM is small, but output becomes unstable/noisy.
  • Field cue: behavior flips with shield/return reference changes.
Path C — Nonlinear rectification / mixing
  • Entry: junctions with C(V) or I(V) nonlinearity (ESD/TVS/clamp, input structures).
  • Typical result: RF converts into DC shift or in-band spurs (IM products / envelope).
  • Field cue: stronger at higher RF strength and near clamp conduction edges.

Minimal equivalent elements (keep only what matters)

Rs (source impedance)
Sets RC poles and converts bias/leakage currents into DC error. Any mismatch between inputs magnifies CM→DM conversion.
Ccable (cable capacitance)
Couples RF into the line as common-mode energy. The coupling strength scales with geometry, shielding, and environment.
Rin / Cdiff / Ccm (input network)
Rin provides damping and isolation; Cdiff targets differential energy; Ccm provides a controlled CM shunt to a reference. Symmetry dominates whether CM stays CM.
Cj + clamp nonlinearity
Junction capacitance and nonlinear conduction rectify and mix RF. Even with strong RC attenuation, spurs can persist if this node still sees RF swing.

Two core conclusions (what actually drives errors)

1) Symmetry drives CM → DM conversion
  • Any mismatch in Rin/C placement, vias, or trace length makes CM disturbances appear as DM error.
  • Equal part values do not guarantee equal parasitics; return paths and geometry must also match.
2) Nonlinearity drives rectification & mixing
  • RF on junctions becomes DC shift; multiple RF components generate in-band IM spurs.
  • Keeping RF swing small at nonlinear nodes is as important as total RF attenuation.

Model → symptom mapping (fast direction to fixes)

Symptom Dominant path Dominant element Quick discriminator Next focus
DC shift / drift with RF A + C Ccable, Cj, clamp I(V) Move RF source/cable; check DC correlation. Staged clamp + symmetry
Glitches / outliers B + A Return path, Rin damping Short-ground probe; add temporary series R. Controlled CM shunt + damping
AM-like noise / spurs C (often with B) Clamp C(V), junction nonlinearity FFT spur stability vs return/shield changes. Reduce RF at nonlinear nodes
Cable → Connector → RC → Clamp → INA pins (minimal coupling model) Block diagram showing how RF couples through a cable and connector into an RC network, reaches clamp junctions, and finally the INA input pins. Highlights symmetry and nonlinearity locations. Cable Connector RC network Clamp INA pins RF Ccable Lcable Shield ESD entry Pin pad Return Rin (sym) Cdiff Ccm → Ref Rs source Cj Clamp I(V) Leakage Nonlinear IN+ IN− CM GND/Ref A: coupling symmetry nonlinear DM error

Design Targets & Constraints

Input hardening is a three-budget problem: RF attenuation must be strong enough to stop rectification and CM→DM conversion, while signal fidelity (amplitude/phase/settling) stays inside budget and protection meets survivability targets without introducing unacceptable leakage or distortion.

The three budgets (define these before choosing topology)

1) Signal fidelity budget
  • Amplitude error: in-band droop must stay < X% (derived from measurement error budget).
  • Phase / group delay: deviation must stay < X° or ripple < X% (derived from dynamics/sync needs).
  • Settling / recovery: return to valid reading < X ms/µs (derived from sampling and control timing).
2) RF attenuation target
  • Band: identify dominant aggressors (MHz–GHz) and the dominant injection path (A/B/C).
  • Node target: keep RF swing small at nonlinear nodes (clamp junctions and input structures).
  • Verify: DC shift/spur/noise-rise remain below the acceptance table thresholds.
3) Protection constraints
  • ESD level: IEC class targets (contact/air) plus post-stress re-test requirements.
  • Surge/EFT: energy handling with controlled current and safe failure behavior.
  • Failure modes: avoid latent leakage growth that shifts offset over temperature.

Parameter checklist (fill-in template)

These fields define the viable RC/clamp space. Populate with worst-case values and guardband for tolerance and temperature.

Required
  • BW_signal: band of interest (Hz/kHz).
  • Rs_source: source impedance (Ω, differential/SE equivalent).
  • Vcm_range: common-mode range including transients and tolerance.
  • settling_budget: allowed settling/recovery time.
  • ESD_level: target IEC class (contact/air) + re-test policy.
  • max_leakage: allowable leakage at temperature extremes.
Optional (useful constraints)
  • cable_length: wiring length and geometry.
  • shield_termination: single-end vs both-end.
  • aggressor_type: radio / inverter / wireless module.
  • phase_budget: channel-to-channel phase/delay tolerance.
  • imbalance: expected input mismatch (lead resistance / bridge imbalance).
  • event_current: allowable input current during stress events.

Constraint funnel (how requirements restrict topology)

Use requirements to narrow options. After the funnel output is selected, later sections only tune values inside the chosen set (no new topologies are introduced to avoid scope creep).

  • Dynamics / sync sensitive: phase and settling budgets dominate; avoid overly aggressive RC poles.
  • High RF exposure: prioritize controlled CM return and low RF swing at nonlinear nodes.
  • High ESD/surge: staged clamps and current limiting dominate; validate leakage drift across temperature.
Constraint funnel: requirements → constraints → topology set Funnel diagram mapping application requirements into electrical and protection constraints, producing a restricted set of viable input hardening topologies. Requirements Accuracy Dynamics Environment Constraints BW_signal Rs_source Vcm_range ESD_level Leakage Settling Topology set Diff RC CM shunt Staged clamp Hybrid Define budgets first Use worst-case + guardband Tune within the set

RC Topologies Toolkit

Input hardening is not “add a capacitor.” A reusable toolkit starts from what must be attenuated (DM vs CM RF), then checks what must remain predictable (distortion, phase/group delay, settling), and finally enforces symmetry so CM energy does not convert into DM error.

Building blocks (what each element actually does)

Rin (symmetric series resistors)
  • Limits event current and protects clamp/inputs.
  • Damps cable + input-C ringing and improves stability.
  • Trade-offs: thermal noise and settling/GBW burden.
Cdiff (differential capacitor)
  • Targets DM RF and fast DM edges.
  • Improves RF-to-baseband immunity when the main threat is DM.
  • Trade-offs: adds load; can increase settling time and distortion if driven hard.
Ccm (two symmetric CM shunts)
  • Targets CM RF by providing a controlled return.
  • Works best when the return reference is predictable (chassis/controlled ground).
  • Trade-offs: any asymmetry creates CM→DM conversion; return choice matters.
Rcm / return impedance control
  • Controls CM current loops and avoids “mystery return paths.”
  • Prevents random coupling into sensitive ground regions.
  • Trade-offs: excessive impedance can raise CM swing elsewhere.

Differential RC vs common-mode RC (choose by the dominant threat)

Differential RC (Rin + Cdiff)
  • Targets: DM spikes and DM RF energy.
  • Strong when: the cable acts as a DM source or the sensor output is fast/edge-rich.
  • Main risk: settling burden and distortion if Cdiff is too large for the source drive.
Common-mode RC (Ccm → reference)
  • Targets: CM injection from cable antenna coupling.
  • Strong when: symptoms depend on shield/ground/chassis conditions.
  • Main risk: asymmetry turns CM into DM; reference choice defines the return loop.

When series resistors are mandatory (limit / damp / isolate)

Limit event current
If ESD/EFT/surge stress pushes clamp or input structures into uncontrolled conduction, series R is required to keep input current within allowable limits.
Damp ringing
If cable + input capacitance creates ringing that crosses decision thresholds (glitches/outliers), series R reduces Q and stabilizes the node.
Isolate capacitive loads
If Cdiff/Ccm or clamp junction capacitance dominates the input node, series R isolates the sensor and preserves predictable settling behavior.

How tolerances become error (symmetry first, not theory)

Asymmetric Ccm
Two “equal” capacitors are not equal if placement, return vias, and loop areas differ. CM energy converts into DM error and channel-to-channel phase mismatch.
Asymmetric Rin
Resistor mismatch shifts DM poles and increases CM→DM conversion. It also creates different settling and distortion behavior between inputs.
Unequal return paths
Return imbalance is “hidden mismatch.” Even with perfect parts, asymmetric ground/chassis return geometry makes CM interference appear as DM noise/spurs.

Reusable topology cards (start ranges use magnitudes)

A) Symmetric diff RC
Use when: DM spikes or DM RF dominates; settling budget is moderate.
Pros: predictable; robust if Rin and routing are symmetric.
Main risks: source drive burden; settling/phase impact if Cdiff is too large.
Start ranges: Rin ≈ tens–hundreds Ω; Cdiff ≈ tens pF–few nF (keep pole comfortably above BW_signal).
Layout hooks: match Rin placement and trace length; keep Cdiff close to inputs.
B) Symmetric CM shunt
Use when: CM injection dominates; behavior changes with shield/chassis conditions.
Pros: strong CM RF reduction with controlled return loop.
Main risks: asymmetry creates CM→DM; reference choice can inject currents into sensitive ground.
Start ranges: Ccm ≈ tens pF–few nF (two matched parts to the same reference geometry).
Layout hooks: identical placement/return vias; minimize loop area to the reference.
C) Hybrid (diff + CM)
Use when: both CM and DM energy are present (common in real cables).
Pros: reduces RF swing at nonlinear nodes; improves predictability.
Main risks: cumulative settling/phase impact; symmetry and return control are mandatory.
Start ranges: Rin ≈ tens–hundreds Ω; Cdiff ≈ tens pF–nF; Ccm ≈ tens pF–nF.
Layout hooks: treat both inputs as a matched pair; keep return geometry identical.
D) π network (segmented)
Use when: strong RF environment or long cables; a staged approach is needed.
Pros: distributes attenuation and controls CM return and DM filtering together.
Main risks: tolerance/placement mismatch becomes phase and CM→DM error; over-filtering hurts dynamics.
Start ranges: Rseries ≈ tens–hundreds Ω; Ccm/Cdiff in pF–nF range (validated against settling budget).
Layout hooks: keep the two CM shunts symmetric; enforce shortest return loops.
E) Connector-first CM control
Use when: RF enters mainly at the connector; cable is the antenna.
Pros: shunts RF before it reaches inner nonlinear nodes; reduces rectification risk.
Main risks: return reference errors create new coupling paths; long returns reduce effectiveness.
Start ranges: small Ccm near connector (pF–hundreds pF) + inner Rin/Cdiff as needed.
Layout hooks: keep the return loop tight to chassis/controlled reference near connector.
F) High-Rs source friendly
Use when: sensor/source impedance is high and settling is tight.
Pros: avoids overloading the source while still providing damping/isolation.
Main risks: insufficient RF suppression if C values are too small; CM control still needed.
Start ranges: Rin often stays modest; Cdiff kept lighter (pF–low nF) with validation against noise/settling.
Layout hooks: maximize symmetry; minimize leakage paths around high-impedance nodes.
Topology Gallery (RC input hardening templates) Six small block diagrams showing reusable RC topologies for EMI/RFI hardening: differential RC, common-mode shunt, hybrid, pi network, connector-first segmentation, and high source impedance friendly filtering. Topology Gallery A) Diff RC IN+ IN− Rin Rin Cdiff B) CM shunt IN+ IN− Ccm Ccm Ref C) Hybrid IN+ IN− Rin Rin Cdiff Ccm Ccm D) π network R R Ccm Ccm Cdiff E) Segmented Conn Ccm Rin Ccm Cdiff F) High-Rs Rs Rin Cdiff Ccm

ESD / Clamp Strategies

“Passing ESD” is not enough. A production-ready clamp chain must handle energy without creating long-term measurement error. The key is staging (energy vs speed), placement (short loops), and return closure (where currents go).

Staged protection (energy → speed → last line)

Level 1 — Connector TVS (energy)
  • Job: absorb/divert large stress energy at the entry.
  • Why here: shortest loop to the chosen reference; prevents current from entering sensitive inner routes.
Level 2 — Board-level fast clamp (speed)
  • Job: fast, low-loop clamp to protect inner nodes from overshoot.
  • Why here: enables tighter symmetry and controlled return geometry.
Level 3 — IC input clamp (last line)
  • Job: protect internal structures in corner events.
  • Rule: never rely on this level for energy handling; it increases distortion and recovery risks.

Clamp parameters that affect measurement (map to observable behavior)

Cj (junction capacitance)
Larger Cj increases HF coupling and raises CM→DM sensitivity when placement/returns are not symmetric.
Ileak (reverse leakage)
Leakage through Rs/Rin becomes input offset and drift. Temperature extremes can dominate accuracy even when ESD “passes.”
Rdyn (dynamic resistance)
Higher Rdyn leaves larger residual voltage during events, pushing inner nodes into overload and increasing recovery time.
Vclamp / threshold
Too low causes early conduction (distortion); too high risks overstress. The correct choice depends on allowed input current and headroom.
Recovery behavior
Slow recovery appears as baseline shift or long tails after stress. Production checks must include post-event offset and drift.

Clamp to where (close the return loop, not a “ground philosophy”)

To chassis / shield reference
Works well for CM energy near the connector. Requires a short, low-inductance return so current does not enter sensitive board ground.
To analog ground
Can be controlled inside the board, but large event currents may pollute local ground and create measurement artifacts if the loop is not isolated.
To supply rails
Routes stress into the power network. Requires explicit rail absorption and local decoupling paths to avoid spreading transients.

Protection device selection fields (what to ask / record)

Field Why it matters Watch-out Verify with
Cj (typ/max) Sets RF coupling and symmetry sensitivity. Asymmetry → CM→DM error, phase mismatch. RF injection + spur/DC shift check.
Ileak (temp) Becomes offset/drift via Rs/Rin. Post-ESD leakage growth is a hidden failure. Hot/cold offset + drift re-test.
Vclamp / Vbr Defines headroom and overstress risk. Too low → distortion; too high → damage risk. Overload recovery and THD check.
Rdyn Controls residual voltage during events. High Rdyn increases inner node stress. Event waveform and recovery time.
IEC rating Sets survivability class requirement. Must include post-stress accuracy re-test. Pre/post accuracy + leakage checks.
Staged ESD/Clamp Chain (Connector → Series R → Inner Clamp → INA) Cross-section diagram showing a staged protection chain: connector TVS for energy, series resistors for limit/damp, inner fast clamp for speed, and INA pins as the last line. Return loop arrows illustrate where currents close. Staged protection cross-section Connector Series R Inner clamp INA pins TVS (energy) Chassis/Ref Cable Rseries + Rseries − limit/damp Fast clamp Cj / Rdyn To Ref/Rail IN+ IN− Last line Return loop (keep short) Rail injection risk

Predictable Distortion & Phase

The goal is not “add RC and hope.” The goal is predictable impact: distortion and phase changes that can be modeled, measured, and accepted with clear pass criteria. That requires locating the nonlinear nodes, controlling RF swing at those nodes, and verifying behavior with the same test matrix across builds and temperature.

Nonlinearity map (where distortion really comes from)

C(V) of protection junctions
  • Observable: AM-like noise, spur growth, or THD increase under RF exposure.
  • Dominant knob: RF swing at the clamp/input node (Rin isolation, staged placement, symmetry).
  • Quick isolation: reduce injected RF or move Ccm/Cdiff position; compare spur/THD deltas.
Soft conduction near clamp threshold
  • Observable: distortion rises sharply with input amplitude or with CM steps.
  • Dominant knob: clamp threshold and series R that limits edge current and node swing.
  • Quick isolation: sweep amplitude; look for a knee where THD/IMD changes slope.
Dynamic resistance & recovery tails
  • Observable: baseline shift or long recovery after a transient.
  • Dominant knob: staged protection (energy handled early), return loop size, and isolation R.
  • Quick isolation: step/overload test; measure recovery time and residual offset.

Phase & group delay (keep band behavior predictable)

Differential pole drivers
Rin and Cdiff define where DM attenuation starts. If the pole is pushed too low, settling and in-band phase shift become large.
Common-mode pole drivers
Ccm only works as intended when the return reference is controlled. Return geometry and symmetry dominate CM→DM conversion and phase mismatch.
Predictability rule
The pole location is only “predictable” when both input halves see the same parts, the same parasitics, and the same return loop geometry.

Engineering modeling path (what to characterize, in order)

Step 1 — Small-signal FRF
Measure in-band magnitude, phase, and group-delay ripple for the full input network. This becomes the baseline “predictable” signature.
Step 2 — Large-signal step & overload recovery
Stress the input with realistic steps and CM disturbances. Record recovery time, residual offset, and whether recovery differs between IN+ and IN− paths.
Step 3 — In-band THD / two-tone IMD
Compare distortion with and without the protection network at the same output level. A clamp-induced knee indicates soft conduction or C(V) modulation.
Step 4 — RF injection sensitivity
Inject RF (CM and DM) and log baseband DC shift, noise lift, and in-band spurs. This validates that RF swing at nonlinear nodes is controlled.

Four-step verification matrix (Test → Setup → Observable → Pass criteria)

Test Setup Observable Pass criteria (placeholders)
Small-signal FRF Low-amplitude sweep across BW_signal Magnitude ripple, phase shift, group delay ripple |ΔGain| < ___ dB; |ΔPhase| < ___°; GD ripple < ___
Step / overload Step/CM pulse representative of system transients Recovery time, residual baseline shift, ringing Recovery < ___; residual shift < ___; no long tail
THD / IMD In-band sine and two-tone at target levels THD/IMD delta vs baseline ΔTHD < ___ dB; ΔIMD < ___ dB (no knee)
RF injection CM + DM injection with defined coupling fixture DC shift, noise lift, in-band spur Shift < ___; noise lift < ___; spur < ___
Model → Test → Spec closed loop Block diagram showing a closed loop from nonlinear model elements to test methods and then to acceptance specs: model nodes like C(V) and Rdyn feed tests like FRF and THD, which map to specs like phase, THD, shift, and recovery. Arrows close the loop for iteration. Predictability loop Model Test Spec C(V) Rdyn Threshold Symmetry FRF Step THD / IMD RF inject Phase THD Shift Recovery Iterate

Leakage & Bias Error Budget

ESD can “pass” while accuracy fails. Leakage from protection parts and PCB surfaces combines with input bias current and turns source impedance into offset and drift. A usable design must budget leakage across temperature and control the leakage paths with guarding and cleanliness.

Minimal, reusable error budget (fill-in worksheet)

Verror = Itotal_leak × Req_source
Req_source should represent the effective resistance seen by the leakage and bias currents at the input node. The key is to track leakage at the temperature points that matter, not only at room conditions.
Req_source = ___ Ω (effective)
I_leak_TVS(max,T) = ___ A
I_leak_inner(max,T) = ___ A
I_surface(max,T) = ___ A
I_bias_INA(max,T) = ___ A
Itotal_leak = ___ A → Verror = ___ V

Temperature behavior (why drift appears “suddenly”)

Hot conditions
Leakage increases dramatically and turns into measurable offset and drift through Req_source. If drift grows with temperature, leakage is a primary suspect.
Cold conditions
Recovery can slow down and moisture-related effects can become more visible during transitions. Repeatability improves only with controlled cleanliness and guarding.
Rule for sign-off
Always re-check offset and drift after stress (ESD/EFT) at temperature points. A “pass” is defined by post-stress accuracy, not only survivability.

Control actions (guarding and leakage discipline)

Guard ring around high-impedance nodes
  • Goal: intercept surface leakage before it reaches the sense node.
  • Rule: keep the guard continuous and symmetric around IN+ and IN− routes.
  • Verify: humidity/contamination sensitivity test and offset repeatability.
Cleanliness around input network
  • Goal: remove flux residue and ionic contamination that forms leakage films.
  • Rule: treat the TVS/ESD + Rin/C network area as a high-impedance region.
  • Verify: compare offset/drift before and after controlled cleaning/drying.
Leakage-aware placement
  • Goal: prevent clamp leakage from flowing through large source resistances.
  • Rule: keep high-leakage parts away from ultra-high impedance inputs; use staging to reduce stress on inner clamps.
  • Verify: hot offset/drift delta and channel-to-channel consistency.

Production-ready verification hooks

Post-stress accuracy check
After ESD/EFT stress, re-measure offset and drift. Pass criteria must include: offset < ___ and drift < ___ across temperature.
Humidity / contamination sensitivity
Validate that offset does not jump with humidity or handling. If touch/airflow changes the reading, surface leakage paths are likely active.
Channel consistency
Compare channel offsets and hot drift. Large spread indicates mismatch in leakage, guarding, or placement symmetry.
Leakage paths map Diagram mapping leakage sources: connector TVS leakage, inner clamp leakage, PCB surface leakage from residue and moisture, and the guard ring used to intercept leakage before it reaches high-impedance INA inputs. Arrows show leakage currents flowing through source resistance causing Verror. Leakage paths map TVS Ileak RC net Req Clamp Ileak INA Bias PCB surface Moisture Residue IN node Guard Verror = I × R

Layout & Return Path

An input network can be correct on the schematic but fail on the PCB when symmetry breaks, return paths become uncontrolled, or the protection zone leaks RF current through precision references. This section locks the solution to the input area: zoning, symmetry, controlled Ccm return, and a clear shield boundary.

Placement zoning (keep RF energy in the protection area)

Connector zone
Highest RF and ESD energy. Place entry components here and avoid letting return currents spread into the precision area.
Clamp zone
TVS and staged clamps belong here. The Ccm return reference must be short and deliberate. Do not route RF return through sensitive analog references.
Precision zone
INA pins and the last-stage RC belong here. Keep this zone free of RF return currents and keep IN+ and IN− fully symmetric.

Symmetry & return path rules (prevent CM→DM conversion)

Symmetry means equal impedance
Match IN+ and IN− length, via count, component placement, and local parasitics. Any asymmetry turns common-mode RF into differential error.
Ccm return must be short and controlled
Ccm only helps if its return loop is tight. A long or shared return path injects RF into sensitive references and creates unpredictable offsets and spurs.
Define a shield boundary in the input area
Keep the protection return reference separate from the precision reference. Use a clear boundary and a deliberate tie point within the input area.

Layout checklist (priority-ordered, input area only)

Priority Action Quick check Failure signature
P0 Mirror IN+ / IN− component placement (Rin, C, via count) Overlay the two routes; verify equal geometry and via count CM injection becomes DM offset/spurs; channel mismatch
P0 Keep Ccm return loop tight to its reference point Trace the loop; confirm shortest path and minimal area RF sensitivity changes with cable/hand; unpredictable drift
P0 Do not route protection return through precision reference Follow return copper; ensure it stays in protection area Noise lift / spur under RF; baseline shifts after events
P0 Place TVS close to connector; stage energy early Connector→TVS trace shortest; minimal stubs Inner clamps overstress; post-event drift/leakage increases
P1 Keep DM RC nearest to INA pins and symmetric Check Rin/Cdiff placement and equality on both sides In-band phase mismatch; settling differences between channels
P1 Keep other high-speed nets out of the input keepout Enforce spacing around IN routes and clamp node Noise floor rises with digital activity; spurs at data rates
P1 Use input-area stitching to define the return boundary Check that stitching supports the chosen reference path RF current detours; sensitivity varies with board mounting
P2 Guard high-impedance input nodes consistently Guard ring continuity and symmetry around IN routes Humidity/touch sensitivity; offset jump with contamination
Placement zoning (input area) Top view of the input area partitioned into connector, clamp, and precision zones with a star tie point and short controlled Ccm return. Arrows show allowed return paths and a forbidden return across the precision zone. Placement zoning (input area) Connector zone Clamp zone Precision zone Connector TVS Rin+ Rin− Ccm Ccm Inner clamp INA Cdiff * Tie point No RF return

Validation Playbook

RFI immunity must be verified with repeatable injection methods, stable fixtures, and objective observables. This playbook focuses on input-side injection and logs: DC shift, noise lift, in-band spurs, and recovery time. Common measurement traps are listed to prevent false confidence.

Input-side injection methods (repeatable options)

Near-field probe
  • Injection point: scan the connector and clamp zones first, then precision zone edges.
  • Strength control: fixed distance and fixed orientation; log position ID.
  • Repeatability knob: use a simple spacer to keep distance consistent.
Capacitive injection
  • Injection point: cable line, connector pin, or the clamp-side node (avoid probing-induced asymmetry).
  • Strength control: injection capacitor value + source level.
  • Repeatability knob: fixed capacitor placement and lead length.
Cable injection
  • Injection point: the cable segment near the connector for the most realistic coupling.
  • Strength control: clamp position + drive level + frequency sweep.
  • Repeatability knob: fix the cable shape and mounting position.

Observables to log (the four-metric set)

DC shift
Record baseline movement during injection and after removal. This captures rectification and leakage-driven effects.
Noise lift
Compare noise density or integrated noise in the same measurement bandwidth before and during injection.
In-band spur
Check FFT for new tones or sidebands in the signal band. Log frequency and amplitude deltas.
Recovery time
Measure how quickly the output returns to baseline after injection stops. Long tails indicate clamp recovery or leakage changes.

Test record table (Setup / Point / Sweep / Level / Pass)

Setup ID Method Injection point Sweep Level Observable Pass criteria
S___ Probe Clamp zone edge ___ to ___ MHz Distance ___ / level ___ Shift / spur Shift < ___; spur < ___
S___ Cap Cable line ___ to ___ MHz Cin jigs ___ / level ___ Noise lift Lift < ___
S___ Cable Near connector ___ to ___ MHz Clamp pos ___ / level ___ Recovery Recovery < ___

Measurement traps (avoid self-deception)

Probe ground lead becomes an antenna
Long ground leads create pickup and false “sensitivity.” Use short ground springs and keep the measurement loop area minimal.
Bandwidth and windowing hide spurs
If the analyzer/FFT settings are inconsistent, spurs can vanish or appear. Use the same bandwidth and windows for baseline and injected runs.
Injection path is not stable
Cable bending, clamp position, and coupler placement change coupling. Fix the geometry and log an ID for each fixture configuration.
Only time-domain or only spectrum misses the root
Time-domain shows recovery and baseline shifts; spectrum shows spurs and modulation. Always log both for the same injection sweep.
RFI validation setup (input-side) Block diagram showing RF source feeding optional coupling methods (probe, capacitor, cable clamp), injecting into a cable and connector into the DUT input chain (TVS, RC, clamp, INA). Measurement blocks show time-domain and spectrum logging. RFI validation setup (input-side) RF source Coupler Probe Cap Clamp Cable Connector DUT TVS RC Clamp INA Measurement Time / FFT Fix geometry Log sweep

Production-Ready Checklist & Selection Notes

This section turns the input-side RFI/EMI hardening approach into a production-ready flow: selection priorities, supplier inquiry fields, incoming lot controls, and minimal spot-check tests that catch drift and RF sensitivity before volume build. Scope is limited to the input chain: connector → protection → RC → INA pins.

Selection priority (what matters first for precision + immunity)

Rule of thumb: prioritize error sources that age and drift
  1. Leakage vs temperature (dominant for DC offset and drift through source impedance)
  2. Capacitance + C(V) (drives phase, settling, and distortion predictability)
  3. Clamp behavior (Vclamp / Rdyn / recovery tail under events)
  4. Tolerance & symmetry (CM→DM conversion and channel-to-channel mismatch)
  5. ESD / surge level (survivability target, staged across zones)
  6. Package cleanliness (humidity/contamination sensitivity and long-term drift)
Component-specific selection notes (input chain only)
  • Connector-side TVS: choose for energy handling; accept higher Cj/leakage but keep it out of the precision zone.
  • Inner ESD/rail clamps: choose for low leakage and stable parasitics; prevent post-event drift and rectification.
  • Series resistors (Rin/Rcm): thin-film preferred for stability; match both legs to preserve symmetry.
  • Signal capacitors (Cdiff/Ccm): C0G/NP0 preferred for predictable phase/distortion; control tolerance to protect symmetry.
  • Feedthrough parts (optional): use when high-frequency return must be shortened; verify mechanical fit and layout window.

Incoming & lot consistency controls (catch distribution, not “typical”)

Production failures commonly come from lot-to-lot leakage spread, Cj spread, and assembly contamination that increases surface leakage. Require distribution-oriented data and perform small-sample checks under temperature when DC accuracy is critical.

Incoming checks (recommended minimum)
  • Ileak distribution: measure at room and hot (e.g., 85 °C / 125 °C) per lot.
  • Cj / C(V) sanity: sample a few parts at the intended bias range.
  • Clamp behavior: spot-check Vclamp at a defined pulse current (fixture-defined).
  • Cleanliness risk: watch for moisture/flux residues near high-impedance inputs; log process controls.
Lot acceptance table (placeholders)
Item Sample size Condition Observable Limit (placeholder)
TVS / ESD leakage n = ___ 25°C + hot Ileak < ___
Capacitance sanity n = ___ Bias range Cj / C(V) ΔC < ___
Clamp behavior n = ___ Fixture pulse Vclamp < ___

BOM inquiry template (supplier must provide these fields)

Request fields that map directly to offset/drift and RFI behavior. Missing leakage and bias-dependent capacitance data makes prediction and acceptance impossible.

Component Must-provide fields Why it matters
TVS / ESD / Clamp Ileak vs T (room + hot), Cj / C(V), Vclamp @ Ipp, Rdyn, recovery notes, IEC level, package notes Predicts DC drift, rectification sensitivity, clamp tails, and lot-to-lot behavior
Series resistors (Rin/Rcm) Technology (thin-film), tolerance, TCR, voltage coefficient (if available), power derating Controls symmetry, drift, and nonlinearity-driven IMD
Cdiff / Ccm Dielectric, tolerance, bias behavior (if not C0G), microphonic notes (if relevant) Preserves predictable phase/settling and channel match
Feedthrough (optional) ESL / equivalent circuit, mechanical size, DC resistance/current rating Shrinks high-frequency return loops and reduces layout sensitivity

Production spot-check plan (minimal tests that catch real failures)

Use a small, repeatable set of checks that correlates with field issues: leakage drift with temperature, RF sensitivity, and post-ESD drift. Pass criteria are placeholders and must be set by the system noise/accuracy budget.

Test Setup Observable Pass criteria (placeholder)
Hot drift screen Short dwell at hot point Δoffset / baseline shift |Δ| < ___
RF spot-check Fixed 2–3 freq points, fixed injection point Shift / spur / recovery Shift < ___; spur < ___; recovery < ___
ESD sample + retest Lot-based sampling, then functional retest Δoffset / Δnoise / recovery tail Δ < ___ (pre vs post)
Cleanliness audit Input-area inspection and process log Residue / moisture indicators No residue; process in control

Reference example part numbers (starting points only)

These examples help speed up datasheet lookup and prototyping. Final selection must be driven by the inquiry fields and pass criteria above. Use staged protection: connector-side energy handling plus inner low-leakage protection for precision.

Low-leakage / low-cap ESD (inner stage)
  • TI: TPD4E1B06 (multi-channel ESD array)
  • Nexperia: PESD5V0X1UALD (single-line ESD)
  • Nexperia: PESD5V0S2BT (dual-line ESD)
  • Nexperia: PESD5V0X2UM (dual-line ESD)
Connector-side TVS / arrays (energy stage)
  • Semtech: LCDA05 (TVS array family example)
  • Littelfuse: AQ1205-01LTG (TVS array example)
  • Semtech: RClamp0542T (rail-clamp array example)
Feedthrough + C0G examples (EMI + predictability)
  • Murata: NFM31KC153R1H3L (feedthrough capacitor example)
  • Murata: GRM1555C1H101JA01D (C0G/NP0 capacitor example)
  • Murata: GRM1555C1H471JA01D (C0G/NP0 capacitor example)
Thin-film resistor examples (symmetry + stability)
  • Vishay: TNPW080549R9BEEA (49.9 Ω example)
  • Vishay: TNPW0805100RBEEA (100 Ω example)
Factory flow (input chain hardening) Block diagram of a production-ready validation flow: incoming distribution checks, ICT, functional tests, RF spot-check, ESD sampling, and retest. Feedback arrows indicate design/process review loops. Factory flow (production readiness) Incoming Ileak / Cj ICT Functional offset / noise RF spot-check shift / spur ESD sample IEC Retest drift Review RC / layout Process cleanliness

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FAQs: RFI/EMI-Hardened Input for INAs

Short, production-oriented answers that stay within the input chain boundary (connector → protection → RC → INA pins). Each answer uses a fixed 4-line format for fast troubleshooting and acceptance.

Why does the output shift when a phone/radio gets close to the cable?
Likely cause:
Cable acts as an RF antenna; common-mode RF converts to differential via asymmetry and rectifies in protection/input junctions.
Quick check:
Move the RF source distance/power; if output shift is monotonic with RF strength, the symptom is RF-induced (not random noise).
Fix:
Add/optimize Ccm return (short loop) and enforce symmetry (matched Rin + matched routing) before increasing capacitance.
Pass criteria:
RFI-induced DC shift |ΔVout_RF| < X (system accuracy budget) across the defined distance/power sweep.
Why does adding input RC reduce RF issues but worsen settling?
Likely cause:
RC adds poles/zeros at the input; RF attenuation improves but time constant consumes settling/step response budget.
Quick check:
Apply a differential step (or fast stimulus change) and measure time-to-within-error at the ADC/measurement point.
Fix:
Shift RC corner up (reduce C first), keep Rin for damping/limit current, and move more RF work to Ccm return and symmetry.
Pass criteria:
Settling error < X within T_settle (system dynamic requirement) while |ΔVout_RF| remains < Y.
Differential C vs common-mode C: which one should be larger first?
Likely cause:
Most RF enters as common-mode on the cable; converting it to differential is mainly a symmetry/return-path problem.
Quick check:
Compare two builds: (A) increase Cdiff, (B) add modest Ccm with a short return; observe which reduces output shift more.
Fix:
Start by making Ccm effective (short return loop + controlled reference point), then add minimal Cdiff for band-edge shaping if needed.
Pass criteria:
Common-mode RF sensitivity improves by ≥ X dB while band-edge phase/settling stays within Y.
Why does TVS “fix ESD” but introduce offset drift over temperature?
Likely cause:
TVS reverse leakage rises with temperature; leakage through source resistance creates a temperature-dependent input offset.
Quick check:
Repeat a zero-input test at hot; if offset grows with temperature and depends on source impedance, leakage is dominant.
Fix:
Use staged protection: connector-side TVS for energy, inner low-leakage ESD/clamp near INA; keep the precision node clean and guarded.
Pass criteria:
Hot offset drift from protection leakage < X (system DC error budget) over the specified temperature range.
How to choose series resistors without adding too much noise/error?
Likely cause:
Series R is needed for current limiting and damping, but excessive R converts bias/leakage to offset and adds thermal noise.
Quick check:
Measure (A) zero offset shift vs temperature and (B) noise density; compare two R values differing by ~2×.
Fix:
Start with “small but useful” Rin (damping/limit) and rely on symmetry + Ccm return for RF; match both legs and keep the node clean.
Pass criteria:
Added error from Rin (offset + noise) < X, while clamp current remains below Y during defined events.
Why does the circuit pass ESD once but fail after re-test (latent damage vs leakage)?
Likely cause:
ESD can shift leakage or junction behavior without immediate hard failure; post-event drift/noise rises even when basic function remains.
Quick check:
Compare pre/post ESD: (1) zero offset at hot, (2) noise floor, (3) recovery tail after a small step.
Fix:
Move energy handling outward (connector zone), keep inner clamps low-leakage, and ensure short return loops to prevent overstress of inner nodes.
Pass criteria:
Post-ESD deltas: |Δoffset| < X, Δnoise < Y, recovery < Z (defined by production limits).
How to place Ccm: to analog ground or chassis ground?
Likely cause:
Ccm is a high-frequency return element; the wrong reference point forces RF current through sensitive analog return paths.
Quick check:
Probe output shift while moving the Ccm return point; improvement correlates with the shortest, most controlled RF return loop.
Fix:
Return Ccm to the local “RF sink” node (often chassis/quiet plane near connector) with a very short path; avoid routing RF return through precision analog ground.
Pass criteria:
RF return current does not measurably disturb the precision reference node; |ΔVout_RF| < X across the sweep.
Why do two channels behave differently with the same RC values (tolerance/asymmetry)?
Likely cause:
Small mismatches (R/C tolerance, routing, vias, clamp parasitics) convert common-mode RF to differential and shift poles.
Quick check:
Swap the RC/clamp parts between channels; if the behavior follows parts/layout, asymmetry is confirmed.
Fix:
Match both legs (same package/placement), tighten tolerance for the sensitive elements, and replicate return paths and via patterns.
Pass criteria:
Channel-to-channel RFI-induced error mismatch < X and phase mismatch < Y within the band.
How to test RFI immunity without a GTEM cell?
Likely cause:
RFI sensitivity is dominated by the input chain and cabling; controlled local injection can reproduce the failure signatures.
Quick check:
Use a repeatable injection: near-field probe over cable/connector, or capacitive injection to the cable shield/CM node, with fixed geometry.
Fix:
Define a shop-floor sweep set (f1/f2/f3, Pinj1/Pinj2, power steps) and validate improvements against the same fixture and geometry.
Pass criteria:
Across the defined sweep, |ΔVout_RF| < X and spur delta < Y, with recovery < Z.
Why does the spur appear only at certain RF frequencies (mixing/rectification)?
Likely cause:
Nonlinear junctions (clamps/input structures) mix RF with internal tones/clock edges; only certain frequencies land in-band.
Quick check:
Sweep RF frequency and log the spur location/amplitude; if spur tracks |fRF ± fX|, mixing is confirmed.
Fix:
Reduce RF at the nonlinear element (better Ccm return + symmetry + staging), and avoid operating clamps at the conduction edge in normal conditions.
Pass criteria:
Worst-case in-band spur delta < X dBc (or X µV_rms) across the defined RF sweep.
What’s the common probing mistake that makes RFI look worse than it is?
Likely cause:
Probe ground leads and large loops act as antennas, injecting or reshaping RF and creating artifacts that are not present in normal operation.
Quick check:
Repeat the measurement using a short ground spring/coax method; if the “RFI symptom” changes dramatically, the probe is part of the problem.
Fix:
Use minimal-loop probing, fixed fixture geometry, and consistent bandwidth/filters; measure at the acceptance node (ADC input/output spec node).
Pass criteria:
Measurement repeatability: Δresult between probe methods < X; conclusions do not flip with probing style.
How to set pass/fail limits for “RFI-induced error” in production?
Likely cause:
Without a defined injection setup and an observable metric, pass/fail becomes inconsistent and misses the real field failure mode.
Quick check:
Define a fixed sweep set (f1/f2/f3, injection point, geometry, power steps) and record the metric: Δoffset, spur delta, recovery time.
Fix:
Set limits directly from the system budget: allocate allowed RFI error (X) and ensure it fits within DC accuracy + noise margin.
Pass criteria:
Across the defined sweep, max(|ΔVout_RF|) < X and worst spur delta < Y, with recovery < Z (all budget-derived).
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